JPH07295676A - Dynamic circuit - Google Patents

Abstract

PURPOSE:To provide the dynamic circuit which actualizes more excellent power management. CONSTITUTION:Under control based upon the switching signal from a control circuit part 15, a storage circuit 14 is not added to the output node 13 of a clocked inverter part 12 in high-speed clock operation, but in low-speed clock operation, the storage circuit part 14 is added. In the high-speed clock operation, the storage circuit part 14 is not added to the output node 13 under the control based upon the switching signal from the control circuit part 15 and the dynamic operation of the clocked inverter part 12 is performed to place its output node 13 in a dynamic node state. In the low-speed clock operation, the storage circuit part 14 is added to the output node 13 with the switching signal from the control circuit part 15 to enter a static circuit state, and the output node 13 is placed in a static node state. Consequently, malfunction is prevented and the power consumption is reduced.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to dynamic circuits.

[0002]

As is well known, recently, as represented by a CPU (Central Processing Unit) of a computer,
In order to increase the calculation processing speed and the like, the circuit operation speed is increasing at a very fast pace. On the other hand, in order to realize the high-speed operation of the circuit, the operation clock becomes high-speed, and the AC power consumption of a circuit, for example, an integrated circuit (IC) configured in proportion to this increases, and the power consumption of this circuit increases Is becoming a big issue.

Therefore, the power consumption is suppressed by operating the functional blocks not used by the operating IC with a low-speed clock to operate only the required functional blocks with the high-speed clock. Active power management technology to reduce power consumption is drawing attention.

On the other hand, conventionally, for example, a dynamic circuit called a clocked inverter as shown in FIG. 7A is known. It consists of pMOS4,60 and nMOS5,61 connected in series.
5, a common input signal is applied via an input node 80, and a control signal (for example, a clock signal CLK and its inverted signal CLK) is applied to the gates of the pMOS 60 and the nMOS 61.

PMOS 60 and nMOS 6 are controlled by a control signal.
1 is turned off, the supply of the power supply potential to the sources of the pMOS 4 and the nMOS 5 is cut off, and the signal on the output node 6 is dynamically held by the parasitic capacitance. The output node 6 is input to the gate of the MOS transistor at the next stage (not shown), but the circuit may be the input gate of a dynamic circuit similar to that shown in FIG. 7A. Also, the next M
The gate of the OS transistor does not have to be the gate in the dynamic circuit.

FIG. 7B shows another example, that is, an example of a clocked inverter using an analog switch. The analog switch is composed of pMOS 70 and nMOS 71, and whether or not to transmit the inverter output, which inverts the signal applied to the input node 80, to the output node 6 is determined by the control signal applied to the gates of the pMOS 70 and the nMOS 71.

PMOS 70 and nMOS 7 are controlled by a control signal.
1 is turned off, the signal supply to the output node 6 is cut off, and the signal on the output node 6 is dynamically held by the parasitic capacitance. The output node 6 is input to the gate of the MOS transistor at the next stage (not shown), but the circuit may be the input gate of a dynamic circuit similar to that shown in FIG. 7A.

Further, the dynamic circuit as shown in FIGS. 7A and 7B has a lower limit operating frequency. That is, when the clocked inverter or analog switch is turned off for a long time by the above control signal,
The charge on the output node 6 decreases due to the off leak current of the transistor, the reverse bias leak current of the pn junction, etc., and the potential thereof changes. This fluctuation is caused by the threshold voltage of the circuit of the next stage and the threshold voltage (V
If it exceeds _th ), the circuit or transistor in the next stage malfunctions.

Therefore, when the clocked inverter and the analog switch are turned off for a long time, there is an upper limit on the length of time. Hereinafter, this phenomenon will be referred to as the lower limit operating frequency characteristic. When the control signal is a clock signal, it can be regarded as the lower limit of the repetition frequency or the limit of the duty ratio.

As a method of improving the above lower limit operating frequency, it is known that the output node 6 is made into a static node by adding a feedback circuit section 3 to the output node 6, as shown in FIG. . The feedback circuit unit 3 includes two sets of pMOSs connected in series.
7 and an nMOS 8 are formed, and the input / output nodes 9 and 10 of the feedback circuit unit 3 are connected to the output node 6 of the dynamic circuit 1. The feedback circuit section 3 holds the signal by latching the signal at the output node 6. The clocked inverter circuit 2 of FIG. 8 having the same configuration as the circuit shown in FIG. 7A may be replaced with the circuit shown in FIG. 7B.

By using a static circuit, the problem of the lower limit operating frequency can be solved. However, when the static circuit is operated at a frequency higher than the lower limit operating frequency of the dynamic circuit 1 before being made into a static circuit,
Since the unnecessary feedback circuit unit 3 also operates at this frequency, a problem arises in that much power is consumed as compared with the case where the feedback circuit unit 3 is not added.

On the other hand, when the dynamic circuit is adopted, there is a problem that the lower limit operating frequency naturally causes a limit (lower limit) to reduce the power consumption by the active power management as described above.

Therefore, there has been a strong demand for realization of a circuit system capable of better power management.

It is difficult to accurately measure the lower limit operating frequency of a dynamic circuit before it is made into a static circuit in consideration of temperature, power supply voltage, noise, manufacturing variation, environment in which the circuit is used, etc. It is decided including the margin in consideration of. Dynamic node Depending on the parasitic capacitance value, for example, in the case of a node in an IC, about 1 MHz may be considered as the lower limit operating frequency. Of course, due to the recent fine processing technology, the capacitance value parasitic on the dynamic node is decreasing, and the off-leakage current of the transistor is increasing, so that the frequency tends to be higher.

In the following (including the embodiments), a frequency higher than the lower limit operating frequency of the dynamic circuit before being made into a static circuit is referred to as a high-speed clock for convenience, and a frequency lower than the lower limit operating frequency is referred to as a low speed for convenience. Call it a clock. The low-speed clock frequency is 0 Hz, that is, the operation stop state is also included. Further, the lower limit operating frequency is set to a value including a margin in consideration of certainty of circuit operation.

[0016]

SUMMARY OF THE INVENTION The present invention has been made in view of the above situation, and its object is to use an original dynamic circuit when operating with a high-speed clock and to operate with a low-speed clock. In this case, a static circuit or a charge-holding capacitance can be added to form a low power consumption circuit to reduce the power consumption to zero or sufficiently reduce it and prevent malfunctions to improve the power consumption. -To provide a dynamic circuit that enables management.

[0017]

A dynamic circuit according to the present invention comprises an output node of a main circuit section which operates dynamically,
A memory circuit section that can be added to this output node;
A state in which the control circuit section controls whether or not the storage circuit section is added to the output node, and the storage circuit section is not added to the output node when a high-speed clock is operated by a switching signal from the control circuit section. The storage circuit section is added to the output node during operation of a low-speed clock, and the storage circuit section is further controlled by a switching signal from the storage section and the control circuit section. It is characterized in that it is configured to include a switch unit that opens and closes, and an addition state of the storage unit to the output node is controlled by opening and closing the switch unit. It is characterized in that the output node is changed from a dynamic node state to a static node state by adding it to a node. In addition, the storage circuit unit is characterized in that the storage circuit unit is provided with a capacitance as a storage unit, further, the control circuit unit whether the addition of the storage circuit unit according to the power consumption suppression mode signal. It is characterized in that it outputs a signal for controlling.

[0018]

The dynamic circuit configured as described above is
The memory circuit section is not added to the output node of the main circuit section that operates dynamically under the control of the switching signal from the control circuit section when the high-speed clock operates, and the memory circuit section is added when the low-speed clock operates. There is.
As a result, during the operation of the high-speed clock, the storage circuit section is not added to the output node under the control of the switching signal from the control circuit section, and the original dynamic operation is performed only by the main circuit section and the output node becomes a dynamic node. When the low-speed clock is operating, the memory circuit is added to the output node by the switching signal from the control circuit to make it a static circuit (when a feedback circuit is added) or the lower limit operating frequency of the dynamic circuit is improved. (When adding capacitance)
Becomes As a result, it is possible to prevent erroneous operation during operation of the low-speed clock, and to reduce the power consumption of the memory circuit unit during operation of the high-speed clock.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. First, a first embodiment will be described with reference to FIGS. FIG. 1 is a block diagram of a dynamic circuit according to the present invention, and FIG. 2 is an example of a schematic circuit diagram of a main part.

1 and 2, a dynamic circuit 11 according to the present invention includes a clocked inverter section 12 which is a main circuit section which operates dynamically, and a storage connected to an output node 13 of the clocked inverter section 12. It is composed of a circuit section 14 and a control circuit section 15 that controls the memory circuit section 14. The output node 13 of the clocked inverter unit 12 is connected to the clocked inverter unit 12 of the next-stage dynamic circuit. Note that the clocked inverter unit 12 includes the p-channel and n-channel transistors 1 connected in series.
6, 62, 17, and 63 are formed, and 18 is an input node. The transistors 62 and 63 have a control signal CL
It is turned on or off by K and bar CLK.

The memory circuit section 14 includes two pairs of p-channel and n-channel transistors 19 and 20 connected in series.
And a p-channel and n-channel transistors 22 and 2 inserted in the power supply side and the ground side of the transistors 19 and 20 of the storage unit 21, respectively.
3 and a switch unit 24. Therefore, the power supply voltage V _DD and the ground potential are applied to the storage unit 21 connected in series via the switch unit 24.

Further, 25 is an input node of the memory circuit unit 14, 26 is an output node of the memory circuit unit 14, and the output node 13 of the clocked inverter unit 12 is respectively provided.
It is connected to the. The outputs of one pair of transistors 19 and 20 provided on the input node 25 side are output from the other pair of transistors 1 and 20 provided on the output node 26 side.
The inputs of 9 and 20 and the outputs of the other pair of transistors 19 and 20 are output to the output node 13 of the clocked inverter unit 12. Further, the switch unit 24 of the memory circuit unit 14 is connected to the control circuit unit 15
It is designed to be opened / closed by a switching signal (CTRL, bar CTRL) from, and the memory circuit unit 14 may or may not be added to the output node 13 of the clocked inverter unit 12 with this opening / closing. It has become. That is, the power supply voltage V _DD and the ground potential are applied to the storage unit 21 by opening and closing the switch unit 24,
It may not be applied.

When the power supply voltage V _DD and the ground potential are controlled to be applied to the storage unit 21, the switch unit 24 is closed, and the storage circuit unit 14 operates to operate the storage unit 21 and add it to the output node 13. Then, a signal is exchanged with the output node 13 via the input node 25 and the output node 26. When the storage unit 21 is controlled so that the power supply voltage V _DD and the ground potential are not applied, the switch unit 24 opens and the storage circuit unit 14 stops the operation of the storage unit 21 and the input node 25 and the output node. 26 remains connected and is disconnected from the output node 13, and signals are not exchanged.

Further, the control circuit section 15 outputs a switching signal to open the switch section 24 when the clocked inverter section 12 operates with a high speed clock, and switches the switch section 24 to close when operating with a low speed clock. It is designed to output a signal.

Since the dynamic circuit 11 is constructed as described above, when the clocked inverter unit 12 operates at a high speed clock, the switch unit 24 of the memory circuit unit 14 is operated by the switching signal from the control circuit unit 15. OF
The F state is maintained, and in this state, the power supply voltage V _DD and the ground potential are not applied, so that the storage unit 21 does not operate. Therefore,
The memory circuit section 14 is in a disconnected state in which the input node 25 and the output node 26 are still connected and are not added to the output node 13.

The dynamic circuit 11 includes the clocked inverter unit 1 to which the memory circuit unit 14 is not added.
The circuit becomes an original dynamic circuit of only 2 and the output node 13 is in a dynamic node state. As a result, the storage circuit unit 14 stops operating during operation of the high-speed clock, and the dynamic circuit 11 mainly consumes power in the clocked inverter unit 12, but does not consume extra power. On the other hand, when the clocked inverter unit 12 operates at a low speed clock, the control circuit unit 1
The switch section 24 of the storage circuit section 14 is turned on by the switching signal from the storage circuit section 5, the storage section 21 is operated by applying the power supply voltage V _DD and the ground potential, and the storage circuit section 14 is added to the output node 13. Becomes The signal from the input node 25 connected to the output node 13 is stored in the storage unit 2
1 and is output to the output node 13 via the output node 26.
Will be fed back to.

In this way, in the dynamic circuit 11, the memory circuit section 14 forming the feedback circuit section at the time of operation of the low speed clock is added to the output node 13 of the clocked inverter section 12 to make it a static circuit, and the output node 13 becomes a static node. Become. As a result, even when the clocked inverter unit 12 is operated at a low frequency equal to or lower than the lower limit operating frequency, the potential of the output node 13 can be maintained at an appropriate level, and malfunction due to insufficient potential can be prevented. it can. In particular, there is no fear of malfunction even if the frequency is 0 Hz, that is, the operation is stopped.

As described above, according to the present embodiment, it is possible to reduce power consumption according to the operating state and to realize better power management without fear of malfunction.

Next, a second embodiment will be described with reference to FIG. FIG. 3 is a circuit diagram of a main part of the dynamic circuit according to the present invention.

In FIG. 3, a dynamic circuit 31 according to the present invention controls a storage circuit section 32 connected to an output node 13 of a clocked inverter section 12 which is a main circuit section that operates dynamically, and the storage circuit section 32. The control circuit unit 15 is provided. The memory circuit section 32 includes a switch section 35 formed by including two pairs of p-channel and n-channel transistors 33 and 34 connected in series,
Two pairs of p-channel and n-channel transistors 3 connected in series with each switch portion 35 provided therebetween
6, 37, and a storage unit 38 formed.

Further, 39 is an input node of the memory circuit section 32, 40 is an output node of the memory circuit section 32, and each is an output node 13 of the clocked inverter section 12.
It is connected to the. The outputs of the pair of transistors 36 and 37 on the input node 39 side are input to the other pair of transistors 36 and 37 on the output node 40 side via the switch section 35 provided therebetween. The outputs of the other pair of transistors 36 and 37 are output to the output node 40 via the switch section 35 provided therebetween.

Further, the switch section 35 of the memory circuit section 32.
Is a switching signal (CTRL, bar C from the control circuit unit 15).
The memory circuit section 32 may or may not be added to the output node 13 of the clocked inverter section 12 according to the opening / closing of the memory circuit section 32. That is, the switch unit 3
Depending on whether the power supply voltage V _DD and the ground potential are applied or not by opening / closing 5, the storage unit 38 may or may not operate.

When the power supply voltage V _DD and the ground potential are controlled to be applied to the storage unit 38, the switch unit 35 is closed, and the storage circuit unit 32 operates to operate the storage unit 38 and add it to the output node 13. Then, signals are exchanged with the output node 13 via the input node 39 and the output node 40. When the storage unit 38 is controlled so that the power supply voltage V _DD and the ground potential are not applied, the switch unit 35 opens, and the storage circuit unit 32 stops the operation of the storage unit 38 and the input node 39 and the output node. 40 remains connected and is disconnected from the output node 13, and signals are not exchanged.

The control circuit section 15 outputs a switching signal to open the switch section 35 when the clocked inverter section 12 operates at a high speed clock, and closes the switch section 35 when operating at a low speed clock. It is designed to output a switching signal.

Since the dynamic circuit 31 is constructed as described above, when the clocked inverter unit 12 operates at a high speed clock, as in the first embodiment, the switching signal from the control circuit unit 15 is used. Storage circuit unit 32
The switch section 35 of the above is kept in the OFF state, and in this state, the power supply voltage V _DD and the ground potential are not applied, so the storage section 38
Does not work. Therefore, the memory circuit unit 32 is connected to the input node 3
9 and the output node 40 are still connected to the output node 13
It is in the separated state, which is not added to.

The dynamic circuit 31 includes the clocked inverter unit 1 to which the memory circuit unit 32 is not added.
The circuit becomes an original dynamic circuit of only 2 and the output node 13 is in a dynamic node state. As a result, the storage circuit section 32 stops operating during the operation of the high-speed clock, and the dynamic circuit 31 mainly consumes power in the clocked inverter section 12, but does not consume extra power. On the other hand, when the clocked inverter unit 12 operates at a low speed clock, the control circuit unit 1
In response to the switching signal from the switch 5, the switch unit 35 of the memory circuit unit 32 is turned on, the memory unit 38 operates by applying the power supply voltage V _DD and the ground potential, and the memory circuit unit 32 is added to the output node 13. Becomes Then, the signal from the input node 39 connected to the output node 13 is stored in the storage unit 3
8 and is output to the output node 13 via the output node 40.
Will be fed back to.

In this way, in the dynamic circuit 31, the memory circuit section 32 forming the feedback circuit section at the time of operation of the low speed clock is added to the output node 13 of the clocked inverter section 12 to make it a static circuit, and the output node 13 becomes a static node. Become. As a result, even when the clocked inverter unit 12 is operated at a low frequency equal to or lower than the lower limit operating frequency, the potential of the output node 13 can be maintained at an appropriate level, and malfunction due to insufficient potential can be prevented. it can.

As described above, according to the present embodiment, it is possible to reduce power consumption according to the operating state and to realize better power management without fear of malfunction.

Next, a third embodiment will be described with reference to FIG. FIG. 4 is a circuit diagram of a main part of the dynamic circuit according to the present invention.

In FIG. 4, a dynamic circuit 41 according to the present invention controls a memory circuit section 42 connected to an output node 13 of a clocked inverter section 12 which is a main circuit section that dynamically operates, and the memory circuit section 42. The control circuit unit 15 is provided. The storage circuit unit 42 includes a storage unit 43 formed by a flip-flop circuit, an output node 1 of the storage unit 43 and the clocked inverter unit 12.
And a transmission gate 44 which is a switch unit inserted between
It consists of and. The transmission gate 44 is formed by p-channel and n-channel transistors 45 and 46, and is inserted between one output end of the storage section 43 and the output node 13.

Then, the transmission gate 44 of the memory circuit section 42.
Is a switching signal (CTRL, bar C from the control circuit unit 15).
TRL) opens and closes the gate,
With this opening / closing, the memory circuit section 42 is added or not added to the output node 13 of the clocked inverter section 12. That is, by opening / closing the transmission gate 44, the storage unit 43 and the output node 13 are opened.
Signals may or may not be sent to and from.

Then, the storage circuit section 42 connected to the output node 13 of the clocked inverter section 12 becomes a state in which the storage section 43 is added to the output node 13 via the transmission gate 44, and the transmission / reception of signals is performed. It is supposed to be done. Further, the memory circuit section 42 is kept connected to the output node 13 via the transmission gate 44, and the memory section 43 is disconnected from the output node 13 so that signals are not exchanged.

Since the dynamic circuit 41 is configured as described above, when the clocked inverter unit 12 operates with a high speed clock, the transmission gate 44 of the memory circuit unit 42 is changed by the switching signal from the control circuit unit 15. OF
It keeps F state and does not work. Therefore, the memory circuit section 42 is in a separated state where it is not added to the output node 13.

The dynamic circuit 41 includes the clocked inverter unit 1 to which the memory circuit unit 42 is not added.
The circuit becomes an original dynamic circuit of only 2 and the output node 13 is in a dynamic node state. As a result, the storage circuit section 42 stops operating during operation of the high-speed clock, and the dynamic circuit 41 consumes only power mainly in the clocked inverter section 12, but does not consume extra power. On the other hand, when the clocked inverter unit 12 operates at a low speed clock, the transmission gate 4 of the memory circuit unit 42 is generated by the switching signal from the control circuit unit.
4 is turned on, and the memory circuit unit 42 outputs the output node 13
Is added to. Then, signals are exchanged between the output node 13 and the storage section 43 formed by the flip-flop circuit via the transmission gate 44.

In this way, in the dynamic circuit 41, the memory circuit section 42 forming the feedback circuit section at the time of operation of the low speed clock is added to the output node 13 of the clocked inverter section 12 to make it a static circuit, and the output node 13 becomes a static node. Become. As a result, even when the clocked inverter unit 12 is operated at a low frequency equal to or lower than the lower limit operating frequency, the potential of the output node 13 can be maintained at an appropriate level, and malfunction due to insufficient potential can be prevented. it can.

As described above, according to the present embodiment, it is possible to reduce power consumption according to the operating state and to realize better power management without fear of malfunction.

Next, a fourth embodiment will be described with reference to FIG. FIG. 5 is a circuit diagram of a main part of the dynamic circuit according to the present invention.

In FIG. 5, a dynamic circuit 51 according to the present invention controls a memory circuit section 52 connected to an output node 13 of a clocked inverter section 12 which is a main circuit section that dynamically operates, and the memory circuit section 52. The control circuit unit 15 is provided. The storage circuit unit 52 includes a capacitance 53, which is a storage unit, and the capacitance 53.
Of the transmission gate 5 which is a switch section inserted between one terminal of the output terminal 13 and the output node 13 of the clocked inverter section 12.
It is composed of 4 and. The transmission gate 54 is a p-channel transistor and an n-channel transistor 5 connected in parallel.
5, 56.

Then, the transmission gate 54 of the memory circuit section 52.
Is a switching signal (CTRL, bar C from the control circuit unit 15).
TRL) opens and closes the gate,
With this opening / closing, the memory circuit section 52 is added or not added to the output node 13 of the clocked inverter section 12. That is, by opening / closing the transmission gate 54, the charge signal may or may not be transferred between the capacitance 53 and the output node 13.

When the capacitance 53 is controlled to transfer the charge signal, the storage circuit section 52 connected to the output node 13 of the clocked inverter section 12 is connected via the transmission gate 54. The capacitance 53 is added to the output node 13, and the charge signal is exchanged. Further, when the capacitance 53 is controlled so as not to transfer the charge signal, the storage circuit unit 52 remains connected to the output node 13 via the transmission gate 54, and the capacitance 53.
Are separated from the output node 13, and charge signals are not exchanged.

Since the dynamic circuit 51 is constructed as described above, when the clocked inverter unit 12 operates at a high speed clock, the transmission gate 54 of the memory circuit unit 52 is changed by the switching signal from the control circuit unit 15. OF
The F state is maintained, and the storage circuit unit 52 is in a separated state where it is not added to the output node 13.

The dynamic circuit 51 includes the clocked inverter unit 12 to which the memory circuit unit 52 is not added.
Only the original dynamic circuit will be used. As a result, the dynamic circuit 51 does not consume extra power when the high-speed clock operates.

On the other hand, when the clocked inverter unit 12 operates at a low speed clock, the transmission gate 54 of the memory circuit unit 52 is turned on by the switching signal from the control circuit unit 15, and the memory circuit unit 52 outputs the output node. 13 is added. Then, the output node 13 and the capacitance 5
The transfer of electric charge between the electric field and the electric field 3 is performed via the transmission gate 54.

In this way, in the dynamic circuit 51, the memory circuit section 52 is added to the output node 13 of the clocked inverter section 12 during the operation of the low speed clock,
Even when the inverter unit 12 is operated at a low frequency equal to or lower than the lower limit operating frequency, the capacitance 53 maintains the potential of the output node 13 at an appropriate value, and it is possible to prevent malfunction due to insufficient potential. That is, due to the capacitance 53,
The lower limit operating frequency of the inverter unit 12 can be extended to a lower frequency.

The dynamic circuit 51 at this time is
Capacitance 53 is added to maintain the electric potential, thus forming a low power consumption circuit. That is, although power is increased by adding a capacity and charging / discharging the capacity, the switching frequency can be sufficiently lowered, so that the power consumption of the entire dynamic circuit 51 can be reduced.

As described above, according to the present embodiment, it is possible to reduce power consumption in accordance with the operating state and to realize better power management without the risk of malfunction.

In the above example, the clocked inverter unit 12 is used as an example of a circuit which becomes a dynamic circuit in a high speed clock, but the present invention is not limited to this. That is, if the output node is in a high impedance state by the control signals CLK and CLK and the output signal is dynamically held, the output circuit has a memory circuit section (memory circuit) having the function of the present invention. Signals that are generated in the active power management operation described above, that is, a signal that controls the presence or absence of the addition of the memory circuit unit according to the power consumption suppression mode signal. The presence / absence of the addition of the memory circuit unit may be controlled by a control signal from the dynamic operation control circuit (control circuit unit 15) that is output. For example, it may be a dynamic circuit in which an analog transmission gate is added to the output of the logic circuit shown in FIG. 7B as a conventional example. Further, a tri-state circuit as shown in FIG. 6 may be used. Furthermore, its output is high
It may be a memory circuit or a PLA which is in an impedance state and in which an output signal is dynamically held.

[0058]

As is apparent from the above description, the present invention has effects such as reduction in power consumption, possibility of malfunction, and realization of better power management.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a schematic circuit diagram showing a main part of the first embodiment of the present invention.

FIG. 3 is a schematic circuit diagram showing a main part of a second embodiment of the present invention.

FIG. 4 is a schematic circuit diagram showing a main part of a third embodiment of the present invention.

FIG. 5 is a schematic circuit diagram showing a main part of a fourth embodiment of the present invention.

FIG. 6 is a circuit diagram showing a specific example of a circuit forming a dynamic circuit according to the present invention.

FIG. 7 is a circuit diagram shown for explaining a conventional technique.

FIG. 8 is a schematic circuit diagram showing a conventional dynamic circuit.

[Explanation of symbols]

 12 ... Clocked inverter section 13 ... Output node 14 ... Storage circuit section 15 ... Control circuit section

Claims (5)

[Claims] 1. An output node of a main circuit section that operates dynamically, a storage circuit section that is provided so as to be added to this output node, and a control circuit that controls whether or not this storage circuit section is added to the output node. A state in which the storage circuit unit is not added to the output node when a high-speed clock is operated by a switching signal from the control circuit unit, and the storage circuit unit is added to the output node when a low-speed clock is operated. A dynamic circuit characterized in that 2. The memory circuit unit is configured to include a switch unit that opens and closes in response to a switching signal from the memory unit and the control circuit unit, and an addition state of the memory unit to the output node is controlled by opening and closing the switch unit. The dynamic circuit according to claim 1, which is a circuit. 3. The dynamic circuit according to claim 1, wherein the storage circuit unit changes the output node from the dynamic node state to the static node state by adding it to the output node. 4. The dynamic circuit according to claim 1, wherein the storage circuit section includes a capacitance as the storage section. 5. The dynamic circuit according to claim 1, wherein the control circuit section outputs a signal for controlling the presence or absence of the addition of the storage circuit section in accordance with the power consumption suppression mode signal.