JPH0729393A - Memory device and method for restoration of defective memory - Google Patents

Abstract

PURPOSE: To more effectively use an available redundant memory cell. CONSTITUTION: A redundant row decoder is programmable so as to hold the address of a defective row, and moreover a two-stage decoder provided with a first redundant decoder generating a redundant row decode signal and redundant row factor enable signal by receiving a row address. A second redundant decoder is programmable so as to hold the position of an array including a defective row. The redundant row decode signal is received with it to generate an array selecting signal. A third enabler stage, connected to the redundant row of the memory cell and responding to the redundant row factor enable signal and array selecting signal, is added, whereby the selected redundant row of the memory cell in the memory array including the defective row of the memory cell is allowed to enable. A redundant column decoder is programmable so as to hold the address of a defective column.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to integrated circuits, and more particularly to integrated circuit devices formed in semiconductor substrates, such as memory devices such as dynamic random access memories.

[0002]

The development of dynamic random access memory (DRAM) type large scale integrated circuit (VLSI) semiconductor devices is well known. Over the years (as shown in Lao US Pat. No. 4,055,444)
From 16K DRAM (Makkelroy US Pat.
No. 58,377) to 1MB DRAM,
Furthermore, the industry is developing into a 4MB DRAM.
This is a next-generation DRAM in which a 16 MB DRAM in which 16 million or more memory cells and related circuits are integrated on one memory chip is planned to be manufactured.

At present, designers are facing various problems in designing a 16 MB DRAM type VLSI semiconductor memory device. For example, one concern is eliminating defects. Kuo's U.S. Pat. No. 4,240,092
No. 4 (planar capacitor cell) and US Pat. No. 4,721,987 to Bagley (trench capacitor cell)
As shown in, the development of large scale DRAM has been accelerated by the reduction of memory cell geometry. 16M
The extremely small geometry of BDRAM is manufactured using submicron technology. The feature size reduction means that particles, which have not been a problem in the conventional manufacturing process, cause circuit defects or defective devices.

Redundant circuits have been introduced to improve the defects. The redundancy circuit consists of some extra rows and columns of memory cells arranged in the memory array and replaced by defective rows and columns of memory cells. In order to effectively and efficiently repair defects and improve the yield of 16MB DRAM chips, designers need new and improved redundancy circuits.

In one aspect thereof in accordance with the present invention, a memory device includes a plurality of memory arrays having memory cells arranged in rows and columns and having redundant rows of memory cells to replace defective rows and to read information from the memory cells. Row redundancy circuit for selecting the redundant row of the memory cell only in the memory array having the defective row of the memory cell in response to the address of the defective row of the memory cell. Is included.

Preferably, the row redundancy circuit includes a two-stage programmable row redundancy decoder programmable to hold a defective row address and programmable to hold information identifying a memory array containing a defective row of memory cells. There is. According to another aspect thereof in accordance with the present invention, a memory device integrated on a semiconductor substrate comprises a plurality of memory arrays having memory cells arranged in rows and columns and redundant columns of memory cells replacing defective columns. A column redundancy circuit is provided for selecting a redundant column of memory cells only in a memory array having a defective column of memory cells in response to an address of a defective column of memory cells.

Preferably, the column redundancy circuit includes a two-stage programmable column redundancy decoder programmable to hold a defective address and programmable to hold information identifying a memory array containing a defective column of memory cells. . A memory device holds a defective row address, a first redundant decoder programmable to receive the row address and generate a redundant row decode signal and a redundant row factor signal, and a position of the array containing the defective row. And a second redundant decoder programmable to receive the redundant row decode signal and generate an array select signal, a redundant low factor enable signal for the second redundant decoder, an array select signal for the second redundant decoder, and a memory. It is advantageous to include a redundant enabler circuit that is connected to a redundant row of cells and enables selected redundant rows of memory cells in a memory array having defective rows of memory cells.

A memory device according to the present invention includes a row redundancy circuit and a column redundancy circuit, and may include the memory device described in any of the claims. The memory device can be, for example, a dynamic random access memory.

In yet another aspect in accordance with the present invention, a method of repairing a defective memory cell in a semiconductor memory device having more than one memory array programs a first circuit with an address of the defective memory cell. Programming the second circuit with the location of the memory array having the defective memory cell and selecting the redundant memory cell in the memory array having the defective memory cell upon receiving the address of the defective memory cell. Preferably, the defective memory cell is a defective row memory cell and the redundant memory cell is a redundant row memory cell. Alternatively, the defective memory cell is a defective column cell and the redundant memory cell is a redundant column memory cell.

As part of this application, a representative two-stage redundant decoding circuit for a semiconductor memory device is disclosed.
The redundant row decoder is a two-stage decoder that is programmable to hold the address of the defective row and has a first redundant decoder that receives the row address and generates a redundant row decode signal and a redundant row factor enable signal. The second redundant decoder is programmable to hold the position of the array containing the defective row. It receives the redundant row decode signal and outputs the array select signal. Enabling a selected redundant row of memory cells of a memory array including a defective row of memory cells by adding a third enabler stage connected to the redundant rows of memory cells and responsive to a redundant row factor enable signal and an array select signal. can do. The redundant column decoder can be programmed to hold the address of the defective column. It receives the column address and generates a redundant column decode signal and a redundant column factor enable signal. The second redundant decoder can be programmed to retain the position of the array containing the defective column. It receives the redundant column decode signal and generates an array select signal. Enabling a selected redundant column of memory cells of a memory array including a defective column of memory cells by adding a third enabler stage connected to the redundant column of memory cells and responsive to a redundant column factor enable signal and an array select signal. can do. The decoding circuit uniquely identifies the memory part that needs repair,
Use the available redundant memory cells more efficiently. Other objects, advantages and features of the invention will be apparent to those skilled in the art from the following detailed description of the embodiments of the invention taken by way of example with reference to the drawings.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An example of an embodiment of the present invention and a memory chip including the present invention will be described here.

FIG. 1 shows a 16 megabit dynamic random access memory chip called a 16 MB DRAM. The chip size is about 325 x 660 mm. The chip is divided into four memory array quadrants. Each memory array quadrant contains 4 megabits. A 4 MB memory array quadrant contains 16 memory blocks. Each memory block contains 256 kilobits. Column decoders are arranged along the vertical axis of the chips adjacent to their corresponding memory array quadrants. Row decoders are arranged along the horizontal axis of the chips adjacent to their corresponding memory array quadrants. Peripheral circuits, including devices such as I / O buffers and timing and control circuits, are centrally located along both the horizontal and vertical axes of the chip.
The bonding pad is centrally located along the horizontal axis of the chip.

FIG. 2 is a plan view showing the mounting / pin output of this device. The chip is bonded in the center,
Encapsulated in a thin resin J-shaped package with a small outline. Among other features, this DRAM
Has the feature of being programmable by bonding to either an X1 or X4 device. Pin configurations for both X1 and X4 operating modes are shown.

FIG. 3 is a diagram showing a three-dimensional appearance of a chip in which a sealing resin is transparent and encapsulated. The pin configuration shown corresponds to the X4 option. This TSOJ package is a central bonding (LO
CCB type lead over chip
tip). Basically, the chip is located under the lead finger. A polyimide tape connects the chip to the lead finger. Gold wire is wire bonded from the lead fingers to the central bond pad of the chip.

FIG. 4 is a packaged external view of the assembly, and FIG. 5 is a sectional view of the mounted device. FIG. 6 is a diagram showing the names and sequences of bonding pads.
Both sequences are shown for the X1 and X4 options. EXT BLR is an in-house (in-ho
It is a pad only for use). Brackets such as those shown for bond pads 4 and 25 indicate that this is a bond pad option.

The general characteristics of the 16 MB DRAM of FIG. 1 are as follows. The device typically receives an external VDD of 5 volts. An internal voltage regulator on the same chip powers the memory array at 3.3 volts and the peripheral circuits at 4.0 volts to reduce power consumption and channel hot carrier effects. The substrate is biased at -2 volts. This configuration is X1 / X4 programmable by bonding. X1 or X4 option is X1 at manufacturing stage
Bonding pad 25 (Fig. 6) and VS for the device
It can be chosen by placing a bonding wire with S and by omitting this bonding wire for the X4 device. The resulting pinouts for the 10 options are shown in FIG. Bonding wires can be provided between the bonding pads 25 and the leadframe VSS bus 3 (FIG. 3).

Enhancing page mode (enh
The anced page mode is the preferred option, along with the programmable option with a metal mask for bit-wise write (data mask) operations.

The preferred option for the refresh scheme is 4096 cycles at 64 ms. But this D
The RAM can be programmed with a 2048 cycle refresh by bonding. Option selection can be accomplished in a manner similar to that used for X1 or X4 option selection. The associated bond pad is 4 and is bonded to VSS for 2K refresh, otherwise the 4K refresh option is implemented.

DRAM has many test design features. Test mode entry 1 is done through the address-keyless WCBR for 16X internal parallel testing with mode data comparison. Test mode entry 2 is a WCBR with an address key and overvoltage only after that (8 volts on A11). Exiting the test mode occurs by any refresh cycle (CBR or RAS only). Test mode entry 1 is an industry standard 16X parallel test. This test is similar to that used in 1 MB and 4 MB DRAMs, but 16 bits are compared simultaneously instead of 8 bits. Valid address keys are A0, A1, A2, A6. Test mode entry 2 contains a number of tests. 32X parallel test with data comparison and 1 with data comparison
6X parallel test included. Different hexadecimal addresses are keyed for different parallel tests. Storage cell stress test and VDD margin test
Allow connection from external VDD to internal VARY and VPERI device power lines via P-channel device. Other tests include redundant signatures
It includes a test, a row redundant roll call test, a column redundant roll call test, a word line leak detection test, a clear concurrency test, and a reset to normal mode. The DRAM also includes a test validation method that indicates whether it remains in test mode.

Although not shown in FIG. 1 for clarity, DRAM has redundancy features for defect erasure. It has 4 redundant rows per 256K memory block. These four rows can be used simultaneously. There are 3 decoders per redundant row and 11 row addresses per redundant row decoder. Fuses are used for row redundancy, averaging 10 for a single repair.
One fuse blows. Row redundancy uses a two-step programmable scheme to allow for efficient correction. There are 12 redundant columns per quadrant and 4 decoders per redundant column. There are 8 column addresses and 3 row addresses per decoder. The total number of fuses for a column repair is approximately 10 blown fuses per single repair. Column redundancy also allows more efficient modifications,
It uses a two-step programmable scheme.

FIG. 7 is a plan view of the arrangement of the capacitor cells. The bit line is poly 3 (TiSi 2) polycide. The bit line reference is not used. Three bit lines are twisted together to suppress noise. The power line voltage is about 3.3 volts. The word lines are poly 2 segmented. They are bound by metal 2 every 64 bits. The memory cell is of the modified trench capacitor type and is disclosed in US Pat. No. 5,017,5
06 and European Patent Application No. 0410288.

Another suitable memory cell is of the stacked trench type disclosed in US Pat. No. 4,978,634.

In FIG. 7, the size of each part is such that the bit line pitch is 1.6 μm, the double word line pitch is 3.0 μm, and the cell size is about 4.8 μm.
It has been obtained using μm technology. The trench opening is about 1.1 μm and the trench depth is about 6.0 μm. The derivative is a nitride / oxide with a thickness of about 65Å. Field plate separation is used. The transistor has a thin gate. FIG. 8 is a cross-sectional view of the modified trench capacitor cell, and FIG. 9 is a side view of the trench capacitor cell. The operation of this embodiment will be described in detail below.

CL1-COLUMN LOGIC-Circuit Diagram FIG. 10 This is a CBR detector which, in addition to checking the CBR state, converts the external TTL_CAS signal logic level to a CMOS logic level to generate an internal CAS clock CL1_.

The first part of the circuit is the TTL to CMOS converter, XTTLCLK. It is an internal RA
Controlled by S clock, RL1, signal conversion is RL1
Start only if _ is taken high. The feedback of the internal CAS clock CL1_ allows XTTLCLK to remain active even when RL1 changes state from active high to low. This configuration allows the device to operate in EXTENDED CAS 'mode, ie CAS_ remains active low after RAS_ goes high. However, the feedback loop of CL1_ is gated by the power-up signal RID before entering the converter. This avoids unnecessary switching of the converter during power-up. The second part of the circuit samples the CAS_ signal when RL1 goes high. If CAS_ is low at this time, that is, if CAS_ falls before RAS_, CBR_EN_ becomes active low and C
The BR cycle is shown. RBC_EN remains high, but if CAS_ is high, the output has an inverse logic level indicating a normal RBC cycle. Here, latching is not performed and sampling continues as long as RL1 is high. When the CAS_ signal changes state during this cycle, the outputs CBR_EN_ and RBC_EN_ change together. However, these subsequent outputs are
N'T CARES 'and the initial output latch is RB
A programmable delay is used in the C circuit to control the start of this sampling.

RBC-RAS BEFORE CAS RBC_RESET-RAS BEFORE CAS
RESET Circuit Diagram FIGS. 11 and 12 As discussed in the CL1 circuit, CBR_EN_ and RB
Only the initial output of C_EN_ is the type of device operating cycle, RAS BEFORE CAS or CAS.
Reflects BEFORE RAS. Therefore, it is necessary to latch the initial output for the entire operating cycle. This latching is done in the RBC circuit. RBC_RE
The SET circuit resets the latch at the end of the cycle to make the device ready for the next cycle. CBR
In addition to latching _EN_ and RBC_EN_, RBC
Generates a RAN signal to gate the row address.

LBC_EN_ and CBR_EN_ signals are latched by two interlocking latches, XRS
1 and XRS_3. One of the two latches is RBC_EN_ or CB during the precharge state.
Excited by an active low signal from R_EN_. The excited latch then locks the excitation of the second latch. Lock is deasserted at the end of the RAS_active cycle going low, generating an RBC_RESET pulse that resets and locks the latch. RL
RST_ is a precharge signal that occurs on the rising edge of RL1_ after a delay.

In normal operation, RAS BEFORE C
AS cycle RBC or CAS BEFORE
The RAS cycle CBR is brought high. CBR_DF
The T signal follows CBR logic but is not used in normal operation. A similar signal is generated from CBR with a delayed falling edge. This is the CBRD signal, CAS BEF
Used as an incremental clock signal for the ORE RAS internal counter. The falling edge of this signal causes the increment.
Therefore, by delaying the internal counter, the device is allowed to change its ROW before changing the internal counter address.
Sufficient time is provided to turn off ADDRESSBUFFER.

When the device is in DFT ROW COPY mode, the XRS_3 latch acts as an inverter at node N2 to output CBR_ and CBR is disabled to a low logic level. This is node N2 and R
Correct unless BC_RESET is both logic high at the same time. Please note that this situation does not occur in the activity sequence. With this setting the RBC is still latched and locks off the CBR_EN_ signal, but in CAS BEFORE RAS operation CBR_
EN_ is activated during all cycles and output CBR_
Must have a DFT. Therefore, CAS_ is R
It will be low as long as AS_ is low. CBR and CB
Both RD are disabled from going high in this test mode. CAS BEFOR in this test mode
When E RAS cycles are performed, they are disabled to avoid using the internal CBR counter as a row address.

In this test mode, resetting is performed at the end of the active cycle by normal RASBEFORE CAE.
Performed by RBC_RESET in S cycle. C
During the AS BEFORE RAS cycle, a logic high on CBR_EN_ resets at the end of the active cycle. The other part of the circuit is ROW ADDRESS E
The NABLE signal and RAN & RAN are generated. These signals are generated during any active cycle. For a typical RBC type cycle, these signals need to occur as soon as possible. Therefore, RBC_E
The falling edge of N is used to trigger the transition of the RAN signal. In order to keep the RAN signal active during the RAS_precharge period, the RBC_ signal is used to keep the RAN signal active. CAS-BEFORE-R
For AS operation, it is necessary to delay the execution of the RAN signal to ensure that the address buffer functions properly.

In these two circuits, the power-up signal RID is used to preset the initial state of the latch. Before the delay stage, XSDEL1, delays the assertion of RAN from CBR_ and enables the buffer with RAN, the CBR internal address is ROW ADDRESSBU.
Allow sufficient time to reach FFER. Therefore,
No false data is pulled from ROW ADDRESSEE BUFFER. RAN_ is RBC_RE
Also used to reset SET.

PADABUF-PAD ADDRESS
BUFFER-Circuit Diagram Figure 13 PADABUF multiplexes data from address pins, row address RAP_X and column address CAP.
Latch as _X. In the first stage of the circuit, internal R
Address TTL when AS signal, RL1_ goes low
The signal is converted to CMOS level. Delayed RAS
The signal, RL2, is then latched at the row address. RL
There is also an address delatch delay by 2. This gives the device time to disable precharge before address disable. When disabled, the address RAP_X is always ‘1’ and RL1.
_ Is inactive high. On the other hand, CLNA_ is set low and the address is propagated as CAP_X.
The column address is available before _ goes low. As a result, the device is "ENHANCE P
Can work with AGE MODE ', AS CL
1_ becomes low and the column address is latched in CAP_X. Finally, during the precharge cycle when RL1_ goes high, the XTTL ADD converter is inhibited and unaffected by the external change address. However, CAP_
X is maintained.

RADR-ROW ADDRESS DRIVER-Circuit Diagram FIG. 14 This is a row address driver. The control signal, RAN, starts driving the address signal. Not only is it a driver, but it also multiplexes the external latch row address and the CBR internal counter address before driving.

BITCOUNT-CBR INTERN
AL, BITCOUNT-Circuit Diagram FIG. 15 12 sets of this circuit are connected in series in the device.
It acts as a 12-bit internal address during the CBR cycle. The circuit is a flip-flop that is excited on the falling edge of its input signal. For the lowest set, the input is the CRBD signal and the output is the LS of the CBR row address.
B, and is also the input to the next set of BITCOUNT circuits. This continues in series until the 12 CBR address lines are formed. Such a circuit provides an incremental binary count based on the pulse of CBRD.

RF & RF CODE-ROW FACTOR Schematic FIG. 16 & APPENDIX A1_ The low factor encodes the row address into the format used in later row circuits. The ROW addresses 2 to 7 and their complements are coded by the AND operation and 12
Generate a low factor of.

RLEN_-ROW LOGIC ENABLE-schematic FIG. 17 The purpose of the RLEN_ signal is RLXH, ie MASTE
Timing the rising edge of R WORDLINE DRIVER, with respect to the low factor. In addition, the RLEN circuit informs the precharge of RLRS.
Generate SEDIS to signal the T_ signal and the BL to BL_ equalization process. RLEN is often ROW
Called FACTOR DETECTOR. It uses low factors RF _{4 to} RF ₇ to detect the completion of low factor encoding. When the encoding is detected, the NAND 'gates ND1 and ND
2 to enable addresses RA11 and RA. 11 to generate RLEN_R and RLEN_L, respectively. These are MASTER WORDLINE DR
This signal excites IVERS, RLXH_R or RLXH_L. Only one of the two drivers is active in one quadrant during normal operation. However, in DFT mode, where all eight octets of the array need to be accessed simultaneously, TL8BS is active high. This causes both RLEN_R and RLEN_L to be active at the same time. Therefore, MASTER WO
RDLINE DRIVERS, RLXH_R and RL
Both XH_L become active.

Upon completion of row factor encoding, the RLRST_state resets from a logic low to a high. On the other hand, at the end of the active cycle, the rising edge of RL1_ causes the RLRST_high logic to go low after a programmable delay. This signals the start of another precharge cycle.

The last element of the circuit is the SENDING EQ
It is UALIZATION DISABLE, SEDIS. Like RLRST_, it is used to signal the stop and start of the BL to BL_ equalization process. However, only the low-factor encoding that triggers the termination of the BL and BL_equalization process is used. This process will stop for 4 nS after completing the low factor encoding. Next, when RLRST_ becomes active low to start the precharge cycle, the SEDIS signal is reset to the logic 0'with a delay of 4 nS. Thus the equalization process is started.

When the device is in the ROW COPY DFT mode, SEDIS changes from a logic low to a high on the first cycle like any normal cycle. However, once the active cycle is complete,
RLRST_ goes low, keeping SEID from going high throughout the inactive cycle and during subsequent cycles. This is due to the active TLRCOPY which disables the reset signal from RLRST_. Without the equalization process, the voltages on BL and BL_ will remain split, and during the DFT low copy operation, BL
Alternatively, the data on BL_ can be dumped to another row.

RLXH-ROW LOGIC X (wo
rd) HIGH-schematic FIG. 18 The output RLXH is a low logic boosted line that drives the word lines and redundant word lines. RLXH is MAST
Also called ER WORDLINE DRIVERS. The circuit is formed as follows. A. AT PRECHARGE −. Node N4 is idled to (Vperi-Vt) by the inactive logic of RL1_ and RLB. −. Boosting capacitor MN11 is MN7 and M
Charge to (Vperi-Vt) via N8. −. The node N3 of the capacitor MN13 is set to the ground level. −. The word line driver RLXH, which is set to low as RLEN_0 by the transistor MN5, becomes logically high. B. START OF AN ACTIVE CYC
LE and RL1_ are low. −. "NAND 'gate ND1 is RLB, ROW LO
A circuit can be prepared that responds to the GIC BOOT signal. C. COMPLETION OF FACTORS
ENCODING and RLEN_0 become active low. −. Due to the high stray capacitance of the N channel transistor MN4 from the nodes N1 to N4, the node N4 becomes (Vperi
+ Vperi-Vt) is boosted. RLE
When N_0 becomes a logic low, N1 goes from a logic low to a high. −. When N4 is boosted up, capacitor MN1
The node N5 of 1 is charged to all Vperi. −. The node N3 of the capacitor MN13 is charged to Vperi via MN9. −. The transistors MN6 and MN4 are turned on, and the word line driver becomes Vperi like the node N1. D. START OF DRIVER BOOTIN
G and RLB become active high. −. Transistor MN4 is turned off to isolate RLXH from node N1 and protect the CMOS device at node N1 when RLXH is fully boosted. MN9 is also shut off for the boost of node N3. −. When the RLB becomes active, the node N12 becomes logic 1. As a result, the node N5 becomes
eri-Vt). Node N3 is node N
Twenty becomes a logical one and is booted at the same time. −. The booted node N3 causes the capacitor MN11
The booted voltage of is completely transferred to the word line driver RLXH. Thus the word line driver is booted and drives the addressed row. E. END ACTIVE CYCLE, RL1_ and RLEN_ are inactive (logic high level). −. The booted signal is emitted via MN10 and MN5. −. Return the node to the precharged state, as at point (A.).

In addition to the normal operation of points (A.) to (E.),
The PBOSC signal from the oscillator is excited during the LONG RAS cycle. This is to compensate for the leak in the word line by always booting RLHX in the capacitor MN16. In 2DFT mode,
WORDLINE STRESS and WORDL
INE LEAKAGE, word line driver booting is disabled by NOR 'gates NR3 and NR4. Transistor MN19 is WORDL
It is turned on in the INE STRESS mode. Thus, with booting disabled, an external voltage can be applied to the driver.

For WORDLINE LEAKAGE mode, booting is disabled and the leakage test is simply a test of word line leakage rather than a booting capacitor. The only drawback is that it is not a true check of leakage, ie there is no high voltage word line. The word line is (Vperi-Vt)
On the level. The oscillation signal from the PBOSC is also disabled through the NOR 'gate NR5 during either one of these 2DFT modes. This avoids recharging the word line via another source.

RDDR-ROW DECORDER DRIVER-Circuit Diagram FIG. 19 CODE APPENDIX A2 RDDR is the row predecoder of the device. It is used for initial address decoding. Each predecoder gates the RLXH signal and outputs 2 in each quadrant.
Select one of each four rows for two 256K array blocks. The predecoder circuit has 5 inputs NOR '
It consists of a gate. The inputs used for predecoding are RA0, RA1, RA9 and RA10. The last input is RRQSQ, which is used to disable the predecoder if the row is programmed redundancy. During precharge, BNKPC_Q is used to charge node N3. Inverter I
When the V1 and the transistor MP3 are selected, the node N
Used to maintain a high level of 3, driving RLXH to the word line decoder. However, when the device is operating in the DFT WORDLINE STRESS mode, the active-low TLWLS_ signal disables address decoding based on RA0. By doing so, two adjacent rows can be selected.

BNKPC_-BANK SELECT
PRECHARGE CLOCK GENERATOR-Circuit Diagram 20 BNKPC_ is BANK SELECT PRECHA
RGE CLOCK GENERATOR CIRCUI
T. It is clocked off from the reset pulses RID and RLT2. The output signal BNKPC_Q is the row decoder driver RDDR and the bank select circuit B.
37 and 38 for exciting the precharge decoders of the NKSL, the left end bank select circuit and the right end bank select circuit.

XDECM-ROW DECODER-schematic FIG. 21 The purpose of row decoding is to do the final decoding of the address to select only the correct word line. The row decoder uses a 3-input NAND 'gate. Inputs are low factor, RF47, RF811 and RF1216. This selects one of the 64 sets of rows in each block of the 256K array. `NAND '
The source of the gate transistor is the block select signal B
Connected to SSJK_M, which is decoded from RA8-RA11. This setting selects only one of the two active 256K array blocks with a set of 4 word lines. Set of 4 word lines is XWJM
K1, XWJMK1, XWJMK2 and XWJMK3. Please note that only one of these is active because it has already been pre-decoded in the RDDR circuit.

The BSSJKM signal is used to precharge N1 to '1' and inverter IV2 and transistor MP2 are used to hold the signal during select. ROW DEDUNDANCY SCHEME OVE
The purpose of RVIEW low redundancy is to allow replacement of defective word lines to repair the die to a serable state.
There are 16 blocks of 256K arrays in a 16 meg quadrant. Each of these blocks has four physically redundant word lines. All four redundant rows are located to the right of the 256K array block, and each redundant word line can replace any defective row in the same block. Note that there are no dummy word lines that limit the types of rows that can be swapped with redundant rows, ie BL or BL_LOW.

In redundancy programming, a quadrant is divided into two octets, each of 8 blocks. For any redundant row programmed in the octospace, similar redundancy must be programmed into the image blocks in other octospaces. This circuit is adopted for the following reasons. A. Computation reduction DF with array block operating in two octant spaces
Complex decoding circuitry is required to distinguish between octant spaces with redundant rows and octant spaces without redundant rows in various special modes of operation such as TX32 parallel and ROW COPY. To avoid this, both 8
The subspaces can be programmed symmetrically, eliminating extra decoding circuitry. B. High Access Speed By not decoding the RA11 address line, redundant row access times are much faster.

Twelve redundancy decoders in the device,
There is RRDEC. This allows a total of 12 logic word lines to be exchanged within the die. Each logical redundant line consists of a pair of physical rows, one in each quadrant, one in each octant space. However, since there are only four physically redundant rows in each 256K array block, 256K
Please note that the maximum exchangeable row in the array block is only 4. Total 12 for the entire device
Please be aware that there is no restriction on the location of the repair. For example, all repairs can be done within one quadrant.

RRA-ROW REDUNDANCY
ADDRESS-Schematic Figure 22 APPENDIX A3 and A4 RRAs generate redundancy addresses for redundancy decoders.
There are 120 RRA circuits in the device, each 10 RR
It is divided into 12 groups of A circuits. Row address RA0
/ RA_0 to RA9 / RA_9 are used as inputs to each of these groups. Each group represents a logical redundant row address.
For redundancy programming, set the address line to logic 1
If it is desired to be ', the fuse F1 is blown and the redundant row is selected. Otherwise, F1 cannot be cut. By this fuse programming during the active cycle, when the input address during the active cycle matches the redundant address, the RRA output and RRUVAX are set to logic "0". If the input address does not match the redundant address, RRUVAX provides a logical 1'output. The circuit works as follows. −. Upon power-up, the RRDSPU input pulse signal goes high. −. The pulse latches in the redundant address, ie

[Table 1]

For example, the A72H row is programmed as a redundant row. Here, one set of 10 RRA circuits is provided with addresses RA0 / RA0_ to RA9 for programming.
/ RA9_ is used.

[Table 2]

Please note that addresses RA11 and RA10 are not used here. 8 in each quadrant
RA11 is ignored because no subspace selection is required.
RA10 is decoded in the RRDEC circuit. Finally, there is the node RRUVPN. This node acts as the power line for the inverter with MP2 and MN2. This prevents the voltage on N1 from dropping too low during power-up if the fuse is not blown. When this occurs, it is difficult to pull up N1 because MP1 is mainly a current limiting device. Due to layout restrictions, the two RRA circuits share a transistor MP1 of size (W / 1 = 20 / 0.8), and the size of MP1 in the circuit is (W / 1 = 10 / 0.8). Thus, R
RUVPN is only a common node between two RRA circuits.

RRDEC-ROW REDUNDANC
Y DECODER-Circuit Diagram FIG. 23 This circuit decodes the redundancy address generated by the RRA circuit. A set of 10 RRA outputs form the inputs of the NOR 'structure decoder. The ten RRA outputs are generated from row addresses RA0 / RA0_ to RA9 / RA_9. In addition to this, RA10 and RA10_ are also NOR '
It is connected as an input via two fuses. The fuse acts as a circuit enable switch. At least one of these must be turned off to excite the circuit. If the programmed redundant RA10 is a logic 1 ', the fuse connected to the input RA10 is blown. When programming to logic '0', the other fuse is blown. If neither fuse is blown, RRDEC remains inactive during any active cycle. However, if both fuses are blown, the device can ignore the address R10 / R10_ and select two rows in the octet space simultaneously.

During precharge, RRL2 switches on 'the transistor MP1 so that the output is precharged high. All inputs are inactive low logic to avoid high current. In the active cycle, if the address RA0 / RA10 matches the programmed redundancy address, the output stays high indicating that a redundant low selection has been detected. 1
Unlike typical redundancy decoding circuits that use a stage NOR 'decoder, this uses a two stage decoding system. RRA is a predecoder and RRD
EC is used for final decoding. The advantages of this circuit are as follows. −. The number of fuses required on the chip is reduced. Conventional methods have true and complementary addresses entering the decoder, each of which requires a fuse. −. The capacity of the decode node N2 is reduced and the decoding speed is improved.

RRX-ROW REDUNDANCY
X FACTOR-Circuit Diagram FIG. 24 There are four of these circuits in the DRAM. 12 of each
Gates 3 of the RRDEC outputs of the
Select one of four redundant rows in K block in parallel. Output signal is RRQS, ROW REDUNDAN
Channeld to the CY QUADRANT SELECT circuit. The RRXE signal enables the three NAND 'gates. Here, it is important that the RRXE start to be enabled only after the redundancy decoding is completed, that is, the non-selected RRUDV signal becomes low.
If the RRXE signal arrives too early, a high pulse will occur at the output PROXU, RR1XU or RR2XU due to the spacing between the rising edge of RRXE and the falling edge of the unselected RRUDV signal. RRQS due to the high pulse of these outputs
The Q signal is emitted and the determination of which quadrant is using the redundancy cannot be made accurately. Another important aspect of RRXE gate timing is the need to switch off gating as soon as possible after an active cycle. This is the NOR 'gate RRQ
This is because the S decoder is disabled to eliminate high current during precharge.

RRXE-ROW REDUNDANCY
X FACTOR EMULATOR-schematic FIG. 25 In order to achieve the correct timing as described in the RRX circuit section, the RRXE circuit is a mock ROW REDUN.
Designed as DANCE DECODER, RRDEC. This allows the RRX circuit to be gated in with the proper sequence of the RRXE signal. R
In RXE, RA0 and RA0_ are used to simulate redundancy addresses in RRDEC. The P-channel transistor MP1 used to precharge the circuit is sized much larger than that of the RRDEC circuit. It slows the switch off and RR
This is to delay the start of XE. Further delay is provided by inverter IV2. Also, a large transistor pulls up the node N2 at high speed, and RRQS '
The inputs of the NOR 'gate are disabled and high currents are avoided. Two passgates MN2 and MN3 are used to match the passgates in the RRA.

The RL1_ and RL2 signals are gated together to provide the precharge signal to the gate of MP1. This allows early switch-off of precharge due to the falling edge of RL1_ and late turn-on of precharge due to the falling edge of RL2. Gated RL1_ and R
The L2 signal is finally gated by the delayed RRXE signal to generate the precharge signal RRL2 of the row redundancy circuit. The reason for doing so is to interlock the RRXE circuit in a precharge cycle before another row redundancy circuit precharges. Therefore, in precharging the RRXE circuit, various decoder inputs are disabled before the active RRL2 begins precharging these decoders. Therefore, there is no overlap that there are decoders with active inputs and precharge cycles. When this happens,
High current is drawn in the decoder. Please note that you can disable the row redundancy circuit for the entire device by turning off the two fuses.

RRQS-ROW REDUNDANCY
QUADRANT SELECT-Circuit Diagram FIG. 26 So far, the previous circuit has decoded and identified redundantly used row addresses. RRQS, QUADRANT
SELECT further performs decoding to identify which quadrant the redundant row belongs to. The device has four RRQS circuits. Each of them selects a quadrant of the array. The RRQS circuit is designed as a 12-input NOR 'gate. In designing this circuit, if the redundant address does not belong to the repaired quadrant, the corresponding fuse in RRQS is blown. The fuse cannot be cut for the repaired row in that quadrant. This causes node N2 to go low, producing active output RRQS signals, TLRR_Q and RRQSQ, whenever a redundant row is addressed and belongs to that quadrant. Node N2 remains high if the redundant row does not belong to that quadrant or if the addressed row is not a redundant row.

The RRL2 signal is used to turn on MP1 and precharge N2 high during precharge. MP2 with an inverter is used to hold the precharge level at node N2 when it is not selected. Please note that by design, redundant addresses can select any number of active quadrants. This is done without blowing the fuse corresponding to the selected address in the RRQS circuit for the quadrant with the repaired row.

RXDEC-REDUNDANCY X
(Word) DECODER-schematic FIG. 27 RXDEC acts as the final decoding of the redundant rows. Once decoded, the booted voltage level is propagated from the word line driver to the redundant row. RXDEC
The circuit produces each physically redundant row. Redundancy decoding is performed by a 3-input NAND 'gate. With a given redundancy address, RRQSQ identifies the quadrant and RRXU decodes one of the four redundant rows in each 256K array block. Finally, when the normal row decoding is performed, the block signal BSSJK_M selects one of 16 array blocks and completes the row redundancy decoding.

RRDSP-ROW REDUNDANC
Y DECODER SET PULSE-Circuit Diagram FIG. 28 The purpose of this circuit is to pulse the RRA and CRRA circuits to generate redundant addresses during power up. This circuit is a series of connected inverters and capacitors. The input and output stages of these inverters are NA
It is gated by the ND 'gate to provide the pulse. The circuit is excited at power up using the RID as an input. Here, instead of generating one pulse for all RRA circuits, four pulses are generated for 120 RRA at different times.
Generated in the circuit. This avoids simultaneous excitation of all RRA circuits, which causes high peak currents. Besides this, S
RRDSP0 and RRD having RRDSP1 by changing the metal mask of W2A, SW2B, SW2C, and SW2D
The pulse widths of RRDSP2 with SP3 are each combined to generate two sets of pulses instead of four sets of pulses. After the pulse is generated, the output CRDST is excited. This starts the column redundancy address latching pulse in the CRDSP circuit.

RRATTST--Circuit Diagram FIG. 29 The purpose of this circuit is that the pulse generated by the RRDSP is RRA.
Check if it is enough to latch the address. It is used only for internal probing. RR
RRATTST is the same as RRA, except that the fuse used in A is replaced by capacitor MP1. Instead of using the regular input, the probe pad for external signal is R
It is placed on A_X. The RAX input is grounded. Another probe pad is connected in parallel to the RRDSPU signal. This allows the alternating signal to perform latching. Capacitor MN5 pulls node N2 low at power up. This circuit serves to check whether the RRDSPU pulse width is sufficient to discharge node N1 of capacitor MP1. The status is monitored from the probe pads at nodes N1 and N3.

SENSE CLOCKS Sense clocks are a chain of activities that sequence data sensing within the device. Completion of row address decoding within any active cycle excites these activities. This involves the generation of various clocks that turn on the selected sense amplifiers. Before entering the individual sense clock circuit, the 16 Meg sense amplifier circuit is examined (see FIGS. 68, 69 and 70). First, the quadrant is a 16 block 256K memory array, namely BLK0-B.
LK15. Seventeen banks of sense amplifiers are arranged in one quadrant. These sense amplifiers are arranged on the side of ENDO1 to ENDO2 in the quadrant. There is a sense amplifier bank that separates each 256K block from its neighbors. Banks are labeled S0-S16, S0 is B
It is on the ENDO1 side of the LK0 array and S16 is BLK15.
Located on the ENDO2 side of the array.

To minimize the area used, 16 Meg is designed with a shared sense amplifier. In the shared sense amplifier circuit, each sense amplifier bank is shared by two array blocks, that is, the blocks except the end banks S0 and S16 on the ENDO1 side and the ENDO2 side. Please note that these two banks can only have array blocks on one side. Each sense amplifier bank has 512 sense amplifiers, thus the bank supports 512 columns of the array from the block on its ENDO1 side and another 512 columns of the array from the block on its ENDO2 side. Due to array symmetry, the columns supported on the ENDO1 side of the bank are always odd address columns,
The column on the END0 side is always an even address column.
For S0, only odd columns of array BLK0 are supported, and for S15, only even columns of array BLK15 are supported. Thus, in each array block, the 512 (even address) column goes to the sense amplifier bank on the ENDO1 side, and the other 512 (odd address) column goes to the sense amplifier bank on the ENDO2 side. A point to note in this circuit is that two columns sharing the same sense amplifier do not have the same Y address, one has an odd address and the other has an even address. Another point is that access to a row in the array block excites two sense amplifier banks, one on the ENDO1 side and one on the ENDO2 side of the array block.

SDXWD-SENSE CLOCK X
-WORD DETECT-Circuit Diagram FIG. 30 This circuit times the sense clock with respect to the excitation of the word lines. In previous DRAM generations, the voltage level on the mock word line was used to trigger this circuit. However, in 16 Meg, the mock word line is omitted.

A delay of 4 nS is used instead of the mock word line. When the low factor encoding is complete, ie one of the RLEN signals goes active low, a high signal is generated at the output SDXWD after a delay. This signal is the MASTERSENSE CLOCK,
It is channeled to SDS1 to excite sensing activity. In addition, the SDXWD circuit times the word line booting and the RLB signal. In the normal cycle, the sense clock SDS4 is used to excite the word line booting. However, DFT R
In OW COPY mode, the sense clock is suppressed after the first cycle. In subsequent cycles, RLB
Are excited after a delay with RLEN.

SDS1-MASTER SENSE CLOCK-Circuit Diagram FIG. 31 SDS1 is a MASTER SENSE CLOCK. It controls and generates other sense clocks required for sensing operation. During the active cycle,
When the delayed SDXWD signal is received, the SDS1 signal is generated. However, if the device is DFT ROW
If operating in COPY mode, the circuit is inhibited during the second active cycle. Therefore, in the second cycle, when the base row is identified, row data is sensed and suppressed in BL & BL_, and MASTER SENS is detected.
E CLOCK is made active high. There are two probe pads that can control the SDS1 signal with an external injection signal. These two probe pads are always held low by the two N-channel transistors. By injecting a logic 1'voltage into the probe pad EXTS1EN, the circuit is forced to lock out the SDXWD signal and the circuit is forced to the probe pad EXTS1CTL.
To select the signal from.

SDS2-SENSE CLOCK-2 SDS3-SENSE CLOCK-3 SDS4-SENSE CLOCK-4-Circuit Diagrams FIGS. 32-34. These three signals have an SDS with programmable delay.
A clock chain generated from one signal. These three signals and SDS1 are PC (P-channel) and N
It is a clock that controls switching of the sense amplifier via a C (N channel) transistor. The structure of these three circuits is basically the same. They are SD
S1 is used as a circuit enable signal. At the same time, SDS
SDS via programmable delay stage except 4 circuits
One signal is propagated to generate each sense clock. SDS
For the four circuits, the SDS3 signal is propagated through the delay stage instead of the SDS1 signal to generate the SDS4 signal.
As a result, the SDS4 signal and the SDS3 signal are interlocked. Like the SDS1 circuit, these three circuits have two input probe pads for internal testing. An external signal can control the sense clock generation timing by these probe pads. SD
In the S2 circuit, another signal, STPL_
A signal is generated. It has the same timing as SDS2, but the polarity is different. This signal is the BL from the sense amplifier
Used to time the start of insulation on / BL_.

SENSE AMPLIFIER BANK As described above, the sense amplifier banks arranged between the two array blocks are different from those arranged on the ENDO1 side of the array BLK0 and the array BNK15 side. Therefore, the sense amplifiers arranged at the ends of the quadrants are controlled by separate select circuits, and the sense amplifier banks S1 to S15 are repeatedly controlled by the bank select circuits. −. BNKSL BANK SELECT, these are 2
Used to select the bank shared by two array blocks. −. LENDBNKSL, LEFT END BANK
SELECT is used to select the bank on the ENDO1 side of array BLK0. −. RENDBNKSL, RIGHT END BAN
K SELECT is used to select the bank on the ENDO2 side of the array BLK15.

The purpose of the BANK SELECT circuit is to decode the row address and select the sense amplifier bank for the desired array block. In addition, partial row decoding, that is, block select decoding is performed to the row decoder as BSSJK_.
An M signal is given to identify the array block. Each sense amplifier bank has its own BANK SELECT circuit. The address decoding circuit for each of these banks is shown in Appendix A9. In addition to the address, Appendix A
9 shows all corresponding clock names for all sense amplifier banks.

BNKSL-BANK SELECT-Schematic Figure 35 Code Appendix A5 Each BNKSL supports two array blocks. Therefore, it is necessary to decode two sets of addresses. The address lines used are RA8 or RA8 to RA11 or RA11_. In the first part of the circuit, the sense amplifier bank selection is decoded using a combination of two sets of similar decoding logic with different address lines. The outputs of these two decoders are combined at the NAND 'gate ND1 to generate the BNKSL signal. BNKSL by selecting either of the two decoders
The signal becomes active, indicating the bank selection. Besides the address lines, the TL8BS signal is used as an input for the decoder logic. This signal is RA11 / RA1
OR'ed with 1_. This output becomes the input of both NAND gate decoders. With this setting, the address RA11 can be ignored in the 2K refresh selection, that is, the TL8BS is connected to the logic `1`. Thus, the two sense amplifier banks are always selected in the quadrant without RA11. The second part of the circuit generates TL / STR pulses that isolate BL & BL_ from the sense amplifier to enhance sensing. It contains two interlocking logic circuits. Since this is a shared sense amplifier circuit, the sense amplifier has two BL & B pairs.
Connected to L_. However, in the active cycle only one of these sets needs to be excited. To achieve this, the logic circuit uses two decoder outputs to identify the BL / BL_set that needs to be excited.
An unselected BL / BL_set keeps its STR or STL signal low throughout the operating cycle. A high pulse is generated at the STR or STL output for the selected set. The start of the high pulse is timed by STPL_ and the stop is timed by the STPH signal. Finally, the bank's ENDO2 side (RIG
The output from the NAND decoder that decodes the array of (HT SIDE) also generates the BSSJKM signal. This is BLOCK SELECT in row decoding.
Used as a signal. Please note that other NAND decoders are not used for block select. This is 2 to select any row in the array block.
This is because one sense amplifier bank is excited. For row decoding, only the right side of the BNKSL decoding circuit is used to generate the BLOCK SELECT signal.

LENDBNKSL-LEFT END
BANK SELECT RENDBNKSL-RIGHT END BANK
SELECT-Circuit Diagram FIG. 37 and FIG. 38. The structure of these two circuits is basically the same as that of BNKSL except that it has only one set instead of two sets of decoders and BL / BL_isolation logic. . This is because the selected bank is identified by one unique address. Similar to BNKSL, address RA8 / RA8
_ ~ RA11 / RA11_ and TL8BS are used for address decoding. STPL_ and STPH are used to time BL / BL_ isolation during selection. In RENDBNKSL, the block has already been BLOCK S
Since ELECT is given, there is no BSSJKM signal output.

BSS-DR-- Circuit Diagram FIG. 36 This acts as a buffer for the BSSJKM signal. It applies the correct polarity signal to the row decoder to select one block of row decoder and precharge the circuit.
Please note that the decoder circuit is always in precharge mode when the row decoder is not selected.

S1234-SENSE CLOCK 1234-Circuit Diagram FIG. 39 The purpose of this circuit is to allow all sense clocks to propagate to the selected sense amplifier bank and to filter the clock signal when the sense amplifier bank is not selected. . SDS1 to SDS in the S1234 circuit
4 clocks and SENSE EQUALIZATION
DISABLE and SEDIS signals are BANK SEL
It is combined with the ECT signal. Therefore, only the selected bank will drive these signals high. The proper polarity of the clock is now set, active low for the PC clock and active high for the NC clock.

PCNC-P Channel and
N Channel-Circuit Diagram FIG. 40 This is a circuit that pulls up and pulls down the voltage difference in BL and BL_ pairs during sensing.
S1JKM connected to two N-channel transistors
And S2JKM pull down the low-side bit line, and S3JK_M connected to the P-channel transistor.
And S4JK_M pull up the high side bit line. The BLR signal also applies to node P during the precharge cycle.
Connected to equalize CJKM and NCJKM. This supports and speeds up the BL and BL_equalization processes.

SA-SENSE AMPLIFIER SA_END-SENSE AMPLIFIER EN
D-Circuit Diagram Fig. 41 and Fig. 42 Code Append
ix A6 These are sense amplifier circuit diagrams. SA is a shared sense amplifier and SA_END is a sense amplifier arranged in an end bank in the quadrant. BL and BL_ are connected to a sense amplifier via a pair of low Vt n channel transistors. In SA circuits, these transistors serve two purposes. The first purpose is non-selected BL
To isolate the / BL_ pair from the sense amplifier. The second purpose is to provide an isolation pulse to the selected BL / BL_ pair for sensing enhancement reasons. The SA_END circuit requires two transistors just for sensing enhancement reasons. E and BLR signals are B during precharge
Used to equalize L and BL_. In the active cycle, the E signal is inactive and when NC and PC pull down and pull up, the sense amplifier can divide the voltage level between BL and BL_. When the sensing is completed, if the YSEL signal is made high, the data from BL and BL_ will be LOCAL I /
It can be transferred to the O, LIOI and LIO_I lines.

COLUMN CLOCK The column clock is a short series of activities that selects the sense amplifier data propagated to the LOCAL I / O lines. The activity involves generating a column factor in the selection of the sense amplifier. ENHANC
When supporting E-page mode, these activities are called Column Address Select (C
AS) ROW CLOCK and SEN instead of clock
Triggered off by SECLOCK.

COLUMN CLOCK DECODI
NG SCHEME The column decoding performed here is just partial column decoding. It is CA2 / CA2_ ~ C
Use A9 / CA9_. CA0, CA1, CA10
, And the column decoding by CA11 and the address complement is performed by the I / O circuit. First, the entire memory array is examined. It is divided into four quadrants. Each quadrant is identified by addresses CA10 and CA11. Therefore, these two column address lines only select quadrants, not physical columns. For X4 devices, CA10 / CA10_ and CA11 / CA11_ remain high. In any case, this part is the I / O circuit part. Then there are 1024 columns in the quadrant.
These columns are decoded by the addresses CA0-CA9 and their complements. These are common CA2-CA
It is classified into 4 columns of 9. Each of these groups has one YS
It is identified by the EL signal. In this way, four sets of data from adjacent four columns are propagated to the LOCAL I / O lines and COLUMN CLOCKS DECODING is set.
SHEME is completed. Selection of the final address column is I
/ O circuit.

CABUF01-COLUMN ADDR
ESS BUFFER 01 CABUF29-COLUMN ADDRESS BU
FFER 29-Circuit Diagram Figure 43 and Figure 44 These two circuits act as column address buffers. These generate the true and complement addresses that will be used for decoding purposes in later circuits. CABUF29
Is for column addresses CA2 to CA9 and CABUF0
1 is for CA0, CA1, CA10 and CA11.
These circuits are currently the same, but these address lines are classified into two circuits that identify the various stages used for decoding and have different loading conditions. With two circuits, the output driver size can be easily changed in two separate blocks. CAB
The UF29 buffer is an address line used for column factor generation, and CABUF01 is an address line used for I / O decoding.

CLEN-COLUMN LOGIC ENABLE-Circuit Diagram FIG. 45 CLEN enables propagation of column factor generation and one ADDRESS TRANSITION DETEC
Excite the TOR circuit. CLNA_ is a delayed STPL_ signal that propagates an external address as a column address. By doing so, the external address is actually multiplexed using the sense amplifier sensing start (that is, the time point when BL & BL_ is isolated from the sense amplifier) to form the column address. By doing so, EN
HACED PAGE 'mode operation is supported,
That is, note that the column address is propagated to the decoder even before the CAS_ signal is excited. ST
The PL_ signal is also propagated to a series of inverters and combined with RL2 to generate CLEN and CLEN_. Each of these initiates column factor generation and Addres
s A signal that excites the Transition Detector. Probe pad EXTCLENEN and E
XTCLENCTL can be used to disable normal operation of the circuit and an external supply signal can be used to generate the output.

CF07-COLUMN FACTOR 0,7 CF07DR-COLUMN FACTOR 0,7 driver CF815-COLUMN FACTOR 8,15 CF_CODE-COLUMN FACTOR COD
E-Schematics Figures 46-48 APPENDIX A7 column factors are now encoded for better decoding circuitry. These are encoded by the NAND function. A series of inverters enhance the drive capability of these factors.

YDEC-Y DECODERS-Circuit Diagram FIG. 49 YDEC decodes an input address via a column factor, and when set high, turns on the transfer gate of the selected sense amplifier and connects the LOCAL I / O line to the bit line. . The circuit is basically a 2-NOR 'with 4 inputs each
It is a gate decoder. The four inputs come from a combination of four sets of column factors. The reason for designing as a combination of a NOR 'gate, an AND' gate and an inverter instead of a simple 4-input NOR 'gate is as follows. Layout restrictions-. High capacity loading of 4-input NOR 'gate.

COLUMN REDUNDANCY S
Similar to CHEME row redundancy, its purpose is to replace a bad column to create a fully working die. The memory array within the die is divided into four quadrants. Each quadrant has 16 array blocks of 1024 columns. 12 for each array block
There are redundant columns. These redundant columns are arranged on the side facing the center of the die. The redundant column includes a pair of bit lines (BL and BL_) and a sense amplifier. Unlike row redundancy circuits, which can replace redundant rows with arbitrary defective rows, column redundancy repair is dominated by the defective column data path. Each array block is supported by two sense amplifier banks. Each of these banks has two data paths to two different GLOBAL I / O lines. Therefore, the same GLOB for repair
Only redundant columns with AL I / O lines can be used.

The redundant column array has the same topology as the block array topology. The redundant sense amplifier bank is a continuation of the regular sense amplifier bank.
There are six redundant sense amplifiers in each of these banks.
The first three of these sense amplifiers are even globals.
The other three sense amplifiers are connected to the odd GLOVAL I / O. For redundant repair, it is first necessary to know which sense amplifier the defective column is connected to. When a bad column and a failing sense amplifier are identified, it is replaced with a redundant column whose sense amplifier has the same GLOBAL I / O.

In redundancy programming, it is necessary to replace two adjacent columns for each defective column in the array block. 2 columns have common column address CA
11 to CA1. At the same time, another column at the same address in the next octant space is replaced. The reason for performing two octet space repairs at the same time is the same as in the case of the row redundancy circuit. In addition to repairing two columns at a time, optionally a column CA11 having the same redundant decoder
It is also possible to replace the adjacent 4 columns of CA2. You also have the option of replacing several quadrants with the same redundant decoder.

There are the following restrictions on how many columns can be replaced. Only 12 redundant decoders and thus 12 logical columns can be replaced. 12 physical redundant columns per array block, but each repair uses at least 2 columns. Therefore, each array block has only six repairable positions. 6 redundant sense amplifiers per bank. Three of them are connected to the even GLOBAL I / O and the other three are odd GL
Connected to OBAL I / O. This makes the same GLO
The maximum column that can be replaced with BAL I / O is limited to 3. -Repairs for columns of the same address from different blocks should have independent redundant recorders if they do not share the same RA8-RA9 addresses.

COLUMN REDUNDANCY D
ECODE ENABLE CIRCUIT CRDECE-FIG. 50 The column redundancy decode enable circuit CRDECE is an enabler circuit of a column redundancy decoder. There are 12 CRDECE circuits on the chip. When the fuse F1 is blown, the corresponding column redundancy decoder is enabled.

CRRA-COLUMN REDUNDA
NCY ROW ADDRESS CRCA-COLUMN REDUNDACY COL
UMN ADDRESS-Circuit Diagrams 51 and 52 CODE APPEND
IX8, 9, 10. These circuits are RRA of ROW REDUNDANCY
It is the same as the circuit. CRRA and CRCA are used to program the column redundancy address, where CRC
A programs columns CA2-CA9 and CRRA is used to program RA8-RA10 for array block identification. Redundancy programming is done by blowing fuses in the circuit. See the row redundant RRA circuit for programming instructions. These redundant addresses are latched during the power-up sequence when the CRDSPI pulse is propagated to the circuit. The value of the address output signal output to the redundancy decoder is determined by the latched address.

CRDEC--COLUMN REDUN
DANCY DECODER CRDACE-COLUMN REDUNDACY D
ECODER ENABLE-Circuit Diagrams FIGS. 53 and 54 There are 12 CRDEC circuits in the device. CRD
EC_ decodes the address generated from CRC Inversion A and CRRA to determine if the input address is a redundant column address. Each of these decoders is associated with one CRDEC circuit. To enable a CRDEC, its corresponding CRDEC fuse is blown. CRDEC circuit is CRRA, CRCA and RR
It operates like the A circuit. Node N1 during power up
Is considered low. When the fuse blows, N1 stays low. Otherwise MP1 will bring it back high. Due to this, when the fuse blows, CRDECEU
V becomes logic `1 ′, otherwise it becomes logic` 0 ′. Logic `1` signals that the corresponding decoder is enabled. CRDECEUV is each CRRA and CR
Together with the output from CA, it forms the input of the redundant decoder CRDEC_. These signals are first coupled to the NAND 'gate and subsequently to the NOR' gate. Finally, they are combined with the control signal, CLEN. CLEN acts as a control signal to excite decoding upon completion of row decoding. Also, thereby, the decoder output is always inactive high during the precharge cycle.

CRY-COLUMN REDUNDAN
CY Y FACTOR-Circuit Diagram FIG. 55 The CRY circuit has two purposes. First, redundant decoders are classified and identified by the available physical redundant columns. Second, buffer the decoder outputs due to their poor driving capabilities. The four redundant decoder outputs are combined to generate the CPU signal. Output CRY as long as any one of the four decoders is active
U is high. Since there are 12 decoders, 3 CRYU signals are generated from 3 CRY circuits. Each CRYU signal identifies a pair of redundant sense amplifiers from each bank of four quadrants, one of which is an even group of sense amplifier banks.
Go to the LOCAL I / O line and go to the strange GLOBAL line. Therefore, CRY performs partial selection of physically redundant columns. The decoder output is buffered through the inverter to enhance the driving capability.

CRSS-COLUMN REDUNDA
CY SEGMENT SELECT-Schematic Figure 56 The device has two CRSS circuits. As described above, each sense amplifier bank has an even global I / O.
There are two data paths to the odd GLOBAL I / O. During the normal column addressing, the selected sense amplifier banks are even and odd GLOBAL I / O.
It has two sets of data that propagate to the line. These two sets of data from the two columns are selected by CA11-CA2 and CA0. CRSS allows the replacement of either one of these two columns to be selected. Also, these two columns of the same sense amplifier bank can be replaced simultaneously.

CRSS is a gate 12-input NOR 'structure. Its input comes from the CRY circuit. In column redundancy programming, columns CA9 to CA2
Does select the column with the even GLOBAL I / O, its corresponding fuse for that decoder address in CRSS0 will not blow. Therefore, when selected, the node N of the active column redundancy decoder
5 is high and active CRSS0_ and CRSS0
Generate output. At the same time, it is not desirable to indicate that other columns with odd Global I / O are redundant columns. Therefore, the fuse for the corresponding decoder signal in CRSS1 is blown.

When only a column having an odd GLOBAL I / O is selected, the fuse in CRSS1 is not blown and the fuse in CRSS0 is blown. However, if you want to use both columns as redundant columns, these 2
Both corresponding fuses in the circuit are left open.
All pull-down transistors of the NOR 'gate are controlled by the CRDPC signal. In the precharge cycle, all inputs are grounded. In an active cycle, CRDPC is biased into the 1.5V to 1.6V region. This is to keep the blown input at a precharged low level. Here, the selection bias is performed in consideration of not grounding the high input where the fuse is not blown.

CRQS-COLUMN REDUNDA
CY QUADRANT SELECT-schematic diagram The purpose of CRQS is to identify the quadrant to which the redundant column belongs. The device has four CRQS circuits. Each CRQS represents one quadrant. Programming within the CRQS circuit is independent of each other, thus allowing one redundant decoder to program the same column address in more than one quadrant.

The CRQS circuit is basically the same as the CRSS structure. It has a 12 input NOR 'gate with CRDPC as the precharge signal. CRPPC
And the pull-down transistor serves the same purpose as in CRSS. The input to the NOR 'gate is the buffered output from CRY. CRS during precharge
There is the same problem of high current as in the case of S, and the same countermeasure as in the case of CRSS is taken. At the time of redundancy programming, the fuse corresponding to the output of the desired address is not cut off, indicating that the redundant column belongs to a certain quadrant. The fuse at the decoder output is blown to its CRQS to indicate that the redundant column does not belong to a particular quadrant. In addition to the regular select signals, CRQS_Q and CRQSQ, another signal is generated. This is DFT COLUMN
Used for REDUNDANCY ROW CALL.

CRYS-COLUMN REDUNDA
NCY SELECT-Circuit diagram FIG. 58 CODE APPENDIX 11 This circuit performs the final decoding of the redundant address and excites the redundant sense amplifier transfer gate to GL the data.
Propagate through the OBAL I / O line. The output signal is the Y from the YDEC circuit, except that it excites two sense amplifiers in the array block instead of four sense amplifiers.
It is equivalent to the SEL signal.

CLIOS-COLUMN REDUND
ANCY I / O SELECT-Circuit Diagram FIG. 59 As described above, there is an odd-even GLOBAL I / O line for each sense amplifier bank. Excitation of even or odd redundant sense amplifiers depends on the programming of the CRSS0 and CRSS1 circuits. However, this programming causes the redundant sense amplifiers to be simply energized to their respective G
Please understand that it only propagates data to the LOCAL I / O line. The normal sense amplifier operation in the array block is not interrupted, and the data propagates from the normal sense amplifier bank to the GLOBAL I / O line. CRI
What data set is actually GLOBAL I / O
Select whether the line is passed. There are four CRIOS circuits, each controlling one quadrant of the array. C
RIOS takes the CRSS0 and CRSS1 signals and combines them with CRQSQ to generate multiplexed signals CRIOSJK0 and CRIOSJK1. CRIOSJK0 is even G
Used to select LOCAL I / O line CR
IOSJK1 is used for odd GLOBAL I / O lines.

CRDPC-COLUMN DELAY
REDUNDANCY PRECHARGE-Circuit Diagram FIG. 60 CRDDPC produces a constant output of 1.5-1.6V. This output is used to adjust the pull-down transistors in CRSS and CRQS. Active cycle, or active CLE, to minimize current
A constant voltage level is generated only in N or active RL1_. RL1_ provides early setting of the output to the adjusted value, CLEN maintains it for a delay period after RL1_ is in the inactive state.

CRDSP-COLUMN REDUND
ANCY DECODER SETPULSE-Circuit Diagram FIG. 61 This circuit is basically the same as the row redundancy, RRDSP circuit, and four pulses are generated in the circuit. These are used for column address latching in the CRRA and CRCA circuits. Pulse is CRD from RRDSP
Triggered by the ST signal, ie after all row redundancy addresses have been latched.

INPUT / OUTPUT CIRCUI
T CATD-COLUMN ADDRESS TRANS
ISION DETECTOR-Circuit Diagram As can be seen from the name in FIG. 62, this circuit detects a change in column address. There are nine of these circuits. They detect changes in the addresses CA2-CA9 and the CLEN_ signal. The purpose of the CATD is to inform the device that it will perform a proper initialization whenever there is a new dataset to be dumped to the I / O line. It also enables the device to operate in "ENHANCED PAGE 'mode, ie, when the column address changes, the I / O lines are preset to idle before a new data set is propagated.

Please note that only CA2-CA9 are used. CA10, CA11, CA11 and CA
0 is not required because it is the address line used to select quadrants and I / O lines. CA2 to CA9 are addresses that determine the column factor and excite Y select. Thus, they select the column sets that propagate the data to the I / O lines. For CLEN_,
This signal times the propagation of an external address as a column address. Thus, the excitation of this signal initiates the acceptance of the column address and the propagation of the column data via the I / O line. Therefore, it is necessary to detect the transition of CLEN_ in order to perform an appropriate preset.

In PAGE 'mode operation, I / O
Propagation of active data through the line is initiated by the detection of CLEN_ transition. Whenever the column address changes, the next data set can be PAGED. The CATD circuit consists of two special composite gates. The special gate is a totem pole with two p-ch gates and two n-ch gates. The top p-ch of the composite gate is the bottom n-ch of the other composite gate.
, And the gate of the p-ch is connected via an inverter. For circuit performance, see APPENDIX
15 are described. Delay generators SD1 and S
Note that D2 is only the delay for the high-to-low transition.

CLSUM-COLUMN LOGIC
SUMMotion-Schematic Figure 63 CLSUM combines all CATD outputs together CA
Due to the preset and initialization conditions mentioned in the TD section,
Gives a set of signals for the device to use. First to occur
Is ATDOP_, which is simply the union of all CATD outputs and has the same polarity as CATD. The ATDOP signal is inverted in the CLSUMDR circuit and buffered into four separate ATDP signals. AT
The DO pulse is the LOCAL I / O in the IOCLMP circuit.
Used to initialize the line. The ATD1P_ signal is generated by combining all CATD signals and CLEN_. The ATD1P signal is then inverted in a CLSUMDR circuit and buffered into four separate signals.

The ATD1 signal is at the logic 1'level during the precharge cycle and flips to the low level due to the falling edge of the ATDO pulse. During the PAGE mode, another ATDO pulse is generated by the transition of any column address, CA2 to CA9. This makes ATD
An ATD1 pulse that is 2 nS longer than the O pulse is generated.
The ATD1 signal controls the data amplification via the LOCAL I / O AMP circuit.

The last signal generated is the STPH signal. The gated CATD signal triggers STPH from logic '0' to logic '1' on the trailing edge of the pulse. When STPH is triggered, it is latched until reset on precharge. By doing so, it acts as an interlock of activity, and the stopping of the `T 'signal only occurs after completion of I / O line initialization. This is to avoid interruption of the sensing operation due to I / O initialization. In addition, PA
The sense amplifier is isolated if there is new data dumped to the I / O path during GE 'mode.

CLRSUMDR-COLUMN LOG
IC DRIVER-schematic FIG. 64 The CLUSMDR circuit takes in the ATD0P_ and ATD2P_ signals and inverts each to buffer four separate ATD0 and ATD2 signals. The four outputs from each signal go to the 4-array quadrant and are placed in close proximity to the quadrant on which it operates. The purpose of these signals is described in the CLSUM section.

QDDEC-QUADRANT
SELECT QDDEC_CODE-QUADRANT SELECT
TCODE-schematic FIG. 65 APPENDIX — 12 — QDDEC performs active quadrant selection decoding. QDDEC_CODE indicates a decoding circuit. There are four DATA LINEs in the device, each representing a quadrant. The addresses CA10 to CA11 are used for decoding. Four D's for X1 devices
Only one ATA LINE is active, X4
In the device, all four DATA LINEs are active due to valid data. C in X4 operation
The pass gate CPGL2 is disabled by the LX4 signal, masking off the address decoding. CL
X4 enables all four QDDECs by pulling up nodes N6-NP1. Device is D
When in FT X16 or X32 mode, all four DATA LINEs are excited regardless of device type. The DFT signals TL16 and TL32_ block the pass gate CPGL2 and pull up the nodes N7 to MP2.

For X4 devices, "WRITE"
There is a PER BIT 'operation. This action gives the user the option of selecting the quadrant to be masked off, ie no data is written to that quadrant during the write cycle. In this operation, the WMBQ signal is logic '0' if the quadrant is masked off, and logic '1' otherwise. By this logic `0 ′, the pass gate CPGL2 is cut off and MN2 and MN
The output is disabled by pulling node N7 low through 1. By having the MN1 controlled by the DFT signal, it acts as an interlock, ie the WRITEPER BIT
Please note that ´ operates only in non-DFT mode. In addition to the main operation of decoding the active quadrant, Q
DDEC is a 2K REFRESH, X4 device I / O
It produces the other two signals required for O-line decoding. Two signals are TWOKADQ and FOURKADQ
Is. These signals are generated by combining CLX4 and TWOKREF. The active TWOKADQ signal represents an X4 device operating in 2K refresh mode. Active FORKADQ represents all X1 devices or only one X4 device with 4K refresh. GASELE-GLOBAL AMPLIFIER S
ELECT END GASEL-GLOBAL AMPLIFIERS
ELECT-Schematics Figure 66, Figure 67-APPENDIX 13 and 14 There are eight GLOBAL I / O lines in one quadrant.
In the normal read operation, only one of the eight data lines is selected and data can be propagated to the quadrant DATA LINE. In the regular write cycle, quadrant DA
Write data on TA LINE is one GLOBAL
Propagated to I / O line. This selection is GASEL and G
Performed by ASELE. 4 GASEs in one quadrant
There are LE and four GASEL circuits. Used to select one of the eight GLOBAL I / O lines, each of which is excited. In addition to simply making a 1 in 8 election, these circuits are used to excite only the GLOBAL ALI / O lines in the active quadrant using the QDDEC_ signal.

The GLOBAL I / O line is GASEL A
The method classified into ND GASELE is as follows. GASELE-GLOBAL I / O # 0, 1, 4 &
5, i.e. END I / O line GASEL-GLOBAL I / O # 2, 3, 6 &
7, that is, Normal I / O line It is the end G that requires the two types of decoding.
This is because the LOCAL I / O lines (# 0, 1, 4 & 5) require more complicated decoding than the other four GLOBAL I / O lines. Regular GLOBAL I
For the / O line, note that the address RA11 is either logic high or logic low. However, for the end GLOBAL I / O lines, the decoding circuit will be logical high (R) for global I / O selection.
Both A11) and a logic low (RA_11) are required.

With respect to the above description, the following items will be further disclosed. (1) In a memory device, the memory device has a plurality of memory arrays having memory cells arranged in rows and columns and redundant rows of memory cells replaced with defective rows, and information is read from and written to the memory cells. A memory device comprising a support circuit, the support circuit including a row redundancy circuit responsive to a defective row address of a memory cell to select a redundant row of memory cells only within a memory array having a defective row of memory cells.

(2) In the memory device according to item (1), the row redundancy circuit is programmable to hold a defective row address and holds information for identifying a memory array including a defective row of memory cells. A memory device including a programmable two-stage programmable row redundancy decoder.

(3) In a memory device, the memory device responds to a plurality of memory arrays having memory cells arranged in rows and columns and redundant columns of memory cells to replace defective columns, and addresses of defective columns of the memory cells. Memory device having a column redundancy circuit for selecting a redundant column of memory cells only in a memory array having a defective column of memory cells.

(4) In the memory device according to item (3), the column redundancy circuit is programmable to hold a defective column address and holds information for identifying a memory array including a defective column of memory cells. A memory device including a programmable two-stage programmable column redundancy decoder.

(5) In the memory device according to item (1) or (2), the device holds an address of a defective row, receives the row address, and outputs a redundant row decoder signal and a redundant row factor signal. A first redundant decoder for generating, a second redundant decoder for holding a position of an array including a defective row, receiving a redundant row decode signal and generating an array selection signal, and a redundant low factor of a first redundant recorder. A memory including a enable enable signal, an array select signal of a second redundant decoder, and a redundant enabler circuit connected to a redundant row of memory cells to enable selected redundant rows of memory cells in a memory array having defective rows of memory cells. device.

(6) In the memory device according to item (3) or (4), the memory device holds an address of a defective column, receives the column address, and outputs a redundant column decode signal and a redundant column factor signal. A first redundant decoder programmable to generate a signal, a second redundant decoder programmable to hold the position of the array including the defective column, receive a redundant column decode signal and generate an array selection signal, A redundancy column factor enable signal of the first redundancy decoder, an array selection signal of the second redundancy decoder and a selected redundancy column of memory cells in the memory array having a defective column of memory cells connected to the redundancy column of memory cells; A memory device including redundant enabler circuitry to enable.

(7) The memory device according to any one of the above items, which includes both a row redundant circuit and a column redundant circuit.

(8) The memory device according to any one of the above items, wherein the device is a dynamic random access memory.

(9) In a method of repairing a defective memory cell in a semiconductor memory device having more than one memory array, the method programming the first circuit with the address of the defective memory cell, A method of repairing a defective memory cell, the method comprising: programming a second circuit according to a position of a memory array having the defective memory cell and selecting a redundant memory cell in the memory array having the defective memory cell when receiving an address of the defective memory cell.

(10) The method according to the item (9), wherein the defective memory cell is a defective row memory cell and the redundant memory cell is a redundant row memory cell.

(11) The method of repairing a defective memory cell according to the method described in (9), wherein the defective memory cell is a defective column cell and the redundant memory cell is a redundant column memory cell.

(12) A two-stage redundant decoding circuit for semiconductor memory device is disclosed. The redundant row decoder is programmable to hold an address of a defective row and receives the row address to generate a redundant row decode signal and a redundant row factor enable signal.
It is a two-stage decoder having a redundant decoder of. The second redundant decoder is programmable to hold the position of the array containing the defective row. It receives the redundant row decode signal and generates an array select signal. A third enabler stage is connected to the redundant row of memory cells and responsive to the redundant row factor enable signal and the array select signal to enable the selected redundant row of memory cells of the memory array including the defective row of memory cells. be able to. The redundant column decoder can be programmed to hold the address of the defective column. It receives the column address and generates a redundant column decode signal and a redundant column factor enable signal. The second redundant decoder can be programmed to retain the position of the array containing the defective column. It receives the redundant column decode signal and generates an array select signal.
Enabling a selected redundant column of memory cells of a memory array including a defective column of memory cells by adding a third enabler stage connected to the redundant column of memory cells and responsive to a redundant column factor enable signal and an array select signal. can do. The decoding circuit uniquely identifies the portion of the memory that needs repair to make more efficient use of available redundant memory cells.

Appendix A1 shows the Row Factor code table. The Row Factor code indicates the relationship between the RF signal and the RAW / RAW signals. The RFR signal is the output of 12 examples of circuit 16.

Appendix 2 is Row Decoder Dri
Indicates a ver code. Row Deco shown in circuit 19
The der driver circuit is used 32 times in each of the four quadrants of the circuit. The RDDR_CODE table shown in Appendix A2 describes the relationship between the output signals RDJ0K0-RDJ7K3 and the signals in each quadrant.

Appendixes 3 and 4 show Row in two tables.
A Redundancy Address code is shown, the first of which is labeled RRA CODE1 and the second of which is labeled RRA_CODE2. The circuit 22, the Row Redundancy Address circuit, is used 120 times in the chip. Appendix A5
And tables RRA_CODE1 and RRQ shown in A7
A_CODE2 shows how 120 examples of RRA circuits are used in the chip to generate the RRAO_RRA119 output signal.

Appendix 5 shows the Bank Select code. The Bank Select code shows how 15 examples of BNKSL circuits, circuit 35, are used to generate 16 unique outputs for each quadrant.

Appendix 6 is the Sense Amplifier
Here is the code. The SA circuit and the circuit 41 are 7, 6 in each quadrant.
Used 80 times. The SA_CODE table shows the connections for these examples of SA circuits.

Appendix 7 shows the Column Factor code. The Column Factor code shows how to use the 16 Column Factor circuits. These are eight examples of column factor circuit CF07 and circuit 46, and column factor circuit CF815,
8 is an example of the circuit 48. CF_COD shown in Appendix A7
The E table shows the connections of these 16 circuits.

Appendix 8 is Column Redundan
5 shows a cy Row Address Code table. Column Redundancy Row A
The address code table is the CRR shown in FIG.
It shows how the A circuit is used in a DRAM. C
The RRA circuit has been used 36 times in DRAM and the CRRA_CODE table shown on page 8 of the appendix shows the detailed connections of 36 examples of the circuit.

Appendices 9 and 10 show the CRCA_CODE table. Column Redund shown in FIG.
the ancy Column Address circuit is DRA
Used 96 times in M. The tables on pages 9 and 10 of the appendix show the detailed connections of the CRCA circuit for 96 times.

Appendix 11 shows the CRYS_CODE table. The CRYS circuit shown in FIG. 58 is used 24 times in the DRAM. CRYS_CODE shown on page A11 of the Appendix
The table shows 24 detailed connections of the CRYS circuit.

Appendix 12 is Quadrant Select
t code is shown. The QuadrantSelect code indicates a decoding circuit for active quadrant selection. The quadrant selection circuit is shown in circuit 65. By referring to the QDDEC_CODE table, it is possible to determine which of the four quadrants is the currently selected quadrant according to the circuit 65.

Appendixes 13 and 14 are Global respectively
The codes of the Amplifier Select End circuit and the Global Amplifier Select circuit are shown. Global Amplifier
The Select circuit implements one of eight codes. The code given in the Appendix shows how the decoding is done in combination with the circuit diagrams 66, 67. Next, the operation of the embodiment will be described in detail.

[Table 3]

[Table 4]

[Table 5]

[Table 6]

[Table 7]

[Table 8]

[Table 9]

[Table 10]

[Table 11]

[Table 12]

[Table 13]

[Table 14]

[Table 15]

[Table 16]

[Table 17]

[Brief description of drawings]

FIG. 1 is a block level diagram illustrating a 16MB dynamic random access memory chip incorporating an embodiment of the present invention.

FIG. 2 is a plan view showing a pin arrangement of a package memory chip.

FIG. 3 is a three-dimensional view of a package memory chip with a transparent sealant.

FIG. 4 is an assembly diagram of FIG.

5 is a sectional view of FIG.

FIG. 6 is a plan view showing a bond pad arrangement of a memory chip.

FIG. 7 is a plan view showing a part of a memory array.

FIG. 8 is a cross-sectional view showing a part of a memory array.

9 is a side view of the cross-sectional view of FIG.

FIG. 10 is a diagram showing CL1, that is, a column logic circuit.

FIG. 11: RBC, Ras Before C
The figure which shows an as circuit.

FIG. 12: RBC_RESET circuit, ie Ras
The figure which shows a Before Cas Reset circuit.

FIG. 13: PADABUF, or Pad Addr
The figure which shows an ess Buffer circuit.

FIG. 14 RADR, that is, Row Address
The figure which shows a Driver circuit.

FIG. 15: BITCOUNT, or Bit Cou
The figure which shows an nt circuit.

FIG. 16 is a diagram showing RF, that is, a Row Factor circuit. The code is Appendix A1.

FIG. 17: RLEN_, that is, Row Logic
The figure which shows an Enable circuit.

FIG. 18: RLXH, or Row Logic X
The figure which shows a (Word) High circuit.

FIG. 19: RDDR, or Row Decoder
The figure which shows a Driver circuit. The code is Appendix A3.

FIG. 20: BNKPC_, that is, Bank Sele
The figure which shows a ct Pre-charge circuit.

FIG. 21: XDECM, that is, Row Decode
The figure which shows an r circuit.

FIG. 22: RRA, or Row Redundan
The figure which shows a cy Address circuit.

FIG. 23: RRDEC, or Row Redund
FIG. 3 is a diagram showing an anacy Decoder circuit.

FIG. 24: RRX, or Row Redundan
The figure which shows a cy X Factor circuit.

FIG. 25: RRXE, or Row Redunda
The figure which shows a ncy X Factor Emulator circuit.

FIG. 26: RRQS, or Row Redunda
The figure which shows a ncy Quadrant Select circuit.

FIG. 27: RXDEC, or Redundancy
The figure which shows a X (Word) Decoder circuit.

FIG. 28: RRDSP, or Row Redund
The figure which shows the ancy circuit.

FIG. 29: RRATTST, or Row Redun
The figure which shows a dancy Address Test circuit.

FIG. 30: SDXWD, or Sense Cloc
The figure which shows a kX-Word Detect circuit.

FIG. 31: SDS1, namely Master Sens
The figure which shows an e-Clock circuit.

FIG. 32: SDS2, or Sense Clock
2 is a diagram showing a circuit.

FIG. 33: SDS3, or Sense Clock
3 is a diagram showing a circuit. FIG.

FIG. 34: SDS4, or Sense Clock
4 is a diagram showing a circuit.

FIG. 35: BNKSL, or Bank Select
The figure which shows a t circuit. The code is Appendix A9.

FIG. 36. BSS_DR, or Bank Sele
The figure which shows a ct Driver circuit.

FIG. 37: LENDBNKSL, or LEFT E
The figure which shows a ND BANK SELECT circuit.

FIG. 38 is a diagram showing BSS_DR.

FIG. 39: 11234, Sense Cloc
The figure which shows a k1234 circuit.

FIG. 40 is a diagram showing a PCNC, that is, a P-charge and N-charge circuit.

FIG. 41 SA, or Sense Amplifi
The figure which shows an er circuit. The code is Appendix A11.

FIG. 42 SA_END or Sense Amp
The figure which shows a lifier End circuit.

FIG. 43: CABUF01, ie, Column A
FIG. 3 is a diagram showing a ddress Buffer01 circuit.

FIG. 44: CABUF29, Column A
The figure which shows the address Buffer 29 circuit.

FIG. 45: CLEN, Column Logi
FIG. 6 is a diagram showing a c Enable circuit.

FIG. 46: CF07, that is, Column Fact
The figure which shows or0,7 circuit. The code is Appendix A13.

FIG. 47: CF07DR, that is, Column Fa
The figure which shows a ctor0,7Driver circuit.

FIG. 48: CF815, Column Fac
The figure which shows tor8-15 circuits.

FIG. 49 is a diagram showing a YDEC, that is, a Y Decoder circuit.

FIG. 50: CRDEC, or Column Red
FIG. 3 is a diagram showing an undandy Coder Enable circuit.

FIG. 51: CRRA, Column Redu
FIG. 3 is a diagram showing an ndancy Row Address circuit.
The code is Appendix A35.

FIG. 52 CRCA, or Column Redu
FIG. 3 is a diagram showing an ndandy Address circuit. The code is Appendix A37 and A39.

FIG. 53: CREDC_, ie, Column Re
FIG. 3 is a diagram showing a dunnancy decoder circuit.

FIG. 54: CRDEC or Column Red
FIG. 3 is a diagram showing an undandy Coder Enable circuit.

FIG. 55: CRY, Column Redun
The figure which shows a dancy Y Factor circuit. The code is Appendix A41.

FIG. 56: CRSS or Column Redu
FIG. 3 is a diagram showing an ndancy SegmentSelect circuit.

FIG. 57: CRRS, Column Redu
FIG. 3 is a diagram showing an ndan quadrant circuit.

FIG. 58: CRYS, Column Redu
FIG. 3 is a diagram showing an ndancy Y Select circuit.

FIG. 59: CRIOS, or Column Red
FIG. 3 is a diagram showing an undan U Select circuit.

FIG. 60: CRDPC or Column Del
The figure which shows an ay Redundancy Pre-charge circuit.

FIG. 61 is a diagram showing a CROSP circuit.

FIG. 62: CATD or Column Addr
FIG. 6 is a diagram showing an ess Transition Detector circuit.

FIG. 63: CLSUM, Column Log
The figure which shows an ic Summation circuit.

FIG. 64: CLSUMDR, or Column S
The figure which shows a um Logic Driver circuit.

FIG. 65: QDDEC, or Quadrant S
The figure which shows an elect circuit. The code is Appendix A15.

FIG. 66: GASEC or Global Amp
The figure which shows a lifier Select End circuit.

FIG. 67: GASEL, that is, Global Amp
The figure which shows a lifier Select circuit.

68 is a diagram illustrating a 16-Meg sense amplifier circuit. FIG.

FIG. 69 is a diagram illustrating a 16-Meg sense amplifier circuit.

FIG. 70 is a diagram illustrating a 16-Meg sense amplifier circuit.

[Explanation of symbols]

CL1 Column logic circuit RBC Ras Before Cass circuit RBC_RESET Ras Before Cass reset circuit PADABUF pad address buffer circuit RADR low address driver circuit BITCOUNT bit count circuit RF low factor circuit RLEN_low logic enable circuit RLXH low logic R (DR) high circuit RDR Driver circuit BNKPC_ Bank select precharge circuit XDECM Row decoder circuit RRA Row redundancy address circuit RRDEC Row redundancy decoder circuit RRX Row redundancy X factor circuit RRXE Row redundancy X factor emulator circuit RRQS Row redundancy quadrant selection circuit RXDEC redundancy X (word) decoder circuit RRDSP Low redundancy circuit RRATTST low Redundant address test circuit SDXWD Sense clock X word detection circuit SDS1 Master sense clock circuit DSD2 Sense clock 2 circuit SDS3 Sense clock 3 circuit SDS4 Sense clock 4 circuit BNKSL Bank selection circuit BSS_DR Bank selection driver circuit LENDBNKSL Left end bank selection circuit 11234 Sense clock 1234 circuit PCNC P charge and N charge circuit SA sense amplifier circuit SA_END sense amplifier end circuit CABUF01 column address buffer 01 circuit CABUF29 column address buffer 29 circuit CLEN column logic enable circuit CF07 column factor 0,7 circuit CF07DR column factor 0,7 driver circuit CF815 column Factor 8 to 15 circuits YD EC Y decoder circuit CRDEC column redundancy decoder enable circuit CRRA column redundancy row address circuit CRCA column redundancy address circuit CREDC_ column redundancy decoder circuit CRY column redundancy Y factor circuit CRSS column redundancy segment selection circuit CRSS column redundancy quadrant circuit CRYS column redundancy Y selection circuit CRIOS Column redundancy U selection circuit CRDPC Column delay redundancy precharge circuit CROSP CROSP circuit CATD Column address transition detector circuit CLSUM Column logic addition circuit CLSUMDR Column sum logic driver circuit QDDEC Quadrant selection circuit GASEC global amplifier selection end circuit GASEL global amplifier selection circuit EXTBLR pad XTTLCLK TTL / CMOS converter XTTLA DD converter XRS1 interlock latch XRS3 〃 XSDEL1_1 delay stage NR3 NOR gate NR4 〃 NR5 〃 IV1 〃 MN 〃 MN 〃 MN 〃 MN 〃 MN 〃 MN 4 MN 〃 MP4 MN 〃 MN4 MN1 MN10 N-channel transistor MN11 〃 MN13 〃 MN16 〃 MN19 〃

Claims (2)

[Claims] 1. A memory device, the memory device comprising: a plurality of memory arrays having memory cells arranged in rows and columns and redundant rows of memory cells replaced by defective rows; and information read from and into the memory cells. A memory device comprising a row redundancy circuit for selecting a redundant row of memory cells only in a memory array having a defective row of memory cells in response to an address of the defective row of memory cells. . 2. A method of repairing a defective memory cell in a semiconductor memory device having more than one memory array, the method comprising first by a defective memory cell address.
The second circuit according to the position of the memory array having the defective memory cell and selecting a redundant memory cell in the memory array having the defective memory cell upon receipt of the address of the defective memory cell. Defective memory cell repair method.