JPH0729371A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To reduce chip area by sharing one set of sense-amplifier with divided plural memory cell arrays and reducing the forming area for parts of the sense- amplifiers concerned. CONSTITUTION:After one of memory arrays 40, 50 is selected with selection control lines S1, S2, local word lines LW11,... are selected and then storage information of memory cells 41,... are transferred to column decoders 43, 53. Selection control lines S1, S2 and a column selection line CC are ANDed in AND circuits 65, 66 and then only the column decoder 43 in the selected memory array 40 is made active. Then, read-out information of the memory cell transferred to data lines D11, D12 are inputted to a sense-amplifier 70 via a wired OR and amplified by the sense-amplifier 70 to be transferred to data busses.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention operates when a plurality of divided memory cell arrays are driven by a set of sense amplifiers in a semiconductor memory such as a static RAM (random access memory) that can be read and written at any time. The present invention relates to a column decoder selection driving technique of closing a column switch of a memory cell array which is not operated and driving only an operating memory cell array by a sense amplifier.

[0002]

2. Description of the Related Art Conventionally, as a technique in such a field,
For example, some documents were described in the following documents. References; IEEE Journal of Solid Circuit (IEEE JOURNAL OF SOLI
D-STATE CIRCUITS), 24 [5] (1989-10) (US) KATSU
ROA SASAKI et al: “9-ns 1-Mbit CMOS SRAM” P.1219-1
225 Conventionally, as described in the above-mentioned document, in a semiconductor memory, when a memory cell is divided into a plurality of memory cell arrays to operate, the divided memory cell array and the sense amplifier always have a one-to-one correspondence relationship. It has become. For example, Parallel-Word-Ac for the purpose of operating a redundant circuit for relieving a defective memory cell at high speed.
In the cess Redundancy Architecure, the spare word line is placed in a memory cell different from the operating memory cell. And if a bad memory cell is found,
By switching to the sense amplifier connected to the spare word line, it is possible to continue reading without theoretically affecting the operation time. This Parallel-Wor
FIG. 2 shows a schematic configuration diagram of a conventional static RAM using the d-Access Redundancy Architecure. The static RAM has a plurality of divided memory cell arrays 10 and 20 having the same structure, and sense amplifiers 16 and 26 are provided in the memory cell arrays 10 and 20, respectively.

The memory cell array 10 has a plurality of word lines W1 and a spare word line SW2, and a plurality of pairs of bit lines B11 and B12 are crossed with each other. A memory cell 11 is connected to each of intersections of a plurality of word lines W1 and a plurality of pairs of bit lines B11, B12, and a spare word line SW2 and a plurality of bit lines B11, B12.
The memory cell 12 for the redundant circuit is also provided at the intersection of the 12 pairs.
Are connected respectively. Each word line W1 is activated by the AND circuit 13 connected to the selection signal line Y1, and the spare word line SW2 is activated by the AND circuit 14 connected to the selection signal line Y2. .
A column decoder 1 is provided for the pair of bit lines B11 and B12.
5, the column decoder 15 is connected to the data bus DB via the sense amplifier 16.
Similarly, the memory cell array 20 has a plurality of word lines W2.
And a spare word line SW1, and a plurality of pairs of bit lines B21 and B22 are crossed with each other. A memory cell 21 is connected to each intersection of the plurality of word lines W2 and each pair of the plurality of bit lines B21, B22, and a redundant circuit is also provided at each intersection of the spare word line SW1 and the pair of bit lines B21, B22. Memory cell 22 for connection is connected. The word line W2 is activated by the AND circuit 23 connected to the selection signal line Y2, and the spare word line S is further activated.
W1 is activated by the AND circuit 24 connected to the selection signal line Y1. A column decoder 25 is connected to the plurality of pairs of bit lines B21 and B22,
Further, the column decoder 25 is connected to the data bus DB via a sense amplifier 26. Sense amplifier 1
6 and 26 are selection signal lines Y via the switches 31 and 32.
1 and Y2 are selectively driven.

Next, the operation will be described. Spare word line S
W1 is in the memory cell array 20, and the spare word line SW2 is arranged in the memory cell array 10. The selection signal lines Y1 and Y2 are connected to the memory cell array 10,
It is a signal line for selecting 20 and, for example, a configuration in which the word lines W1 and W2 of the memory cell arrays 10 and 20 on the side of either high level (hereinafter, referred to as “1”) are activated is assumed. . When the selection signal line Y1 is "1", the AND circuits 13 and 24 activate the word line W1 and the spare word line SW1. At this time, the stored information in the memory cell 11 is selected by the column decoder 15 connected to the pair of bit lines B11 and B12 and transmitted to the sense amplifier 16. At the same time, the information stored in the memory cell 22 is selected by the column decoder 25 connected to the pair of bit lines B21 and B22 and transmitted to the sense amplifier 26. Here, the switch 31 is tilted upward and the switch 32
When the memory cell 11 is turned down, only the sense amplifier 16 becomes active.
Stored information is amplified and transmitted to the data bus DB.
If the memory cell 11 is a defective memory cell,
The switch 31 is turned down and the switch 32 is turned up to activate the sense amplifier 26. Then, the stored information of the memory cell 22 for the redundant circuit is changed to the bit lines B21 and B21.
It is selected by the column decoders 25 connected in 22 pairs, amplified by the sense amplifier 26, and transmitted to the data bus DB. At this time, since the switching time of the switches 31 and 32 is very short, the redundant circuit can be operated at high speed.

[0005]

However, in the conventional static RAM, each memory cell array 10, 2 is
Since one set of sense amplifiers 16 and 26 is provided for each 0, the divided memory cell arrays 10 and 20 are divided.
If the number of divisions of the sense amplifier 16 increases,
There is a problem that the number of 26 also increases and the formation area of the sense amplifier portion increases and the chip area increases, which is difficult to solve. SUMMARY OF THE INVENTION The present invention provides a semiconductor memory that solves the problem that the prior art has, that is, the formation area of the sense amplifier portion increases and the chip area increases.

[0006]

In order to solve the above-mentioned problems, a first invention has a plurality of divided memory cell arrays, and each of the memory cell arrays crosses a plurality of word lines and bit lines. In a semiconductor memory such as a static RAM configured by a plurality of memory cells for storing data connected in a matrix and arranged in a matrix, a selection control line for selecting a memory cell array provided for each memory cell array, and all of the above Column selection lines commonly used in the memory cell array and local column selection lines wired in each of the memory cell arrays. Further, a logic circuit for selectively activating the local column selection line by taking the logic of the selection control line and the column selection line, and provided in each of the memory cell arrays, and driven and controlled by the local column selection line. A column decoder for bit line selection, an integrating means for integrating the data lines from all the column decoders, and a set of sense amplifiers for detecting and amplifying the data from the integrating means,
It is provided. In a second invention, the logic circuit of the first invention is configured by an AND circuit or an OR circuit, and the integrating means is a wired OR, an OR circuit, an AND circuit, or a transfer gate controlled by a set of control lines. It consists of either one.

[0007]

According to the first invention, since the semiconductor memory is configured as described above, the memory cell array is selected by the selection control line. Then, when the storage information of the memory cell in the selected memory cell array is read, the logic of the selection control line and the column selection line is taken, and only the column decoder in the selected memory cell array operates. To do. When the column decoder operates, the storage information read from the memory cell is selected by the column decoder and sent to the data line, and the storage information on the data line is input to the sense amplifier via the integrating means. At this time, since only one set of column decoders is active at any one time,
The read stored information does not collide in the sense amplifier and is accurately amplified by the set of sense amplifiers. In this way, since one set of sense amplifiers can be commonly used in a plurality of memory cell arrays, the formation area of the sense amplifier portion can be reduced. According to the second aspect of the present invention, the stored information of the memory cell sent from the column decoder to the data line is accurately input to the sense amplifier via the integrating means such as the wire OR without the stored information colliding. . Therefore, the above problem can be solved.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 shows a static RA showing a first embodiment of the present invention.
It is a schematic block diagram of M. This static RAM is
A plurality of divided memory cell arrays 40 and 5 having the same configuration
Has 0. The memory cell array 40 has a plurality of local word lines LW11 and LW12 and a plurality of bit line pairs B11 and B12 arranged to intersect with the local word lines LW11 and LW12, and a plurality of memory cells 41 and 42 are connected to the intersections. ing. Each of the memory cells 41 and 42 is composed of a flip-flop in which transistors for storing information are connected in a crossed manner, and the local word lines LW11 and LW are connected.
Bit line B1 is turned on by "1" of 12
It is electrically connected to the pair of B1 and B12. The local column selection line LC is connected to the plurality of pairs of bit lines B11 and B12.
A column decoder 43 for selecting a bit line which is driven and controlled by 1 is connected, and the column decoder 43 is further connected to data lines D11 and D12. Similar to the memory cell array 40, the memory cell array 50 has a plurality of local word lines LW21 and LW22 and a plurality of pairs of bit lines B21 and B22 arranged to intersect with the local word lines LW21 and LW22, and a plurality of memory cells 51 at the intersections thereof. , 52 are connected. A column decoder 53 for bit line selection driven and controlled by the local column selection line LC2 is connected to the plurality of bit line B21, B22 pairs, and data lines D21, D22 are further connected to the column decoder 53. Two selection control lines S1 and S2 for selecting them are provided between the memory cell arrays 40 and 50, and one selection control line S1 is a logic circuit (for example, 2).
Input AND circuits) 61, 63, 65 are connected to one input terminal, and the other selection control line S2 is connected to a logic circuit (eg,
Two-input AND circuits) 62, 64, 66 are connected to one input terminal. The main word line MW1 is connected to the other input terminals of the two-input AND circuits 61 and 62, the other input terminals of the two-input AND circuits 63 and 64 are connected to the main word line MW2, and the two-input AND circuits are further connected. The other input terminals of 65 and 66 are connected to the column selection line CC. Data line D1 from the column decoder 43
1 and D12, the data line D21 from the column decoder 53
And D22 are integrated means (for example, Wied O
R) and is connected to the input terminal of the sense amplifier 70. The sense amplifier 70 is a circuit that detects and amplifies the potential difference between D11 and D12 or D21 and D22 and outputs the amplified read information to the data bus DB.

Next, the operation will be described. For example, when the memory cell array 40 is active and the memory cell array 5
Assume that 0 is not working. When the main word line MW1 becomes "1" by a row decoder (not shown), the AND circuits 61 and 62 are opened, so that the local word lines LW11 and LW21 connected to the AND circuits 61 and 62 may be activated. When the selection control line S1 becomes "1", the output of the AND circuit 61 becomes "1" and the local word line LW11 connected to it becomes active.
Then, the information stored in the memory cell 41 is the bit line B11,
It is output to B12 and is transmitted to the column decoder 43. Here, when the column selection line CC is “1”,
Since the selection control line S1 is "1", the AND circuit 6
The output of 5 becomes "1", and the local column select line LC1 connected to it becomes enable. Then, the column decoder 43 operates, a pair of bit lines B11 and B12 is selected by a column address (not shown), and the storage information read from the memory cell 41 is transmitted to the data lines D11 and D12. In this embodiment, the data lines D11 and D12 from the column decoder 43 and the data lines D21 and D22 from the column decoder 53 are input to the sense amplifier 70 after being subjected to the wise OR. Therefore, in the above state, since the selection control line S2 is inactive (hereinafter referred to as "0"), the output of the AND circuit 66 connected thereto becomes "0" and the local column selection line LC2 also becomes "0". The column decoder 53 is closed. Therefore, no information flows from the column decoder 53 to the data lines D21 and D22,
Only the storage information of the data lines D11 and D12 is input to the sense amplifier 70. The inputted stored information is detected and amplified by the sense amplifier 70, and then sent to the data bus DB. On the other hand, when the stored information of the memory cells 51 and 52 in the memory cell array 50 is read, if the selection control line S2 is set to "1", the local column selection line LC2 is set to "1" via the AND circuit 66 connected thereto. "It becomes. At this time, the selection control line S1 is "0", and the local column selection line L is connected via the AND circuit 65 connected thereto.
C1 becomes "0". Therefore, the column decoder 53 becomes active and the column decoder 43 is closed.
As a result, contrary to the above, the information of the data lines D21 and D22 is input to the sense amplifier 70 through the column decoder 53, amplified by the sense amplifier 70 and sent to the data bus DB.

As described above, this embodiment has the following advantages. Local word lines LW11, LW12, LW21, LW22 of the memory cell arrays 40, 50
Selection control lines S1 and S2 for selecting the column selection line CC and the column selection line CC are ANDed by AND circuits 65 and 66, and the local column selection lines LC1 and LC are obtained according to the logical result.
2 is activated to operate the column decoders 43 and 53. Therefore, the selection control lines S1, S
Only the column decoders 43 and 53 in the memory cell arrays 40 and 50 selected in 2 become active. Therefore, the data lines D11, D from the plurality of column decoders 43, 53
Even if 12 and D21 and D22 are integrated by the wired OR and input to the sense amplifier 70, only one set of column decoders 43 or 53 is active at any one time, so that information may not collide in the sense amplifier 70. Absent. That is, since one set of sense amplifiers 70 is commonly used by the plurality of memory cell arrays 40 and 50, the formation area of this sense amplifier portion can be reduced and the chip area can be reduced. Further, in this embodiment, the data lines D11 and D12 are
And D21 and D22 are integrated by the wire-OR, the circuit configuration is simple.

Second Embodiment FIG. 3 is a static RA showing a second embodiment of the present invention.
It is a partial block diagram of M, and the same code | symbol is attached | subjected to the element common to the element in FIG. 1 which shows 1st Example. In the first embodiment, the data lines D11, D12, D21, D22 from the column decoders 43, 53 are added to the sense amplifier 70 by taking the wide OR, but in the present embodiment, instead of this, 2 The two 2-input OR circuits 81 and 82 constitute an integrating means. That is, the column decoders 43 and 5
3, the local column selection line LC1 or LC
2 is the data line D on the side of the disenable state
11 and D12 or D21 and D22 are set to "0", and the OR circuit 81 sets the data lines D12 and D22 to O.
The R circuit 82 integrates the data lines D11 and D22 and inputs them to the sense amplifier 70. As a result, the same operation and effect as those of the first embodiment can be obtained. In particular,
Since the OR circuits 81 and 82 are used, the input waveform of the sense amplifier 70 is better than that of the first embodiment.

Third Embodiment FIG. 4 shows a static RA showing a third embodiment of the present invention.
It is a partial block diagram of M, and the same code | symbol is attached | subjected to the element common to the element in FIG. 3 which shows 2nd Example. In this static RAM, AND circuits 83 and 84 are provided instead of the OR circuits 81 and 82 of FIG. That is,
In the column decoders 43 and 53, the data lines D11 and D12 or D21 and D22 on the side where the local column selection line LC1 or LC2 is disabled are set to "1", and the AND circuit 83 sets the data line D1.
2 and D22 are connected to the data lines D11 and D2 by the AND circuit 84.
2 are integrated and input to the sense amplifier 70. As a result, the same operation and effect as those of the second embodiment can be obtained. Further, if the AND circuits 83 and 84 are composed of N-channel MOS transistors, for example, the integration process can be speeded up.

Fourth Embodiment FIG. 5 shows a static RA showing a fourth embodiment of the present invention.
It is a partial block diagram of M, and the same code | symbol is attached | subjected to the element common to the element in FIG. 4 which shows 3rd Example. In this static RAM, instead of the AND circuits 83 and 84 of FIG. 4, an inverter 85 that inverts the control line CNT and an output of the control line CNT and the inverter 85 are turned on and off.
Transfer gates 86, 87, 88, 8 which are turned off
And 9 are provided. Then, by the output of the control line CNT and the inverter 85, the transfer gates 86 and 8
7 or the transfer gates 88 and 89 are operated to operate the data lines D12 and D22 or the data line D11.
Either one of the signals D1 and D21 is input to the sense amplifier 70. As a result, the same operation and effect as those of the third embodiment can be obtained.

The present invention is not limited to the above embodiment,
Various modifications are possible. The following are examples of such modifications. (A) By changing the polarities of the selection control lines S1 and S2,
The D circuits 61 to 66 may be replaced with OR circuits. (B) The above embodiment may be applied to another semiconductor memory such as a dynamic RAM other than the static RAM, or the integrating means may have a gate circuit configuration other than that shown in the drawing.

[0015]

As described in detail above, according to the first aspect of the present invention, the selection control line for selecting the local word line of the memory cell array and the column selection line are logically processed by a logic circuit. Since the local column selection line is selectively activated according to the logic result, only the column decoder in the memory cell array selected by the selection control line can be activated. Therefore, even if the data lines from a plurality of column decoders are integrated by the integrating means and input to the sense amplifier, only one set of column decoders is active at any time, so that information does not collide in the sense amplifier. As a result, since one set of sense amplifiers can be commonly used in a plurality of memory cell arrays, the formation area of the sense amplifier portion can be reduced, and thereby the chip area can be reduced. According to the second invention, the logic circuit is ANDed.
Since it is configured by the circuit or the OR circuit, the local column selection line can be properly activated. Moreover, since the unifying means is composed of one of a wire OR, an OR circuit, an AND circuit, or a transfer gate controlled by a set of control lines, it is relatively easy to integrate the data lines from a plurality of column decoders. Can be realized with a simple configuration.

[Brief description of drawings]

FIG. 1 is a static RA showing a first embodiment of the present invention.
It is a schematic block diagram of M.

FIG. 2 is a schematic configuration diagram of a conventional static RAM.

FIG. 3 is a static RA showing a second embodiment of the present invention.
It is a partial block diagram of M.

FIG. 4 is a static RA showing a third embodiment of the present invention.
It is a partial block diagram of M.

FIG. 5 is a static RA showing a fourth embodiment of the present invention.
It is a partial block diagram of M.

[Explanation of symbols]

40,50 memory cell array 41,42,51,52 memory cell 43,53 column decoder 61,62,63,64,65,66,83,84
AND circuit 70 Sense amplifier 81, 82 OR circuit 86, 87, 88, 89 Transfer gate B11, B12, B21, B22 Bit line CC Column select line CNT Control line D11, D12, D21, D22 Data line DB Data bus LC1, LC2 Local column selection lines LW11, LW12, LW21, LW22
Local word line MW1, MW2 Main word line S1, S2 Selection control line

Claims (2)

[Claims] 1. A memory cell array having a plurality of divided memory cell arrays, wherein the memory cell arrays are connected to respective intersections of a plurality of word lines and bit lines and arranged in a matrix. In the configured semiconductor memory, a selection control line for selecting a memory cell array provided for each memory cell array, a column selection line commonly used by all the memory cell arrays, and a wiring line in each memory cell array. A local column selection line; a logic circuit that selectively activates the local column selection line by taking the logic of the selection control line and the column selection line; and the local column selection line provided in each of the memory cell arrays. Column decoder for bit line selection driven and controlled by, and data from all the column decoders A semiconductor memory comprising: an integrating means for integrating lines; and a pair of sense amplifiers for detecting and amplifying data from the integrating means. 2. The logic circuit is an AND circuit or an OR circuit.
A semiconductor memory comprising a circuit, and the integrating means is configured by any one of a wired OR, an OR circuit, an AND circuit, or a transfer gate controlled by a set of control lines.