JPH0728947Y2 - Driving device for piezoelectric element - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to a driving device for a piezoelectric element.

[Prior Art] FIG. 3 is a connection diagram showing a conventional device, in which 7 is a piezoelectric element, 8 is a control signal, 50 is a PWM signal, and 65 and 66 are drivers respectively. The drivers 65 and 66 are drivers whose output terminals take three kinds of states. When the logic of the control signal 8 is "1", the output point becomes high impedance, and when the logic of the control signal 8 is "0". The voltage at the output point has the same logic (driver 65) or the opposite logic (driver 66) as the voltage logic at the input point. Therefore, when driving the piezoelectric element, the logic of the control signal 8 becomes "0", and the polarity of the both ends of the piezoelectric element is changed by the logic of the PWM signal 50. That is, when the logic of the PWM signal 50 is “1”, the positive voltage + E is applied from the driver 65 to one electrode of the piezoelectric element 7 and the GND potential is applied to the other terminal by the driver 66.
When the logic of the PWM signal 50 is "0", the GND potential is given from the driver 65 and the potential + E is applied from the driver 66. In this way, the logic of the PWM signal 50 changes the polarities at both ends of the piezoelectric element, so that the piezoelectric element is driven by the voltage of the absolute value 2E due to charge accumulation in the capacitive component included in the impedance of the piezoelectric element.

Further, when the voltage to the piezoelectric element 7 is cut off, the logic of the control signal 8 becomes "1", and the output elements of the drivers 65 and 66 are both set to high impedance regardless of the logic of the PWM signal signal 50, Shut off.

FIG. 4 is an operation time chart comparing the operation of the device of the present invention with the operation of the conventional device. FIG. 4 (a) shows the original analog signal A0 and the corresponding digital signal D0,
The same figure (b) shows the 0 level of A0 and a sampling point, and the same figure (c) shows the PWM signal P0 which converted the digital signal D0. 4 (d) and (e) will be described later.
P0 is applied to one electrode of the piezoelectric element 7 in FIG. 3, and the opposite waveform of P0 is applied to the other electrode.

[Problems to be Solved by the Invention] In the conventional device, there is a potential difference between both ends of the piezoelectric element 7 regardless of the logic value of the PWM signal 50. There is a problem that the piezoelectric element 7 generates a click sound depending on the transient state when the state is set. In particular, when the piezoelectric element 7 is driven from the high impedance state, this problem becomes remarkable.

The present invention aims to prevent the generation of such a click sound.

[Means for Solving the Problem] In this invention, when the output of the driver transits to the high impedance state or when transiting from the high impedance state to the driving state, control is performed so that no potential difference is generated across the piezoelectric element. did.

[Operation] The same voltage is connected to both electrodes of the piezoelectric element while the PWM signal is logic "0". For that purpose, the digital signal is divided into a polarity signal and an absolute value signal, and when the polarity signal is logic "1", a signal voltage is applied to one electrode of the piezoelectric element and to the other electrode when the logic signal is logic "0".

[Embodiment] FIG. 1 is a block diagram showing an embodiment of the present invention.
In the figure, 1 is a digital signal circuit, 2 is an absolute value signal,
Reference numeral 3 is a polarity signal, 4 is a D / A converter, 5 is a PWM signal, 6 is a piezo drive unit, and 7 and 8 are the same or corresponding parts with the same reference numerals in FIG.

FIG. 2 is a connection diagram showing the connection of the piezo drive unit of FIG.
In the figure, the same reference numerals as those in FIG. 1 denote the same parts, 60 is an inverter, 61 is a first gate, 62 is a second gate, 63 is a first driver, and 64 is a second driver. Further, FIG. 4 (d) shows a digital value D1 representing D0 of FIG. 4 (a) with ZE as a reference, and a polarity signal 3 indicating positive / negative of D1 as S1.
Indicate. Figure 4 (e) is the P obtained by D / A conversion of the absolute value of D1.
The WM signal 5 is indicated by P1. ZE is generally selected as the average value of D0, but other appropriate value may be used.

The input (not shown) of the digital signal circuit 1 may be an analog signal or another form of digital signal, but the output is the absolute value signal 2 representing the absolute value of D1 and the logic of S1. It operates so that the polarity signal 3 is represented. The D / A converter 4 has a pulse width proportional to the absolute value signal 2 and the absolute value.
Convert to PWM signal 5 (P1 in Fig. 4 (e)).

The control signal 8 is constantly applied to the drivers 63, 6 while the piezoelectric element 7 is operating.
4, the driver 63 outputs the voltage of the logic obtained by inverting the logic of the output of the gate 61, and the driver 64 outputs the voltage of the logic obtained by inverting the output logic of the gate 62.

The driver 6 so that the output voltage of the logic "1" of the drivers 63 and 64 becomes + E and the output voltage of the logic "0" becomes 0.
When the power supply voltage of 3,64 is determined, P1 is set while S1 is logic "1".
Is a logic "1", a voltage of + E is applied from the driver 63 to the driver 64. When P1 is a logic "0", the voltage between both terminals of the piezoelectric element 7 is 0, and S1 is a logic "0". When P1 is logic "1", a voltage of + E is applied from the driver 64 to the driver 63, and when P1 becomes logic "0", the voltage between both terminals of the piezoelectric element 7 becomes zero. In this state, even if the outputs of the drivers 63 and 64 are set to a high impedance state or the high impedance state is driven, a potential difference does not occur across the piezoelectric element 7. Therefore, the device of the present invention does not generate a click sound.

“Effect of Device” As described above, according to this device, the click sound can be easily erased and a special muting circuit is not required.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a connection diagram showing the connection of the piezo drive unit of FIG. 1, FIG. 3 is a connection diagram showing a conventional device, and FIG. Operation time chart comparing the operation of the device of the invention with the operation of the conventional device. 1 ... Digital signal circuit, 2 ... Absolute value signal, 3 ...
Polarity signal, 4 ... D / A converter, 5 ... PWM signal, 6 ... Piezo driver, 60 ... Inverter, 61 ... First gate,
62 …… second gate, 63 …… first driver, 64 ……
Second driver, 7 ... Piezoelectric element. The same reference numerals in the drawings indicate the same or corresponding parts.

Claims (1)

[Scope of utility model registration request] 1. A piezoelectric element driving apparatus for driving a piezoelectric element having a pair of electrodes for applying a signal voltage based on a digital signal, wherein the digital signal applied to the piezoelectric element represents the polarity of the signal. Digital signal circuit that outputs the polarity signal and the absolute value signal that represents the absolute value separately. D / A (digital analog) conversion that converts the absolute value signal of the output of this digital signal circuit to a PWM signal (pulse width modulation signal) Device, an inverter that inverts the logic of the polarity signal, a first gate circuit that outputs a logical product of the polarity signal and the PWM signal, a second gate circuit that outputs a logical product of the output of the inverter and the PWM signal , Is driven by the output of the first gate circuit, outputs the first voltage while the logical product of the PWM signal and the polarity signal is logic "1", and outputs the first voltage during other times. Had the second
Is driven by the output of the second gate circuit, and the logical product of the PWM signal and the output of the inverter is logic "1",
A second driver that outputs the first voltage and outputs the second voltage during the other period, and means for connecting the outputs of the first and second drivers to a pair of terminals of the piezoelectric element, respectively. A drive device for a piezoelectric element, comprising: