JPH07288981A - Constant voltage system - Google Patents
Constant voltage systemInfo
- Publication number
- JPH07288981A JPH07288981A JP6075212A JP7521294A JPH07288981A JP H07288981 A JPH07288981 A JP H07288981A JP 6075212 A JP6075212 A JP 6075212A JP 7521294 A JP7521294 A JP 7521294A JP H07288981 A JPH07288981 A JP H07288981A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- fet
- terminals
- load
- charging capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- Dc-Dc Converters (AREA)
- Power Conversion In General (AREA)
- Direct Current Feeding And Distribution (AREA)
- Rectifiers (AREA)
- Control Of Electrical Variables (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は広く電子装置の電源とし
て用いられる定電圧装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to a constant voltage device used as a power source for electronic devices.
【０００２】[0002]
【従来の技術】図３は従来の定電圧装置の一例を示す回
路図である。図３において、交流電源１にその交流入力
端子Ｕ，Ｖが接続される、例えば全波整流ブリッジの整
流回路２と、そのコレクタがこの整流回路２の正側直流
出力端子Ｐに、そのエミッタが充電コンデンサ６を介し
てこの負側直流出力端子Ｎに接続されたスイッチング素
子としてのトランジスタ８Ａと、このトランジスタ８Ａ
を開閉制御する制御回路３とからなり、負荷７は充電コ
ンデンサ６の両端子間に接続される。前記制御回路３
は、そのカソードが整流回路２の負側直流出力端子Ｎ
に、そのアノードがベース抵抗３３を介しこの正側直流
出力端子Ｐに接続されたサイリスタ３２と、そのカソー
ドがトランジスタ８Ａのエミッタに、そのアノードが抵
抗３４を介しサイリスタ３２のカソードに接続されたツ
ェナーダイオード３１とから構成され、サイリスタ３２
のアノードはトランジスタ８Ａのベースに、ツェナーダ
イオード３１のアノードはサイリスタ３２のゲートにそ
れぞれ接続される。2. Description of the Related Art FIG. 3 is a circuit diagram showing an example of a conventional constant voltage device. In FIG. 3, an AC power supply 1 is connected to its AC input terminals U and V, for example, a rectifier circuit 2 of a full-wave rectifier bridge, its collector is a positive side DC output terminal P of this rectifier circuit 2, and its emitter is A transistor 8A as a switching element connected to the negative side DC output terminal N via the charging capacitor 6 and the transistor 8A.
The load 7 is connected between both terminals of the charging capacitor 6. The control circuit 3
Is the negative side DC output terminal N of the rectifier circuit 2.
A thyristor 32 whose anode is connected to the positive side DC output terminal P via a base resistor 33, its cathode connected to the emitter of the transistor 8A, and its anode connected to the cathode of the thyristor 32 via a resistor 34. It is composed of a diode 31 and a thyristor 32.
Is connected to the base of the transistor 8A, and the anode of the Zener diode 31 is connected to the gate of the thyristor 32.
【０００３】この定電圧装置の動作を図４に示す波形図
を参照して説明する。図４は整流回路２の出力電圧，負
荷７の電圧およびトランジスタ８Ａの電流をそれぞれ示
し、負荷７の電圧はツェナーダイオード３１に印加さ
れ、この電圧がツェナーダイオード３１の降伏電圧にな
るまではサイリスタ３２はオフ、従ってトランジスタ８
Ａはオンであり、整流回路２の出力電圧が上昇するにつ
れて充電コンデンサ６に充電が行われる。時刻ｔ2 にお
いて、負荷７の電圧がツェナーダイオード３１の降伏電
圧を越えるとサイリスタ３２のゲートに電流が流入し、
サイリスタ３２はオンする。サイリスタ３２がオンする
と、トランジスタ８Ａはそのエミッタとベースとの間が
充電コンデンサ６を介して短絡されオフする。トランジ
スタ８Ａがオフすると、充電コンデンサ６の端子間電圧
は負荷７の抵抗値と充電コンデンサ６の容量により定ま
る時定数で低下する。充電コンデンサ６の端子間電圧が
ツェナーダイオード３１の降伏電圧以下になるとサイリ
スタ３２のゲート電流は遮断され、サイリスタ３２は整
流回路２の出力電圧が電源電圧の半周期で零になる時点
でオフする。サイリスタ３２がオフすると、ベース抵抗
３３を通してベース電流がトランジスタ８Ａに流入しト
ランジスタ８Ａはオンとなり、次の電源電圧の半波の時
刻ｔ5 において充電コンデンサ６に充電が行われる。こ
の充電によって、充電コンデンサ６の端子間電圧は上昇
しツェナーダイオード３１の降伏電圧を越えると、前述
と同様の動作が行われる。この動作は繰り返されて、充
電コンデンサ６の端子間電圧、すなわち負荷７の電圧は
一定に制御される。The operation of this constant voltage device will be described with reference to the waveform chart shown in FIG. FIG. 4 shows the output voltage of the rectifier circuit 2, the voltage of the load 7 and the current of the transistor 8A, respectively. The voltage of the load 7 is applied to the zener diode 31, and the thyristor 32 is applied until this voltage becomes the breakdown voltage of the zener diode 31. Off, therefore transistor 8
A is on, and the charging capacitor 6 is charged as the output voltage of the rectifier circuit 2 rises. At time t 2 , when the voltage of the load 7 exceeds the breakdown voltage of the Zener diode 31, a current flows into the gate of the thyristor 32,
The thyristor 32 turns on. When the thyristor 32 is turned on, the transistor 8A is turned off because its emitter and base are short-circuited via the charging capacitor 6. When the transistor 8A is turned off, the voltage across the terminals of the charging capacitor 6 decreases with a time constant determined by the resistance value of the load 7 and the capacity of the charging capacitor 6. When the voltage between the terminals of the charging capacitor 6 becomes equal to or lower than the breakdown voltage of the Zener diode 31, the gate current of the thyristor 32 is cut off, and the thyristor 32 is turned off when the output voltage of the rectifier circuit 2 becomes zero in a half cycle of the power supply voltage. When the thyristor 32 is turned off, the transistor 8A flows the base current to the transistor 8A through the base resistor 33 is turned on, charging is performed to the charging capacitor 6 at time t 5 of the half-wave of the next supply voltage. Due to this charging, when the voltage between the terminals of the charging capacitor 6 rises and exceeds the breakdown voltage of the Zener diode 31, the same operation as described above is performed. This operation is repeated, and the voltage between the terminals of the charging capacitor 6, that is, the voltage of the load 7 is controlled to be constant.
【０００４】次に電源電圧が変動して、例えば時刻ｔ6
以後に整流回路２の出力電圧が上昇したとすると、同様
に時刻ｔ7 〜ｔ8 の間ではトランジスタ８Ａはオンであ
り、充電コンデンサ６に充電が行われ、負荷７の電圧が
ツェナーダイオード３１の降伏電圧を越えるとトランジ
スタ８Ａがオフになる。この場合も充電コンデンサ６に
充電される時間が変化するだけで、負荷７の電圧は一定
に制御される。Next, the power supply voltage fluctuates, and, for example, at time t 6
If subsequently the output voltage of the rectifier circuit 2 is a rose, between times t 7 ~t 8 similarly transistor 8A is turned on, charging is performed to the charging capacitor 6, the voltage of the load 7 of the Zener diode 31 When the breakdown voltage is exceeded, the transistor 8A turns off. Also in this case, the voltage of the load 7 is controlled to be constant only by changing the time for charging the charging capacitor 6.
【０００５】[0005]
【発明が解決しようとする課題】前述の定電圧装置にお
いては、整流回路の出力電圧の立ち上がり時に、充電コ
ンデンサの端子間電圧、すなわち負荷の電圧がツェナー
ダイオードの降伏電圧に達するように充電を行っている
ので、交流電源電圧の半波ごとにしかスイッチング素子
としてのトランジスタの開閉制御が行われず、負荷電圧
の脈動（図４でΔｖ1 で示す）が大きい問題がある。ま
た、給電中に負荷が事故などによって切り離されるよう
な場合、電源側のインダクタンスによってサージ電圧が
発生し、この定電圧装置の回路が損傷する問題がある。In the above-described constant voltage device, charging is performed so that the voltage across the terminals of the charging capacitor, that is, the load voltage, reaches the breakdown voltage of the Zener diode when the output voltage of the rectifier circuit rises. Therefore, the switching control of the transistor as the switching element is performed only for each half-wave of the AC power supply voltage, and there is a problem that the pulsation of the load voltage (indicated by Δv 1 in FIG. 4) is large. In addition, when the load is disconnected during power supply due to an accident or the like, a surge voltage is generated due to the inductance on the power supply side, and there is a problem that the circuit of the constant voltage device is damaged.
【０００６】本発明の目的は負荷電圧の脈動を低減し、
更に給電中に負荷が事故などによって切り離されたとき
に生じるサージ電圧を低減することにある。An object of the present invention is to reduce load voltage pulsations,
Another object is to reduce the surge voltage that occurs when the load is disconnected due to an accident during power supply.
【０００７】[0007]
【課題を解決するための手段】前述の目的を達成するた
めに、本発明の定電圧装置は交流電源にその交流入力端
子が接続される整流回路と、この整流回路の負側直流出
力端子にそのソースが接続され、そのドレインは負荷が
その両端子間に接続される充電コンデンサを介して、前
記整流回路の正側直流出力端子に接続されるスイッチン
グ素子としてのＦＥＴと、このＦＥＴのゲートとドレイ
ンとの間に加えられるこのＦＥＴのゲート電流を制御し
て、前記充電コンデンサの端子間電圧を一定になるよう
にこのＦＥＴを開閉制御する制御回路とからなるように
する。この制御回路は、例えば充電コンデンサの端子間
電圧の分電圧が印加される電圧検出器を備え、この分電
圧が前記電圧検出器の設定値を越えたときはＦＥＴをオ
フし、この分電圧が前記電圧検出器の設定値以下のとき
はＦＥＴをオンするようにこのＦＥＴを開閉制御するよ
うにする。更に、この整流回路の正側および負側直流出
力端子の間にサージアブソーバを接続する。In order to achieve the above-mentioned object, the constant voltage device of the present invention comprises a rectifier circuit whose AC input terminal is connected to an AC power source and a negative side DC output terminal of this rectifier circuit. Its source is connected, and its drain is connected to the positive side DC output terminal of the rectifier circuit as a switching element through a charging capacitor whose load is connected between both terminals thereof, and a gate of this FET. The gate current of the FET applied between the drain and the drain is controlled to control the opening and closing of the FET so that the voltage across the terminals of the charging capacitor becomes constant. This control circuit includes, for example, a voltage detector to which a voltage corresponding to the voltage between the terminals of the charging capacitor is applied. When the voltage exceeds the set value of the voltage detector, the FET is turned off, and this voltage is When the voltage is below the set value of the voltage detector, the FET is controlled to open and close so as to be turned on. Further, a surge absorber is connected between the positive side and negative side DC output terminals of this rectifier circuit.
【０００８】[0008]
【作用】本発明の定電圧装置は、例えば充電コンデンサ
の端子間電圧の分電圧が印加される電圧検出器を備え、
この分電圧が前記電圧検出器の設定値を越えたときはＦ
ＥＴをオフし、この分電圧が前記電圧検出器の設定値以
下のときはＦＥＴをオンするようにこのＦＥＴを開閉制
御する制御回路によって、負荷電圧の分電圧がこの電圧
検出器の設定値になるように、スイッチング素子として
のＦＥＴを開閉制御するようにしたので、交流電源電圧
の半波ごとにこのＦＥＴの開閉制御を行う従来の定電圧
装置に比して負荷電圧の脈動が低減される。更に、サー
ジアブソーバを設けたので、給電中に負荷が事故などに
よって切り離され、負荷電流が急変したとき、電源側の
インダクタンスなどによって生じるサージ電圧は、サー
ジアブソーバのダイオードを介してコンデンサに加えら
れて、このコンデンサに吸収されるので低減する。The constant voltage device of the present invention is provided with a voltage detector to which a voltage equivalent to the voltage between the terminals of the charging capacitor is applied,
When the voltage exceeds the set value of the voltage detector by this amount, F
ET is turned off, and the control circuit that controls the opening and closing of this FET so that the FET is turned on when the corresponding voltage is below the set value of the voltage detector causes the divided voltage of the load voltage to reach the set value of this voltage detector. Since the FET as the switching element is controlled to be opened and closed as described above, the pulsation of the load voltage is reduced as compared with the conventional constant voltage device that controls the opening and closing of the FET for each half-wave of the AC power supply voltage. . Furthermore, since a surge absorber is provided, when the load is disconnected due to an accident during power supply and the load current suddenly changes, the surge voltage caused by the inductance on the power supply side is applied to the capacitor via the diode of the surge absorber. , It is absorbed by this capacitor, so it is reduced.
【０００９】[0009]
【実施例】図１は本発明の定電圧装置の一実施例を示す
回路図である。図１において、交流電源１にその交流入
力端子Ｕ，Ｖが接続される、例えば全波整流ブリッジの
整流回路２と、そのドレインが充電コンデンサ６を介し
てこの整流回路２の正側出力端子Ｐに、そのソースがこ
の負側出力端子Ｎに接続されたスイッチング素子として
のＦＥＴ８Ｂと、このＦＥＴ８Ｂを開閉制御する制御回
路４とからなり、負荷７は前記充電コンデンサ６の両端
子間に接続される。1 is a circuit diagram showing an embodiment of a constant voltage device according to the present invention. In FIG. 1, an AC power supply 1 is connected to its AC input terminals U and V, for example, a rectifying circuit 2 of a full-wave rectifying bridge, and its drain via a charging capacitor 6 a positive output terminal P of this rectifying circuit 2. In addition, the source thereof is composed of a FET 8B as a switching element connected to the negative output terminal N and a control circuit 4 for controlling the opening / closing of the FET 8B, and a load 7 is connected between both terminals of the charging capacitor 6. .
【００１０】更に、整流回路２の正側および負側出力端
子Ｐ，Ｎ間にサージアブソーバ９が接続されている。前
記制御回路４は、そのエミッタが整流回路２の正側出力
端子Ｐに、そのコレクタが直列に接続された抵抗４９お
よび５０を介しこの負側出力端子Ｎに接続されたトラン
ジスタ４８と、このトランジスタ４８のエミッタとベー
スの間に接続された抵抗４７と、整流回路２の正側およ
び負側出力端子Ｐ，Ｎ間に直列に接続された抵抗４２，
４３および４４と、その端子ＯＵＴが抵抗４６を介しト
ランジスタ４８のベースに、その端子ＶDD が抵抗４２
と４３の接続点に、その端子ＶSSが抵抗４３と４４の接
続点にそれぞれ接続され、負荷７の分圧電圧が入力され
る電圧検出器４５と、抵抗５０と逆極性並列に接続され
た電圧制限用のツェナーダイオード５１と、そのアノー
ドが抵抗４３と４４の接続点に接続されたダイオード４
１とからなり、このダイオード４１のカソードは充電コ
ンデンサ６とＦＥＴ８Ｂの接続点に、ツェナーダイオー
ド５１のカソードはＦＥＴ８Ｂのゲートにそれぞれ接続
される。なお、ダイオード４１は電圧検出器の端子ＶDD
とＶSS間に逆電圧の印加を防ぐためのものである。Further, a surge absorber 9 is connected between the positive and negative output terminals P and N of the rectifier circuit 2. The control circuit 4 has a transistor 48 whose emitter is connected to the positive output terminal P of the rectifier circuit 2 and whose collector is connected to this negative output terminal N via resistors 49 and 50 connected in series, and this transistor. A resistor 47 connected between the emitter and the base of 48 and a resistor 42 connected in series between the positive and negative output terminals P and N of the rectifier circuit 2.
43 and 44, the terminal OUT of which is connected to the base of the transistor 48 via the resistor 46, and the terminal V DD of which is connected to the resistor 42.
And the terminal V SS is connected to the connection point of the resistors 43 and 44, respectively, and the voltage detector 45 to which the divided voltage of the load 7 is input and the resistance 50 are connected in parallel with the reverse polarity. Zener diode 51 for voltage limitation and diode 4 whose anode is connected to the connection point of resistors 43 and 44
The cathode of the diode 41 is connected to the connection point between the charging capacitor 6 and the FET 8B, and the cathode of the Zener diode 51 is connected to the gate of the FET 8B. The diode 41 is connected to the terminal V DD of the voltage detector.
This is for preventing the application of a reverse voltage between V SS and V SS .
【００１１】前記電圧検出器４５は、例えばセイコー電
子工業株式会社製高精度電圧検出器ＳＯＴ−８９−３で
あり、端子ＶDDとＶSS間の電圧が設定値以上に上昇する
と端子ＯＵＴとＶSS間が導通し、設定値以下に低下する
と端子ＯＵＴとＶSS間が不導通となる。なお、通常、こ
の端子ＶDDとＶSS間の電圧が上昇するときと低下すると
きの設定値の間にはヒステリシスがある。The voltage detector 45 is, for example, a high-precision voltage detector SOT-89-3 manufactured by Seiko Instruments Inc., and when the voltage between the terminals V DD and V SS rises above a set value, the terminals OUT and V When SS is conductive and when the voltage is lower than the set value, the terminal OUT and V SS become non-conductive. Incidentally, there is usually hysteresis between the set values when the voltage between the terminals V DD and V SS rises and falls.
【００１２】また、前記サージアブソーバ９はそのアノ
ードが整流回路２の正側直流出力端子Ｐに、そのカソー
ドがコンデンサ９２を介しこの負側直流出力端子Ｎに接
続されたダイオード９１と、このダイオード９１のアノ
ードとカソードの間に接続された抵抗９３とからなって
いる。この定電圧装置の動作を図２に示す波形図を参照
して説明する。図２は整流回路２の出力電圧，負荷７の
電圧およびＦＥＴ８Ｂの電流をそれぞれ示し、負荷７の
電圧は抵抗４２と４３で分圧されて、この分圧電圧が電
圧検出器４５の端子ＶDDとＶSS間に印加され、この分圧
電圧（但し図２では簡単なため、分圧電圧の分圧比は１
として描いてある）がこの電圧検出器４５の設定値にな
るまでは、この端子ＯＵＴとＶSS間は導通してトランジ
スタ４８はオン、このトランジスタ４８のオンによって
抵抗５０の両端子間に電圧が発生し、この電圧はＦＥＴ
８Ｂのゲートに入力されるのでＦＥＴ８Ｂはオンであ
り、整流回路２の出力電圧が上昇するにつれて充電コン
デンサ６に充電が行われる。時刻ｔ2 において、負荷７
の電圧の分圧電圧が電圧検出器４５の設定電圧を越える
と、電圧検出器４５の端子ＯＵＴとＶSSとの間が不導通
となってトランジスタ４８がオフして、抵抗５０の両端
子間電圧は消滅するのでＦＥＴ８Ｂはオフする。ＦＥＴ
８Ｂがオフすると、充電コンデンサ６の端子間電圧は負
荷７の抵抗値と充電コンデンサ６の容量により定まる時
定数で低下する。時刻ｔ3 において、充電コンデンサ６
の端子間電圧の分圧電圧が電圧検出器４５の設定電圧以
下になると、この端子ＯＵＴとＶSSとの間が導通となっ
てトランジスタ４８がオンして、ＦＥＴ８Ｂはオンとな
り充電コンデンサ６に充電が行われる。この充電によっ
て充電コンデンサ６の端子間電圧は上昇し、時刻ｔ4 で
この分圧電圧が電圧検出器４５の設定値を越えると、こ
の端子ＯＵＴとＶSSとの間が不導通となってトランジス
タ４８がオフしてＦＥＴ８Ｂはオフとなり、充電コンデ
ンサ６の端子間電圧は負荷７の抵抗値と充電コンデンサ
６の容量により定まる時定数で低下する。時刻ｔ5 にお
いて、充電コンデンサ６の端子間電圧の分圧電圧が電圧
検出器４５の設定値以下になると、この端子ＯＵＴとＶ
SSとの間が導通となってトランジスタ４８がオンしてＦ
ＥＴ８Ｂがオンとなり、充電コンデンサ６の端子間電圧
は上昇し、この分圧電圧が電圧検出器４５の設定値を越
えると、前述と同様の動作が行われる。この動作は繰り
返されて充電コンデンサ６の端子間電圧、すなわち負荷
７の電圧は一定に制御される。The surge absorber 9 has a diode 91 whose anode is connected to the positive side DC output terminal P of the rectifier circuit 2 and whose cathode is connected to this negative side DC output terminal N via a capacitor 92, and this diode 91. And a resistor 93 connected between the anode and the cathode. The operation of the constant voltage device will be described with reference to the waveform chart shown in FIG. FIG. 2 shows the output voltage of the rectifier circuit 2, the voltage of the load 7 and the current of the FET 8B, respectively. The voltage of the load 7 is divided by the resistors 42 and 43, and the divided voltage is the terminal V DD of the voltage detector 45. Is applied between V SS and V SS , and this divided voltage (However, since it is simple in FIG. 2, the divided voltage has a division ratio of 1
Until it reaches the set value of the voltage detector 45, the terminal OUT and V SS are conductive and the transistor 48 is turned on. By turning on the transistor 48, the voltage between both terminals of the resistor 50 is turned on. Generated, this voltage is FET
Since it is input to the gate of 8B, the FET 8B is on, and the charging capacitor 6 is charged as the output voltage of the rectifier circuit 2 rises. At time t 2 , load 7
When the divided voltage of the voltage exceeds the set voltage of the voltage detector 45, the terminal OUT of the voltage detector 45 and V SS become non-conductive, the transistor 48 is turned off, and both terminals of the resistor 50 are turned off. Since the voltage disappears, the FET 8B turns off. FET
When 8B is turned off, the voltage across the terminals of the charging capacitor 6 decreases with a time constant determined by the resistance value of the load 7 and the capacity of the charging capacitor 6. At time t 3 , the charging capacitor 6
When the divided voltage of the voltage between the terminals becomes less than the set voltage of the voltage detector 45, the terminal OUT and V SS become conductive, the transistor 48 is turned on, the FET 8B is turned on, and the charging capacitor 6 is charged. Is done. Due to this charging, the voltage between the terminals of the charging capacitor 6 rises, and when this divided voltage exceeds the set value of the voltage detector 45 at time t 4 , there is no conduction between this terminal OUT and V SS and the transistor 48 is turned off, the FET 8B is turned off, and the voltage across the terminals of the charging capacitor 6 decreases with a time constant determined by the resistance value of the load 7 and the capacity of the charging capacitor 6. At time t 5 , when the divided voltage of the voltage between the terminals of the charging capacitor 6 becomes equal to or lower than the set value of the voltage detector 45, the terminals OUT and V
Conduction between SS and transistor 48 turns on and F
ET8B is turned on, the voltage across the terminals of the charging capacitor 6 rises, and when this divided voltage exceeds the set value of the voltage detector 45, the same operation as described above is performed. This operation is repeated and the voltage across the terminals of the charging capacitor 6, that is, the voltage of the load 7 is controlled to be constant.
【００１３】次に電源電圧が変動して、例えば時刻ｔ6
以後に整流回路２の出力電圧が上昇したとすると、同様
に時刻ｔ7 〜ｔ8 およびｔ9 〜ｔ10の間ではＦＥＴ８Ｂ
はオンであり、充電コンデンサ６に充電が行われ、負荷
７の電圧の分圧電圧が電圧検出器４５の設定値を越える
とＦＥＴ８Ｂがオフになる。この場合も充電コンデンサ
６に充電される時間が変化するだけで、負荷７の電圧は
一定に制御される。Next, the power supply voltage fluctuates and, for example, at time t 6
Assuming that the output voltage of the rectifier circuit 2 subsequently rises, the FET 8B is likewise between the times t 7 and t 8 and t 9 and t 10.
Is on, the charging capacitor 6 is charged, and when the divided voltage of the voltage of the load 7 exceeds the set value of the voltage detector 45, the FET 8B is turned off. Also in this case, the voltage of the load 7 is controlled to be constant only by changing the time for charging the charging capacitor 6.
【００１４】なお、前述の動作でＦＥＴ８Ｂがオンした
とき、整流回路２の出力電圧が充電コンデンサ６の両端
子間電圧より低いときは、この時点では充電コンデンサ
６の充電が行われず、整流回路２の出力電圧が上昇して
この充電コンデンサ６の両端子間電圧を越えた時点で、
充電コンデンサ６の充電が行われる。また、抵抗４４は
始動用抵抗で電圧検出器４５の端子ＶSSを抵抗接地し、
この定電圧装置の始動時、交流電源１を投入したとき
に、この電圧検出器４５の端子ＶDDとＶSS間に電圧が印
加されるようにして、ＦＥＴ８Ｂをオンさせて充電コン
デンサの充電が開始されるようにするためのものであ
る。When the FET 8B is turned on in the above operation and the output voltage of the rectifying circuit 2 is lower than the voltage between both terminals of the charging capacitor 6, the charging capacitor 6 is not charged at this point and the rectifying circuit 2 is not charged. When the output voltage of rises and exceeds the voltage between both terminals of this charging capacitor 6,
The charging capacitor 6 is charged. The resistor 44 is a starting resistor for grounding the terminal V SS of the voltage detector 45 by resistance grounding,
When the AC power supply 1 is turned on at the time of starting the constant voltage device, a voltage is applied between the terminals V DD and V SS of the voltage detector 45 so that the FET 8B is turned on to charge the charging capacitor. It is meant to be started.
【００１５】なお、図２のΔｖ2 は電圧検出器４５の設
定値のヒステリシスに基づくリップルであり、通常、こ
のヒステリシスは大きなものではないので、このヒステ
リシスに基づく負荷７の脈動は小さい。このように本発
明の定電圧装置では、充電コンデンサ６の端子間電圧の
分圧電圧、すなわち負荷７の電圧の分圧電圧が電圧検出
器４５の設定値になるようにスイッチング素子としての
ＦＥＴ８Ｂを開閉制御しているので、交流電源電圧の半
波ごとにトランジスタの開閉制御を行う従来の定電圧装
置に比して、負荷電圧の脈動が低減される。It should be noted that Δv 2 in FIG. 2 is a ripple based on the hysteresis of the set value of the voltage detector 45, and normally this hysteresis is not large, so the pulsation of the load 7 based on this hysteresis is small. As described above, in the constant voltage device of the present invention, the FET 8B as a switching element is provided so that the divided voltage of the voltage between the terminals of the charging capacitor 6, that is, the divided voltage of the voltage of the load 7 becomes the set value of the voltage detector 45. Since the switching is controlled, the pulsation of the load voltage is reduced as compared with the conventional constant voltage device that controls the switching of the transistor for each half-wave of the AC power supply voltage.
【００１６】また、給電中に負荷７が事故などによって
急に切り離され負荷電流が急変したとき、電源側のイン
ダクタンスなどによってサージ電圧が発生するが、この
サージ電圧はサージアブソーバ９のダイオード９１を介
してコンデンサ９２に加えられて、このコンデンサ９２
に吸収されるので低減する。なお、９３はこのコンデン
サ９２の放電抵抗である。When the load 7 is suddenly disconnected during power supply due to an accident or the like, and the load current suddenly changes, a surge voltage is generated due to the inductance on the power source side. This surge voltage is transmitted through the diode 91 of the surge absorber 9. Is added to the capacitor 92,
It is absorbed by and is reduced. Incidentally, 93 is a discharge resistance of the capacitor 92.
【００１７】[0017]
【発明の効果】本発明の定電圧装置は交流電源を整流回
路で整流し、この整流出力で充電される充電コンデンサ
を開閉制御する簡単な回路で、かつ、負荷電圧の脈動が
小さいので、低コスト，高性能であり、電子回路などの
定電圧電源として実用的効果が大きい。The constant voltage device of the present invention is a simple circuit for rectifying an AC power supply by a rectifying circuit and controlling the opening and closing of the charging capacitor charged by this rectified output, and because the pulsation of the load voltage is small, it is low. It has high cost and high performance, and has great practical effects as a constant voltage power supply for electronic circuits.
【００１８】[0018]
【００１９】[0019]
【図１】本発明の定電圧装置の一実施例を示す回路図FIG. 1 is a circuit diagram showing an embodiment of a constant voltage device of the present invention.
【００２０】[0020]
【図２】図１に示す本発明の定電圧装置の動作波形図FIG. 2 is an operation waveform diagram of the constant voltage device of the present invention shown in FIG.
【００２１】[0021]
【図３】従来の定電圧装置の一例を示す回路図FIG. 3 is a circuit diagram showing an example of a conventional constant voltage device.
【００２２】[0022]
【図４】図３に示す従来の定電圧装置の動作波形図4 is an operation waveform diagram of the conventional constant voltage device shown in FIG.
【００２３】[0023]
１ 交流電源 ２ 整流回路 ４ 制御回路 ４５ 電圧検出器 ６ 充電コンデンサ ７ 負荷 ８Ｂ ＦＥＴ（スイッチング素子） ９ サージアブソーバ 1 AC power supply 2 Rectifier circuit 4 Control circuit 45 Voltage detector 6 Charging capacitor 7 Load 8B FET (switching element) 9 Surge absorber
Claims (3)
整流回路と、この整流回路の負側直流出力端子にそのソ
ースが接続され、そのドレインは、負荷がその両端子間
に接続される充電コンデンサを介して、前記整流回路の
正側直流出力端子に接続されるスイッチング素子として
のＦＥＴと、このＦＥＴのゲートとドレインとの間に加
えられるこのＦＥＴのゲート電流を制御して、前記充電
コンデンサの端子間電圧を一定になるようにこのＦＥＴ
を開閉制御する制御回路とからなることを特徴とする定
電圧装置。1. A rectifier circuit having an AC input terminal connected to an AC power source, a source connected to a negative side DC output terminal of the rectifier circuit, and a drain connected to a load between the terminals. The charging is performed by controlling the FET as a switching element connected to the positive side DC output terminal of the rectifier circuit via a charging capacitor and the gate current of the FET applied between the gate and the drain of the FET. This FET to keep the voltage between the terminals of the capacitor constant
A constant voltage device, comprising: a control circuit for controlling opening and closing.
御回路は充電コンデンサの端子間電圧の分圧電圧が印加
される電圧検出器を備え、この分圧電圧が前記電圧検出
器の設定値を越えたときはＦＥＴをオフし、この分圧電
圧が前記電圧検出器の設定値以下のときはＦＥＴをオン
するようにこのＦＥＴを開閉制御することを特徴とする
定電圧装置。2. The constant voltage device according to claim 1, wherein the control circuit includes a voltage detector to which a divided voltage of the voltage between the terminals of the charging capacitor is applied, and the divided voltage is set by the voltage detector. A constant voltage device characterized in that when the voltage exceeds the value, the FET is turned off, and when the divided voltage is less than or equal to the set value of the voltage detector, the FET is turned on and off.
おいて、整流回路の正側および負側直流出力端子の間に
サージアブソーバを接続したことを特徴とする定電圧装
置。3. The voltage regulator according to claim 1 or 2, wherein a surge absorber is connected between the positive side and negative side DC output terminals of the rectifier circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6075212A JPH07288981A (en) | 1994-04-14 | 1994-04-14 | Constant voltage system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6075212A JPH07288981A (en) | 1994-04-14 | 1994-04-14 | Constant voltage system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07288981A true JPH07288981A (en) | 1995-10-31 |
Family
ID=13569679
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6075212A Pending JPH07288981A (en) | 1994-04-14 | 1994-04-14 | Constant voltage system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07288981A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008500799A (en) * | 2004-05-24 | 2008-01-10 | ヨンチャン チョー | Low voltage control method using alternating current waveform and system for implementing the same |
| JP2008289353A (en) * | 2007-05-16 | 2008-11-27 | Felix Communication & Information | Ac/dc converter, and ac/dc conversion method using it |
| EP3046220A4 (en) * | 2013-09-13 | 2017-05-31 | LG Innotek Co., Ltd. | Charging control device, charging control method and wireless power receiving device equipped with same |
| CN111033991A (en) * | 2017-09-08 | 2020-04-17 | Wago管理有限责任公司 | Circuit and method for damping oscillations induced by a supply voltage in an input circuit of a DC transformer |
-
1994
- 1994-04-14 JP JP6075212A patent/JPH07288981A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008500799A (en) * | 2004-05-24 | 2008-01-10 | ヨンチャン チョー | Low voltage control method using alternating current waveform and system for implementing the same |
| JP2008289353A (en) * | 2007-05-16 | 2008-11-27 | Felix Communication & Information | Ac/dc converter, and ac/dc conversion method using it |
| EP3046220A4 (en) * | 2013-09-13 | 2017-05-31 | LG Innotek Co., Ltd. | Charging control device, charging control method and wireless power receiving device equipped with same |
| US10069343B2 (en) | 2013-09-13 | 2018-09-04 | Lg Innotek Co., Ltd. | Charging control device, charging control method and wireless power receiving device equipped with same |
| US10348135B2 (en) | 2013-09-13 | 2019-07-09 | Lg Innotek Co., Ltd. | Charging control device, charging control method and wireless power receiving device equipped with same |
| US10608475B2 (en) | 2013-09-13 | 2020-03-31 | Lg Innotek Co., Ltd. | Charging control device, charging control method and wireless power receiving device equipped with same |
| CN111033991A (en) * | 2017-09-08 | 2020-04-17 | Wago管理有限责任公司 | Circuit and method for damping oscillations induced by a supply voltage in an input circuit of a DC transformer |
| CN111033991B (en) * | 2017-09-08 | 2024-05-10 | Wago管理有限责任公司 | Circuit, system and method for damping oscillations |
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