JPH07288549A - Automatic gain control system - Google Patents

Abstract

PURPOSE:To provide an automatic gain control system of digital circuit configuration by which high speed and stable level locking is realized. CONSTITUTION:The AGC circuit 41 is provided with a VGA 11 whose gain is controlled variably by a control signal, an EQ 12, an ADC 13, a (1+D) processing circuit 14 implementing limit of a band of a quantization output for PR 4 processing, a VGA controller circuit 25 detecting ah error of a signal 104 after (1+D) processing from an object level and providing error data 117 and error data 118 delayed by one sampling clock respectively, two kinds of D/A converters 16a, 16b converting respectively the two kinds of the error data 117, 118 into respective analog data, an analog adder 26 summing the outputs of the D/A converters 16a, 16b, a multiplier 17 multiplying a prescribed multiple with an analog adder output 125, and an integration device 18 integrating an output signal of the multiplier 17 to produce a control signal 122 for the VGA.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic gain control system, and more particularly to an automatic gain control system for controlling an amplitude value of a reproduction signal from a disc-shaped recording medium to a set value.

[0002]

2. Description of the Related Art In a magnetic recording / reproducing apparatus for recording and reproducing signal information as a magnetic signal on a disk-shaped magnetic recording medium which rotates at a constant number of revolutions, a magnetic recording medium is recorded between a head and a medium at an inner peripheral position and an outer peripheral position. Since the relative linear velocity is different, the output reproduction signal level of the head fluctuates. Therefore, in such a magnetic recording / reproducing apparatus, the automatic gain control (AG
C: Automatic Gain Control)
The circuit suppresses fluctuations in the reproduced signal amplitude, and performs automatic gain control so that a signal with a constant amplitude is always output.

FIG. 10 is a block diagram of a reproduction signal processing circuit of the above-mentioned general magnetic recording / reproducing apparatus. As shown in the figure, the reproduction signal processing circuit includes a magnetic head 2 for reproducing an electric signal 101 from a magnetic signal on a disk-shaped magnetic recording medium 1 in which signal information is recorded as a magnetic signal, and a reproduced electric signal. A preamplifier 3 for amplifying the signal 101, an AGC circuit 4 for always controlling and outputting the signal 102 amplified by the preamplifier 3 to a constant amplitude, and decoding of data from a reproduction signal 104 controlled to a constant amplitude by the AGC circuit 4. A timing extraction circuit 5 for extracting a sample clock 103 for performing the decoding, a decoding circuit 6 for receiving the reproduced signal 104 and the sample clock 103 to decode the data, and outputting decoded data 105 and a timing clock 106, and a reproduced signal. Sector pulse detection times when 104 is input to detect the beginning of a sector described later and outputs a sector pulse. 7, the decoded data 105 and the timing clock are input to format-convert the data, transfer the format-converted data to a host computer (not shown), and extract the timing based on the sector pulse from the sector pulse detection circuit 7. Control timing signal (read gate) for the circuit 5 and the AGC circuit 4
It has a controller 8 for outputting 201 and a computer for controlling the entire circuit, specifically, a microcomputer 8.

By the way, in such a magnetic recording / reproducing apparatus, generally, information is recorded in a spiral or concentric manner on the magnetic recording medium 1 which rotates at a high speed with respect to the magnetic head 2, and the head is operated during recording / reproducing. A track on which information is passed and recorded is called a track. The recorded information on this track has an appropriate size (for example, 1024 bytes,
It is divided into 512 bytes), and one set of the recorded information is called a sector.

FIG. 11 shows one format of this sector. Each sector is a GAP 61, which is an area arranged between the respective sectors to compensate for the speed fluctuation,
ID63 in which the address number of the sector and the sector number are recorded, and a synchronization signal portion SYNC62, I for generating a timing clock necessary for reading the ID63.
GAP64, which is an area arranged between D63 and SYNC65 for compensating for the speed variation, DATA66, DATA66 which is an area in which actual user data is recorded.
It is composed of a SYNC 65 which is a synchronizing signal portion for generating a timing clock necessary for reading.

Here, ID63 and DATA66 are
Since each is the area in which the address information and the user data information are recorded, the data read from it is an arbitrary pattern. On the other hand, SYNC62 and S
The YNC 65 is formatted in a predetermined regular pattern so that the timing extraction circuit 5 can synchronize based on the pattern. Also, GAP6
The same pattern as that of SYNC62 and SYNC65 is recorded in 1 and GAP64. In order to accurately decode the reproduced signal, the output signal amplitude of the AGC circuit 4 needs to be adjusted to an appropriate value in both the ID 63 and DATA 66 regions. For that purpose, SYNC62, SYN
It is necessary to adjust the output signal of the AGC circuit 4 to an appropriate value by using the reproduction signal in the area of C65 (hereinafter referred to as amplitude pull-in). Details of the signal patterns of SYNC62 and SYNC65, and A using the signal pattern
The amplitude pull-in operation of the GC circuit 4 will be described later.

Here, when a decoding circuit which inputs a digital value such as Viterbi is used as the decoding circuit 6 of FIG.
A configuration is conceivable in which the AGC circuit 4 and the timing extraction circuit 5 have a digital circuit configuration and are controlled in synchronization with the timing clock 103. FIG. 12 shows the configuration of a conventional example of the digital control type (analog input type) AGC circuit.
In this prior art example, a partial response (PRML: Partial Response) based on maximum likelihood decoding detection is used.
This is a reproduction signal processing circuit using the Maximum Likelihood. As a known example of PRML timing extraction, there is a technique described in Japanese Patent Laid-Open No. 1-143447. Further, as a publicly known example of the digital control type AGC circuit, Japanese Patent Laid-Open No. 61-1
There is a technique described in Japanese Patent Publication No. 29913.

As shown in FIG. 12, a conventional AGC circuit 4
Is a voltage-controlled variable gain amplifier (VGA) that controls the amplification gain by the control signal 122 when the read gate 201 is at the high level and holds the gain when the read gate 201 is at the low level.
Gain Amplifier) 11, an equalizer (hereinafter referred to as EQ) 12 for equalizing the waveform of the output 111 of the VGA 11, and an AD for quantizing the output 112 after equalization.
A converter (hereinafter referred to as ADC) 13 and a PR4 (P
an [1 + D] processing circuit 14 that limits the band of the quantized output for the artificial response class 4) processing, and a VGA controller 15 that detects an error from the target amplitude from the signal 104 after the [1 + D] processing and generates an error signal 119. , A DA converter (hereinafter referred to as DAC) 16 for converting the error signal 119 into an analog value, and a DA
It is composed of a multiplier 17 that multiplies the output analog signal 120 of C16 by a predetermined constant, and an integrator 18 that integrates the output signal 121 of the multiplier 17 to generate a control signal 122 of the VGA 11.

Further, V which generates an error signal 119 by detecting an error from the target amplitude from the signal 104 after [1 + D] processing
The GA controller 15 outputs the signal 10 after [1 + D] processing.
Discriminator 1 for determining the level of 4 and generating the determination signal 114
9, a multiplier 20 that multiplies the value of the input signal 104 and the value of the determination signal 114, and a multiplexer that selects and outputs "A" or "0" as the target amplitude value based on the value of the determination signal 114 Circuit (hereinafter referred to as MPX) 21, multiplier 2
A subtracter 22 and a subtracter 2 that subtract the value of the output 116 of the MPX 21 from the value of the output 115 of 0 to generate an error signal 117.
The delay unit 23 that delays the value of the second output 117 by one clock by the control clock 103, and the adder 24 that adds the value of the output 118 of the delay unit 23 and the value of the error signal 117 to generate the error signal 119. Have.

The amplitude pull-in operation of the conventional AGC circuit 4 having the above configuration will be described with reference to the timing chart of FIG. However, FIG. 13 shows the operation for the reproduction signal in the area of the SYNC 62, 65 in which the synchronization signal of the regular pattern is recorded. The sample clock 103 generated at the timing synchronized with the AGC output signal 104 by the timing extraction circuit 5 in FIG. 10 is a square wave with a constant period as shown in FIG.
+ D] is supplied to the processing circuit 14 and the delay device 23, respectively.

The output signal 102 of the preamplifier 3 shown in FIG. 13B is amplified by the VGA 11 with a gain according to the voltage level of the control signal 122 shown in FIG. 12 and becomes a signal 111 shown in FIG. 13C. , EQ12 through ADC13
To be analog-to-digital converted. ADC
13, the EQ output signal 112 is sampled by the sample clock 103 and fetched as a digital value.
The signal 113 shown in (D) is output. Here, SYN
Since it is a reproduced signal in the area of C62 and C65, the ADC output signal 11 sampled by the sample clock 103
3 is {-A, 0, A, as shown in FIG.
The data string has a periodicity such as 0, −A, 0, A, 0.

The [1 + D] processing circuit 14 is disclosed in Japanese Patent Laid-Open No. 1-1.
As described in the upper right column of page 242 of Japanese Patent No. 43447, {-A, 0, A, 0,-for PR4 processing.
ADC output signal 1 which is a data string of A, 0, A, 0 ...}
13 is added with a signal obtained by delaying the ADC output signal 113 by one sample clock, and [1 + D] processing is performed, so that {-A, -A,
A data string 10 such as A, A, -A, -A, A, A ...}
4 is generated and output. This [1 + D] output data string 104
Is supplied to the discriminator 19, where it is judged whether the signal level is "-A", "0" or "A", and as a result, as shown in FIG. When the signal 104 is "-A", it is converted into "-1", when it is "0", it is converted into "0", and when it is "A", it is converted into "1" and output.

This discriminator output signal 114 is output to the multiplier 20.
13 where it is multiplied by the [1 + D] output signal 104 and, as shown in FIG.
4 is converted into an absolute value signal 115. Further, the discriminator output signal 114 is also supplied to the MPX 21, where it is converted into the signal 116 shown in FIG.
Is input as a target value of the output signal 115 of the multiplier 20. This MPX output signal 116 is the discriminator output signal 11
When the value of 4 is "-1" or "1", it is output as "A", and when the value of the discriminator output signal 114 is "0", it is output as "0".

The subtractor 22 subtracts the multiplier output signal 115 from the MPX output signal 116 which is its target value,
The difference signal 117 shown in 3 (I) is output. Difference signal 1
Reference numeral 17 is branched into two, one of which is delayed by one sample clock by the delay unit 23 and then supplied to the adder 24, and the other of which is supplied to the adder 24 without being delayed and added, and FIG. Signal 119.

This adder output signal 119 is sent to the DAC 16
13 is converted into an analog signal 120 shown in FIG.
After being filtered by the control signal 122, the gain of the VGA 11 is controlled. VGA 11 at this time
Is controlled by feedback so that the value of the subtractor output signal 117 becomes zero, and the [1 + D] output signal 10
The amplitude level of 4 is controlled to "A". As a result, AD
The amplitude level of the C output signal 113 converges to "A".

[0016]

However, in the above-mentioned conventional AGC system, as shown in FIG.
Is a [1 + D] processing circuit 14, a discriminator 19, a multiplier 2
0, subtractor 22, MPX 21, delay device 23, adder 24
It has a digital circuit part of. So, in particular,
This is remarkable when the number of bits of the signal data is large, but the processing time of the multiplier 20 and the adder 24 becomes long. The problem when the extension of the processing time of the digital circuit portion (delay circuit delay) becomes large will be described with reference to FIG.

FIG. 14 shows a feedback control system A.
6 is a graph showing an open-loop phase characteristic of the GC circuit 4, in which the horizontal axis represents frequency and the vertical axis represents VGA input signal 1
2 shows the phase delay of the output control signal 122 of the integrator 18 with respect to 02. In the figure, as shown in (A), the integrator 18 has an integration characteristic, so that a phase delay of 90 degrees occurs, and further, as shown in (B), a phase delay occurs due to a digital circuit delay. Since the phase delay due to the digital circuit delay shown in (B) is a constant time, when a delay of a constant time that does not depend on the operating frequency occurs, the delay time corresponds to a larger phase delay as the operating frequency increases. Therefore, a large phase delay occurs as the frequency increases.

Therefore, in the conventional system, when it is attempted to secure the band of the feedback control system up to a high frequency indicated by f1 in FIG. 14, the phase delay becomes large and the phase margin cannot be sufficiently secured, so that the feedback control is performed. The problem arises that the stability of the system deteriorates. Also,
In the conventional method, the bandwidth of the feedback control system is, for example, as shown in
When the frequency is limited to the low frequency indicated by f2 in 4 above, the phase margin can be sufficiently secured to increase the stability of the system, but on the other hand, there is a problem that the amplitude pull-in becomes slow.

Therefore, the present invention has been made in consideration of the above points, and an object thereof is to provide an automatic gain control system of a digital circuit configuration for realizing a high-speed and stable amplitude pull-in operation.

[0020]

In order to achieve the above object, the present invention provides a variable gain amplifier for amplifying and outputting an input signal with a gain designated by an analog control signal, and an output signal of the variable gain amplifier. An analog control signal is generated and output to the variable gain amplifier so that the output signal of the variable gain amplifier has a predetermined amplitude according to the output value of the AD conversion means and the AD conversion means that performs sampling at a predetermined interval. In the automatic gain control method including a control signal generating section, the control signal generating section includes an error data generating circuit that generates a plurality of error data based on the output value of the AD conversion means, and the plurality of error data respectively. A DA converting means for converting into an analog signal and the plurality of analog error signals are added respectively, and the added signal is converted into a variable gain amplifier. It is obtained by a structure having an adding means for outputting as a control signal.

Further, the error data generating circuit includes a processing circuit for limiting the band of the output value of the AD conversion means for the partial response type processing, a discriminator for discriminating the output value of the processing circuit, and a discriminator for the discriminator. A multiplier that multiplies the output value and the output value of the AD conversion means, a switching means that outputs a target value of the output value of the multiplier based on the output value of the discriminator, an output value of the multiplier and an output of the switching means. A subtractor that subtracts the target value and outputs the first error data, and a delay unit that delays the first error data output from the subtractor and outputs the second error data, It is possible to perform automatic gain control with respect to a reproduction signal adapted to the transmission characteristics of a recording medium, especially a magnetic recording medium.

In the present invention, the input signal of the variable gain amplifier is a reproduction signal reproduced from a recording medium recorded in sector units including at least a sync signal partial recording area and a user data recording area, and The error data generation circuit generates a first error signal generation section that generates a first error signal based on the output value of the AD conversion means, and a second error signal generated based on the output value of the AD conversion means. And a second error signal generator for selecting the first error signal when reproducing the user data recording area, and selecting the second error signal when reproducing the sync signal partial recording area. The first error signal is composed of switching means for outputting the error data of No. 1 and delay means for delaying the output error data of the switching means by a predetermined time and outputting as the second error data. The generation unit calculates the absolute value of the output value of the AD conversion unit, a target value generation unit that generates a target value of the output of the calculation unit based on the output value of the AD conversion unit, and the output value of the calculation unit. And a first subtractor that subtracts the output target value of the target value generation unit and outputs a first error signal, and the second error signal generation unit squares the output value of the AD conversion means. It is configured to have a squaring calculation means and a second subtracter that subtracts the output value of the squaring calculation means from the target value.

[0023]

According to the present invention, in the automatic gain control system of the feedback control system including the variable gain amplifier, the AD conversion means, and the control signal generation section, a plurality of error data generation circuits are used to generate a plurality of values based on the output value of the AD conversion means. After the error data is generated and the plurality of error data are converted into analog signals by the DA converting means, the plurality of analog error signals are added by the adding means, and the added signals are sent to the variable gain amplifier as analog control signals. I am trying to output. Therefore, in the prior art, the analog control signal was generated by DA conversion after adding the digital error data, whereas in the present invention, the analog control signal is generated by adding the analog error signals by the adding means. There is.

That is, the error data is, for example, 4 to 7
Since the conventional digital addition requires about 2 nsec to 3 nsec because bit data is used, in the present invention, an analog control signal is generated by current addition of analog values faster than that. Therefore, the circuit delay of the feedback control system can be reduced as compared with the conventional case.

Further, according to the present invention, when reproducing the user data recording area, the calculation means for calculating the absolute value of the output value of the AD conversion means and the target value of the output of the calculation means based on the output value of the AD conversion means are set. Selects a first error signal from a first error signal generation unit having a target value generation unit to be generated and a subtraction of the output value of the calculation means and the output target value of the target value generation unit. When reproducing the sync signal partial recording area, a second calculating means for squaring the output value of the AD converting means and a second subtracter for subtracting the output value of the squaring calculating means from the target value are provided. Selecting the second error signal from the error signal generating section, outputting the selected error signal as the first error data, delaying the first error data by a predetermined time by the delay means, and outputting the second error signal. It is output as error data. Therefore, in particular, even when a phase error occurs between the sample clock of the AD conversion means and the output value of the AD conversion means during reproduction of the sync signal partial recording area, the above first
Error data is added to the second error data, the phase error is erased, and the gain of the variable gain amplifier is controlled by the added signal, regardless of the value of the phase error. , The output value of the AD conversion means can be controlled to be constant.

[0026]

EXAMPLES Next, examples of the present invention will be described. FIG. 1 is a block diagram of an AGC circuit showing a main part of a first embodiment of the method of the present invention.

The AGC circuit 41 of this embodiment is a circuit used as the AGC circuit 4 shown in FIG. 10, and the same components as those in FIG. 12 are designated by the same reference numerals. Further, the signal 102 input to the AGC circuit 41 of this embodiment is a signal reproduced from the magnetic recording medium having the sector format track shown in FIG. 11 as in the conventional case.

Here, the operation sequence of the timing extraction circuit 5 and the AGC circuit 4 (41) for the sector format on the magnetic recording medium 1 of FIG. 10 will be described with reference to FIG. 2 in the order of (a) to (g). To do. In FIG.
(A) is a sector format on the magnetic recording medium 1. At the time of reproduction, the timing of the beginning of each sector (see FIG.
In (a)), the sector pulse is output from the sector detection circuit 7 of FIG. 10 as shown in FIG. 2 (B).

When the controller 8 shown in FIG. 10 receives the sector pulse, as shown in FIG. 2 (C), (b)
The read gate 201 is enabled (H
Level). In response to the enable of the read gate 201, the timing extraction circuit 5 performs a phase pull-in operation at the SYNC 62 in the sector shown in FIG. 2A as shown in FIG.
Controls to synchronize the phase with. Further, the AGC circuit 4 (41) performs an amplitude pull-in operation to adjust to an appropriate reproduction signal amplitude, as shown in FIG. 2 (E).

Subsequently, the timing extraction circuit 5 operates as shown in FIG.
As shown in (D), in order to keep the phase of the reproduced signal at ID 63 and the phase of the sample clock 103 synchronized,
The phase tracking operation is started from the timing shown in (c).
In addition, the AGC circuit 4, as shown in FIG.
The amplitude tracking operation is started from the timing shown in (c), and control is performed so as to maintain an appropriate signal amplitude. When the reproduction of the ID 63 is completed, the controller 8 disables the read gate 201 at the timing of FIG. 2 (d) as shown in FIG. 2 (C) (L level).

When the address information reproduced by the ID 63 is equal to the address of the sector to be read, the controller 8 again reads the read gate 2 at the timing shown in FIG.
01 is enabled as shown in FIG. In response to the enable of the read gate 201, the timing extraction circuit 5 performs a phase pull-in operation by the SYNC 65 as shown in FIG. 2D, and controls the reproduction signal and the timing clock 103 to be in a phase synchronized state, AGC circuit 4
2A, as shown in FIG. 2E, an amplitude pull-in operation is performed to adjust to an appropriate reproduction signal amplitude. FIG. 2F shows the start timing of the phase tracking and the amplitude tracking. The timing extraction circuit 5 carries out a phase following operation so that the phase of the reproduction signal of DATA 66 and the phase of the timing clock 103 are kept synchronized. Further, the AGC circuit 4 performs an amplitude tracking operation and controls so as to maintain an appropriate signal amplitude.
The reproduction signal 104 read in this state is output to the decoding circuit 6 shown in FIG. 10 and decoded together with the sample clock 103.

Viterbi decoding is an example of using a digital value in the decoding circuit 6. Viterbi decoding is digitally maximum likelihood decoding (ML: Maximum Likelilih).
It is one of the methods for realizing the "odd)", and is a decoding method that considers the combination of the reproduction signal values in time series. When the Viterbi decoding using the digital value is used, the timing extraction circuit 5 and the AGC circuit 4 are also suitable for the configuration using the digital value. When digital maximum likelihood decoding is used in the signal processing system of the magnetic recording / reproducing apparatus, partial response (PR: Partial Responses) is used.
The means e) which uses a code form having a power spectrum adapted to the transmission characteristics of the magnetic recording medium is also used.

PR4 (Partial Responses) is suitable for the magnetic recording apparatus of this embodiment.
e Class 4). PRML (Partial Response) is a means for realizing high density of a magnetic recording device by using partial response and maximum likelihood decoding together.
ns Maximum Maximum Likelihood). The configuration of the AGC circuit 4 using such a partial response is the AGC circuit 41 of the first embodiment of the main part of the method of the present invention shown in FIG.

As shown in FIG. 1, the AGC circuit 41 controls the control signal 1 when the read gate 201 is at a high level.
Amplification gain is controlled by 22 and read gate 201
Is low level, VGA1 which holds the gain
1 and EQ1 for equalizing the waveform of the output 111 of the VGA 11
2 and an ADC 13 that quantizes the output 112 after equalization,
Bandwidth limitation of quantized output for PR4 processing [1+
D] processing circuit 14 and a VGA controller circuit 25 that detects an error from the target amplitude from [1 + D] processed signal 104 and outputs error data 117 and error data 118 delayed by one sample clock, respectively. Two types of DACs 16a and 16b for converting the two types of error data 117 and 118 into analog values and two types of D
An analog adder 26 that adds the outputs of the ACs 16a and 16b, a multiplier 17 that multiplies the analog addition output 125 by a predetermined constant, and an integrator that integrates the output signal 121 of the multiplier 17 to generate a VGA control signal 122. 18 and.

The VGA controller 25, which detects an error from the target amplitude after the [1 + D] processing and generates error data 117 and 118, determines the level of the input signal 104 and generates the determination signal 114. Discriminator 19
And a multiplier 20 that multiplies the value of the input signal 104 and the value of the determination signal 114, and selects and outputs either "A" or "0" as the target amplitude value based on the value of the determination signal 114. MPX 21 from the value of the output 115 of the multiplier 20
A subtractor 22 that subtracts the value of the output 116 of the output 21 to generate the error data 117, and the output error data 11 of the subtractor 22.
The delay unit 23 delays the value of 7 by one clock by the timing clock 103 and outputs the error data 118.

The amplitude pull-in operation of the AGC circuit 41 having the above structure will be described with reference to the timing chart of FIG.
However, FIG. 3 shows the operation with respect to the reproduction signal in the area of the SYNC 62, 65 in which the synchronization signal of the regular pattern is recorded. By the timing extraction circuit 5 of FIG.
The sample clock 103 generated at the timing synchronized with the AGC output signal 104 is a square wave having a constant period as shown in FIG. 3A and is supplied to the ADC 13, the [1 + D] processing circuit 14 and the delay unit 23 of FIG. 1, respectively. To be done.

After the output signal 102 of the preamplifier 3 shown in FIG. 3 (B) is amplified by the VGA 11 with a gain corresponding to the voltage level of the control signal 122 of FIG. 1 to become the signal 111 shown in FIG. 3 (C). , EQ12 and supplied to the ADC 13 for analog-digital conversion. ADC13
3 samples the EQ output signal 112 with the sample clock 103 and captures it as a digital value.
The signal 113 shown in (D) is output. Here, SYN
Since it is a reproduced signal in the area of C62 and C65, the ADC output signal 11 sampled by the sample clock 103
3 is the same as the conventional one, as shown in FIG.
The data string has a periodicity such as A, 0, A, 0, -A, 0, A, 0 ...}.

The [1 + D] processing circuit 14 outputs the ADC output to the ADC output signal 113 which is a data string of {-A, 0, A, 0, -A, 0, A, 0 ...} for PR4 processing. By performing a [1 + D] process of adding a signal obtained by delaying the signal 113 by one sample clock, {-A, -A, A, A, -A, -A, A, as shown in FIG. A
}} Is generated and output. This [1
+ D] output data string 104 is supplied to the discriminator 19 of FIG. 1, where the signal levels thereof are “−A”, “0”,
It is determined which of the two is “A”, and as a result, as shown in FIG.
As shown in (F), when the 1 + D output signal 104 is "-A", it is converted into "-1", when it is "0", it is converted into "0", and when it is "A", it is converted into "1" and output. It

Here, there is no case where the discriminator 19 outputs "0" because it is a reproduced signal in the SYNC 62 and 65 areas. The determination condition of the discriminator 19 is, for example,
It is as follows.

[0040]

(Signal 104) ≧ A / 2 (Signal 114) = 1 A / 2> (Signal 104)> − A / 2 (Signal 114) = 0−A / 2 ≧ (Signal 104) (Signal 114) =-1 However, "A" is the amplitude pull-in target value at the sampling point of the output signal 111 of the VGA 11.

This discriminator output signal 114 is supplied to the multiplier 20.
Where it is multiplied by the [1 + D] output signal 104 and, as shown in FIG.
4 is converted into an absolute value signal 115. The discriminator output signal 114 is also supplied to the MPX 21, where it is converted into the signal 116 shown in FIG. 3 (H) and is input to the subtractor 22 as the target value of the output signal 115 of the multiplier 20. This MPX output signal 116 is the discriminator output signal 11
When the value of 4 is "-1" or "1", it is output as "A", and when the value of the discriminator output signal 114 is "0", it is output as "0".

The subtractor 22 subtracts the multiplier output signal 115 from the MPX output signal 116 which is its target value,
The error data (difference signal) 117 shown in (I) is output. The error data 117 is branched into two, one of which is the delay unit 23.
Is delayed by one sample clock to form delay error data 118 as shown in FIG.
16b. The DAC 16a uses the error data 11
7 is digital-analog converted to output an analog error signal 123 as shown in FIG.

On the other hand, the DAC 16b outputs the delay error data 1
Digital-to-analog conversion is performed on 18 to output an analog error signal 124 as shown in FIG. These error signals 123 and 124 are respectively supplied to the adder 26, where they are added to form the analog addition signal 125 shown in FIG. This analog addition signal 125
Is multiplied by a constant by the multiplier 17, integrated (filtered) by the integrator 18, and then controls the gain of the VGA 11 as the control signal 122.

At this time, the gain of the VGA 11 is adjusted so that the value of the analog addition signal 125 becomes zero.
That is, when the analog addition signal 125 has a positive value, the gain of the VGA 11 is controlled to be decreased, and when the analog addition signal 125 has a negative value, the VGA 11 has a negative value.
The gain is controlled to increase. As a result, [1+
D] The level at the sampling point of the output signal 104 is “A”
Is adjusted to. By the above feedback control, the level of the ADC output signal 113 at the sampling point converges to a constant value "A".

Next, the ID 63 and DATA of the present embodiment.
The amplitude tracking operation for the reproduced signal in the area 66 is shown in FIG.
Will be explained. FIG. 4A shows the sample clock 10
3 and the ADC output signal 1 in the same manner as in FIG.
It is generated at the timing synchronized with 13. In contrast,
Signal 102 input to VGA 11 from preamplifier 3
Unlike FIG. 3B, since the signal is a signal in which the areas of ID63 and DATA66 are reproduced, it has a random waveform with no periodicity, as shown in FIG. 4B.

As a result, the VGA output signal 111 is shown in FIG.
In (C), the ADC output signal 113 is as shown in (D) of the same figure, and the data string 104 further processed by [1 + D] is as shown in (E) of the same figure. This [1 + D] processed data string 1
As shown in FIG. 4 (E), 04 is a level fluctuation compared to the signal (FIG. 3 (E)) at the time of reproduction in the area of SYNC 62, 65 in which the synchronization signal of the regular pattern is recorded. Is big.

This [1 + D] output data string 104 is supplied to the discriminator 19 of FIG. 1, and if the signal level is "-A" based on the above-mentioned judgment condition, "-" is output.
1 "," 0 "for" 0 "," A "for" 1 "
Are converted and output. As a result, the output signal 114 of the discriminator 19 becomes as shown in FIG.

This discriminator output signal 114 is supplied to the multiplier 20.
Which is then multiplied by the [1 + D] output signal 104 and, as shown in FIG.
Is converted into an absolute value signal 115. Also, FIG.
(H) is a signal 116 output from the MPX 21 as an amplitude target value of the multiplier output signal 115. When the value of the discriminator output signal 114 is “−1” or “1”, “A” is output, When the value of the discriminator output signal 114 is "0", "0" is output. FIG. 4 (I) shows the subtractor output signal 1
17, the same figure (J) shows the subtracter output signal 117 as DACa1.
The output signal 123 converted into a continuous signal by 6 and the subtracter output signal 117 in FIG.
The delay clock output signal 118 delayed by the sample clock, the figure (L) is the DACb output signal 124 obtained by converting the delay clock output signal 118 into a continuous signal by the DAC 16b, and the figure (M) is the analog addition signal extracted from the adder 26. 125 is shown.

This analog addition signal 125 is applied to the multiplier 1
7. Control signal 122 is passed through the integrator 18 and VGA
The gain of 11 is controlled. As a result, ID63, DAT
Even when the area A66 is reproduced, the level of the ADC output signal 113 at the sampling point is controlled to a constant value "A".

As described above, according to this embodiment, the adder 2
Reference numeral 6 filters the signal 117 via the delay unit 23, the DAC 16a and the DAC 16b.
If the DACs 16a and 16b are current output type, the adder 26 has a configuration in which the DAC output signals 123 and 124 are simply connected, and the circuit delay is smaller than that of the adder of the conventional circuit using digital values. You can That is, the delay time of each constituent block of the conventional ABC circuit 4 shown in FIG. 12 and the delay time of each constituent block of this embodiment are summarized in Table 1.

[0051]

[Table 1]

The conventional VGA controller circuit 15 is
[1 + D] The error between the processed signal and the target amplitude is detected,
The error data and the error data delayed by one clock are added in the state of digital values, and the output is D
It was converted into an analog value by AC16. As error data with respect to the target amplitude, for example, data of 4 to 7 bits is used, and therefore the addition by the adder 24 is 2 to 3 nse.
As a result, as shown in Table 1, the total delay time of the conventional AGC circuit is about 50 nsec.
Is.

On the other hand, in the present embodiment, the addition of digital values is replaced by the current addition of high-speed analog values. In the case of current addition of analog values, the addition is performed simply by connecting the signal lines. Especially fast because it can be realized. Therefore, the total delay time of the AGC circuit of this embodiment is
As can be seen from Table 1, it is about 40 nsec, and the delay time can be shortened by about 20% as compared with the conventional circuit. As a result, in the present embodiment, the phase delay described with reference to FIG. 14B is reduced by about 20% as compared with the conventional circuit.

Therefore, according to the present embodiment, when the same phase margin as in the conventional case is secured, the bandwidth of the feedback control system can be increased by the amount of decrease in the total delay time, and the amplitude pull-in time can be increased. Can be reduced by about 20%. Therefore, the SYNC area for pulling in the amplitude can be reduced by about 20%, and by allocating that portion to the user data area, the capacity of the magnetic recording medium can be increased. That is, the synchronizing signal pattern area on the magnetic recording medium can be reduced by performing a particularly high-speed amplitude pull-in operation, and as a result, the occupation rate of user data on the magnetic recording medium can be increased.

Further, according to the present embodiment, the circuit delay of the feedback control system can be made smaller than before by replacing the addition of the digital value with the addition of the analog value, so that a sufficient phase margin can be secured. A high-speed and stable amplitude pull-in operation and amplitude follow-up operation can be performed.

Next, a second embodiment of the present invention will be described. FIG. 5 is a block diagram of the VGA controller circuit in the AGC circuit 4 which is the main part of the second embodiment of the present invention. The same components as those in FIG. 1 are designated by the same reference numerals.

The AGC circuit of this embodiment is the VG shown in FIG.
Except for the configuration of the A controller circuit 45, it is the same as the first embodiment shown in FIG. 6 and 7 are timing charts for explaining the amplitude pull-in operation of the VGA controller circuit 45 of this embodiment.

As shown in FIG. 5, the VGA controller 4
5 is an error signal 14 for performing an amplitude follow-up operation by using the reproduced signal in the area of ID63 and DATA66 of FIG.
The first error signal generation circuit 41 for generating 1 and the SYNC 6 of FIG. 11 in which the synchronization signal having a regular pattern is recorded.
The second error signal generation circuit 42 for generating the error signal 142 for performing the amplitude pull-in operation using the reproduced signals in the regions 2, 65, the regions of ID63, DATA66 and SYN.
The MPX 36 for switching and using the error signal in the area of C62 and C65, and the delay unit 23 for delaying the output signal 117 of the MPX 36 by one clock by the sample clock 103.

The first error signal generating circuit 41 is based on the discriminator 19 for generating the judgment signal 114, the multiplier 20 for multiplying the value of the input signal 104 and the value of the judgment signal 114, and the value of the judgment signal 114. MPX21 that selects and outputs either "A" or "0" as the target amplitude value, and the output 1 of the multiplier 20
The subtractor 22 subtracts the value of the output 116 of the MPX 21 from the value of 15 to generate the error data 141. In addition, the second error signal generation circuit 41 subtracts the square value 132 of the amplitude target value “A” from the output value 131 of the multiplier 31 and the multiplier 31 for performing the square operation of the input signal 104 to obtain the error. It consists of a subtractor 32 that produces a signal 142.

First, referring to FIG. 11 of the circuit of FIG. 5, ID63, D
The amplitude tracking operation for the reproduced signal in the area indicated by ATA66 will be described. The [1 + D] processed signal 104 is
The signal is output to the discriminator 19 in the error signal generation circuit 41, and the discriminator determines whether the signal 104 is "-A", "0", or "A", and the input signal 104 is "-A". In this case, "-1" is output as the discriminator output signal 114, and "0" is output.
In the case of, "0" is output, and in the case of "A", "1" is output. The multiplier 20 multiplies the signal 104 and the discriminator output signal 114, and outputs a multiplier output signal 115 which is the absolute value of the signal 104. The MPX 21 produces an output signal 116 which is the target value of the multiplier output signal 115,
When the value of the discriminator output signal 114 is "-1" or "1", "A" is output, and when the value of the discriminator output signal 114 is "0", "0" is output. The subtractor 22 outputs an error signal 141 that is the difference between the multiplier output signal 115 and the target value of the MPX output signal 116.

The MPX 36 selects this error signal 141 and outputs it as error data 117 when reproducing the area of ID63 and DATA66. The delay device 43 delays the error data 117 by one sample clock to generate the error data 11
Output as 8. As described above, ID63, D
The amplitude tracking operation for the reproduced signal in the ATA 66 area is the same as that of the first embodiment of the present invention.

Next, referring to FIG. 11, SYNC62, SYNC6
The amplitude pull-in operation for the reproduced signal in the area shown by 5 will be described with reference to the timing chart of FIG. As the error data 117 in this case, the error signal generated by the error signal generation circuit 41 is used. FIG. 6A shows a sample clock 103, which is synchronized with the ADC output signal 113 under the control of the timing extraction circuit 5. Figure 6
(B) is the [1 + D] processed signal 104, which is AD
A signal obtained by delaying the ADC output signal 113 by one sample clock is added to the C output signal 113, and [1 + D] processing is performed. {-A, 0, A, 0, -A,
When 1 + D processing is performed on the data sequence of 0, A, 0 ...}, as shown in FIG. 6B, {-A, -A, A, A,-
A data string such as A, -A, A, A ...} is obtained.

This [1 + D] -processed signal 104 is supplied to the multiplier 31, where it is squared to obtain the signal shown in FIG.
After the multiplier output signal 131 as shown in FIG.
It is input to the subtractor 32. Here, V shown in FIG.
The squared value 132 of the target output amplitude “A” of the GA 11 is subtracted to form an error signal 142 indicating the difference between them. Figure 6
(E) shows this error signal 142.

The MPX36 is composed of SYNC62 and SYNC6.
When reproducing the area of No. 5, this error signal 142 is selected and output as the error data 117 shown in FIG. The delay unit 43 delays the error data 117 by one sample clock and outputs the error signal 118 shown in FIG.

The error signals 117 and 118 are shown in FIG.
After being converted into analog signals by the DACs 16a and 16b, the adder 26 adds them in an analog manner. The analog addition signal 125 is multiplied by a constant by the multiplier 17, filtered by the integrator 18, and then controls the gain of the VGA 11 as the control signal 122. At this time, the AGC circuit outputs the analog addition signal 125.
Has a positive value, the gain of the VGA 11 is controlled to decrease, and when the analog addition signal 125 has a negative value, the gain of the VGA 11 is controlled to increase. As a result, the level of the [1 + D] processed signal 104 is controlled to be "A" at the sampling point. Through the above feedback control, the level of the ADC output signal 113 at the sampling point is controlled to a constant value "A".

Further, in FIG. 7, assuming that the period of the sample clock 103 shown in FIG. 7A is T, the [1 + D] -processed signal 104 shown in FIG. 7B can be regarded as a sine function having a period of 4T. . Here, when a phase error of φ occurs between the sample clock 103 and the [1 + D] processed signal 104, the value of the signal 104 is as shown in FIG.
Sample points {k, K + 1, K + 2, K + 3 ...}
Then, {A'sin (π / 4 + φ), A'sin (π / 4
+ Π / 2 + φ), A'sin (π / 4 + 2π / 2 +
φ), A'sin (π / 4 + 3π / 2 + φ) ...}. Here, A ′ indicates the amplitude value of the signal 104 that is a sine wave.

The value of the signal 104 is {A'sin (π
/ 4 + φ), A′cos (π / 4 + φ), −A′sin
(Π / 4 + φ), −A ′ cos (π / 4 + φ) ...}, and the multiplication output value 131 obtained by squaring this with the multiplier 31 is {A ′ ² sin ² (π / 4 + φ), A ^'2 co
s ² (π / 4 + φ), A ′ ² sin ² (π / 4 + φ),
A ′ ² cos ² (π / 4 + φ) ...}. That is, the multiplier 31 calculates {A ′ ² sin ² (π / 4 + φ)} and {A ′ ²
cos ² (π / 4 + φ)} are output alternately.

Therefore, the error signal 142 obtained by subtracting the squared value 132 of the target amplitude "A" from the multiplied output value 131 is
{A ′ ² sin ² (π / 4 + φ) −A ² , A ′ ² cos
² (π / 4 + φ) −A ² , A ′ ² sin ² (π / 4 + φ) −
A ² , A ′ ² cos ² (π / 4 + φ) −A ² ...}. After (1 + D) processing is performed using the delay device 43, an analog signal is converted by the DAC 16a and the DAC 16b and added in analog by the adder 26, the output is

[0069]

[Number 2] ^{{A '2 sin 2 (π} / 4 + φ) + A' 2 cos 2 (π / 4 + φ) -2A 2, ...} = {A '2 -2A 2, ...} , and the phase difference phi erased It

Therefore, the AGC circuit is feedback-controlled so that (A ' ² -2A ² ) becomes zero regardless of the value of the phase difference φ. At the convergence point, A '/ √2 = A,

[0071]

## EQU3 ## Since A'sin (π / 4) = A '/ √2, sample points {k, K + shown in FIG.
It is possible to control the amplitude at 1, K + 2, K + 3 ...} to "A".

The present embodiment described above has the same effects as the first embodiment. Further, the amplitude pull-in operation can be accurately performed even when the reproduction signal and the sample clock are not synchronized.

By the way, in the AGC circuit 41, [1
The + D] processing circuit 14 is for realizing PR4, and has a differential characteristic at the time of reproduction from the magnetic recording medium and [1+
The D4 characteristic is combined to realize the PR4 characteristic. Therefore, a configuration in which the [1 + D] characteristic is included in another block in the reproduction path until it is input to the decoding circuit 6 is possible, and the [1 + D] processing circuit 14 may not be included in the AGC circuit 4.

FIG. 8 is a block diagram of an AGC circuit showing a main part of the third embodiment of the present invention system in this case. The AGC circuit 42 of this embodiment is a circuit used as the AGC circuit 4 shown in FIG. 10, and the same components as those in FIG. 1 are designated by the same reference numerals. As shown in FIG. 8, the AGC circuit 42 of this embodiment does not have the [1 + D] processing circuit 14 provided between the ADC 13 and the VGA controller 25, which is provided in the embodiment of FIG.

The amplitude pull-in operation of the AGC circuit 42 having this structure will be described with reference to the timing chart of FIG. However, FIG. 9 shows the operation with respect to the reproduction signal in the area of the SYNC 62, 65 in which the synchronization signal having the regular pattern is recorded. The timing extraction circuit 5 of FIG.
The sample clock 103 generated at the timing synchronized with the C output signal 104 is a square wave having a constant cycle as shown in FIG. 9A and is supplied to the ADC 13 and the delay unit 23 in FIG. 1, respectively.

The output signal 102 of the preamplifier 3 shown in FIG. 9B is amplified by the VGA 11 with a gain corresponding to the voltage level of the control signal 122 shown in FIG. 8 and becomes a signal 111 shown in FIG. 9C. . The ADC 13 samples the output signal 112 passing through the EQ 12 with the sample clock 103, captures it as a digital value, and outputs a signal 113 shown in FIG. 9D. Here, since it is a reproduced signal in the area of SYNC 62, 65, the ADC output signal 113 is {-A, 0, 0, as shown in FIG.
The data string has a periodicity such as A, 0, -A, 0, A, 0 ...}.

The output signal 113 of the ADC 13 is supplied to the discriminator 19, where the signal level is "-".
It is determined which of "A", "0", and "A", and as a result, as shown in FIG.
Is "-1" when "-A", "0" when "0",
In the case of "A", it is converted into "1" and outputted. The determination condition of the discriminator 19 is the same as that of the first embodiment.

FIG. 9F is an output signal 115 of the multiplier 20 for multiplying the ADC output signal 113 and the discriminator output signal 114, which is a signal obtained by converting the ADC output signal 113 into an absolute value. FIG. 9G shows the output signal of the MPX 21, which is input to the subtractor 22 as the target value of the output signal 115 of the multiplier 20. This MPX output signal 116 is "A" when the value of the discriminator output signal 114 is "-1" or "1",
When the value of the discriminator output signal 114 is "0", it is output as "0".

The subtractor 22 subtracts the multiplier output signal 115 from the MPX output signal 116 which is its target value,
The error data (difference signal) 117 shown in (H) is output. As a result, in the same manner as the first embodiment, the DAC 16
a output analog error signal 123 (FIG. 9 (I)), output delay error data 118 of the delay unit 23 (FIG. 9 (J)), D
The output analog error signal 124 of the AC 16b (see FIG.
(K)) is generated respectively, and the adder 26 generates
An analog addition signal as shown in (L) is taken out.

Then, similarly to the first embodiment, the analog addition signal 125 is controlled through the multiplier 17 and the integrator 18 as the control signal 122 so that the gain of the VGA 11 becomes zero so that the value of the analog addition signal 125 becomes zero. As a result, the level of the output signal 113 of the ADC 13 at the sampling point is adjusted to be "A".

The present invention is not limited to the above embodiment, and for example, the EQ 12 equalizes the signals to be handled and compensates the performance of the timing extraction circuit 5 and the decoding circuit 6. Therefore, the timing extraction circuit 5 may be included in the configuration, and the EQ 12 may not be included in the AGC circuit. Further, the present invention can be applied to not only a magnetic disk but also a reproduction signal of another recording medium such as an optical disk or a magnetic tape.

[0082]

As described above, according to the present invention,
By generating an analog control signal by high-speed current addition of analog values, it is possible to reduce the circuit delay of the feedback control system as compared to the conventional one, and thus at high speed,
In addition, the stable amplitude pull-in operation and amplitude follow-up operation can be performed. Further, by performing the high-speed amplitude pull-in operation, the sync signal partial recording area on the recording medium can be reduced, and as a result, the occupation efficiency of the user data on the recording medium can be improved. Furthermore, according to the present invention, the output value of the AD conversion means can be controlled to be constant regardless of the value of the phase error between the sample clock of the AD conversion means and the output value. Even if the output value of the AD conversion means is not synchronized, the amplitude pull-in operation can be accurately performed.

[Brief description of drawings]

FIG. 1 is a block diagram of an AGC circuit of a main part of a first embodiment of the system of the present invention.

FIG. 2 is an explanatory diagram of an operation sequence of the AGC circuit of FIG.

FIG. 3 is a time chart for explaining the operation of the AGC circuit of FIG. 1 when reproducing the SYNC area and the like.

FIG. 4 is a time chart for explaining the operation of the AGC circuit of FIG. 1 when reproducing the data area and the like.

FIG. 5 is a block diagram of an essential part of a second embodiment of the system of the present invention.

FIG. 6 is a time chart for explaining the operation of the AGC circuit of FIG. 5 during reproduction of the SYNC area and the like.

7 is an explanatory diagram of the operation of the VGA controller circuit of FIG.

FIG. 8 is a block diagram of an AGC circuit of a main part of a third embodiment of the system of the present invention.

9 is a time chart for explaining the operation of the AGC circuit of FIG. 8 when reproducing the SYNC area and the like.

FIG. 10 is a block diagram of a reproduction signal processing circuit of the magnetic recording / reproducing apparatus.

FIG. 11 is a diagram showing an example of a sector format of a magnetic recording medium.

FIG. 12 is a block diagram of an example of a conventional AGC circuit.

13 is a time chart for explaining the operation of the AGC circuit of FIG. 12 when reproducing the SYNC area and the like.

FIG. 14 is a graph showing open-loop phase characteristics of the AGC circuit.

[Explanation of symbols]

1 ... Magnetic recording medium, 2 ... Magnetic head, 3 ... Preamplifier,
4, 41, 42 ... AGC circuit, 5 ... Timing extraction circuit, 11 ... Variable gain amplifier (VGA), 12 ... Equalizer (EQ), 13 ... AD converter (ADC), 14
... [1 + D] processing circuit, 16a, 16b ... DA converter (DAC), 17, 20, 31 ... Multiplier, 18 ... Integrator, 19 ... Discriminator, 21 ... Multiplexer (MP
X), 22, 32 ... Subtractor, 23 ... Delay device, 26 ... Adder, 25, 45 ... VGA controller circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical indication location H04L 25/03 D 9199-5K (72) Inventor Masashi Mori 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa In stock company Hitachi Image Information System (72) Inventor Shintaro Suzumura 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Inside Company Hitachi Image Information System (72) Inventor Tomoaki Hirai 2880 Kozu, Odawara-shi, Kanagawa Stock Company Hitachi Storage Systems Division

Claims (7)

[Claims] 1. A variable gain amplifier for amplifying and outputting an input signal with a gain designated by an analog control signal, an AD conversion means for sampling an output signal of the variable gain amplifier at a predetermined interval, and the AD conversion. Automatic gain control including a control signal generation unit that generates the analog control signal and outputs the analog control signal to the variable gain amplifier so that the output signal of the variable gain amplifier has a predetermined amplitude according to the output value of the means. In the method, the control signal generation unit includes an error data generation circuit that generates a plurality of error data based on the output value of the AD conversion means, and a plurality of error data extracted from the error data generation circuit, which are analog signals. To the DA conversion means and a plurality of analog error signals extracted from the DA conversion means are respectively added, and the addition signal is added. Signal is output to the variable gain amplifier as the analog control signal. 2. The error data generation circuit includes a calculation unit that calculates an absolute value of an output value of the AD conversion unit, and the AD unit.
A target value generation unit that generates a target value of the output of the calculation unit based on the output value of the conversion unit, and subtracts the output value of the calculation unit and the output target value of the target value generation unit to generate the first error data. And a delay unit that delays the first error data output from the subtractor and outputs the second error data. The DA conversion unit includes the first and second error data. 2. The automatic gain control system according to claim 1, wherein each of the error data of 1 is converted into an analog signal. 3. The discriminator for discriminating the output value of the AD conversion means, the multiplier for multiplying the output value of the discriminator and the output value of the AD conversion means, and the discrimination. Means for outputting the target value of the output value of the multiplier based on the output value of the multiplier, and subtracting the output value of the multiplier and the output target value of the switching means for outputting the first error data. A DA converter that delays the first error data output from the subtractor to output second error data, and the DA conversion unit includes the first and second error data. 2. The automatic gain control system according to claim 1, wherein each of the signals is converted into an analog signal. 4. The processing circuit, wherein the error data generation circuit limits the band of the output value of the AD conversion means for partial response processing, a discriminator for discriminating the output value of the processing circuit, and the discrimination. A multiplier for multiplying the output value of the multiplier and the output value of the AD converter, and a switching means for outputting a target value of the output value of the multiplier based on the output value of the discriminator.
A subtracter for subtracting the output value of the multiplier and the output target value of the switching means to output first error data, and a first error data output from the subtractor for delaying the second error data. 2. The automatic gain control method according to claim 1, further comprising a delay unit that outputs error data, wherein the DA conversion unit converts each of the first and second error data into an analog signal. 5. The variable gain amplifier input signal is a reproduced signal reproduced from a recording medium recorded in sector units including at least a sync signal partial recording area and a user data recording area. Item 5. The automatic gain control system according to any one of items 1 to 4. 6. The input signal of the variable gain amplifier is a reproduction signal reproduced from a recording medium recorded in sector units including at least a sync signal partial recording area and a user data recording area, and the error data generating circuit. Is a first error signal generation unit that generates a first error signal based on the output value of the AD conversion unit, and a second error signal generation unit that generates a second error signal based on the output value of the AD conversion unit. The error signal generator and the first error signal are selected when reproducing the user data recording area, and the second error signal is selected when reproducing the synchronization signal partial recording area, and the first error signal is selected. The first error signal is composed of switching means for outputting as data and delay means for delaying the error data output from the switching means by a predetermined time and outputting as the second error data. The generation unit calculates the absolute value of the output value of the AD conversion unit, a target value generation unit that generates a target value of the output of the calculation unit based on the output value of the AD conversion unit, and the calculation unit. Output the first error signal by subtracting the output value of
And the second error signal generator is configured to
The DA converting means includes a square calculating means for squaring an output value of the D converting means, and a second subtracter for subtracting an output value of the square calculating means from a target value. The automatic gain control method according to claim 1, wherein the second error data and the second error data are converted into analog signals. 7. The output value of the AD conversion means is input to the first and second error signal generation units via a processing circuit that performs band limitation for processing of a partial response system. The automatic gain control method according to claim 6, wherein