JPH07288457A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To provide a semiconductor integrated circuit device which can fast select even a large number of data. CONSTITUTION:This semiconductor integrated circuit device is provided with a data selection circuit 100 which is connected to a 1st power terminal VDD, a precharge circuit 200 which is connected to a 2nd power terminal GND and recieves a precharge signal, and a wiring 1 which is connected to a common connection point X between both circuits 100 and 200. The circuit 100 includes at least the 1st and 2nd data transfer circuits 102-1 and 102-2. Thus a 1st input data signal A and a 1st selection signal Ba are inputted to the circuit 102-1, and a 2nd input data signal B and a 2nd selection signal Bb are inputted to the circuit 102-2 respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device in which a plurality of signal lines are combined into one signal line.

[0002]

2. Description of the Related Art At present, there is a multiplexer as a semiconductor integrated circuit device that combines a plurality of signal lines into one signal line. The multiplexer selects one signal line from a plurality of signal lines and electrically connects the selected signal line and the one signal line.

As a multiplexer comprising a CMOS type transistor circuit, a transfer gate type as shown in FIG. 37 or a clocked inverter type as shown in FIG. 38 has been considered. In any case, the selection signals a, Ba, b, Bb, c, Bc, d, B
The data for the high level is selected from d (the leading code “B” indicates an inverted signal) and is transmitted to the common node X which is an output terminal. The signals indicated by reference symbols A to D are input data signals, and the signal Q indicated by reference symbol Q is an output data signal.

However, in the multiplexers shown in FIGS. 37 and 38, when the number of selected data is large, the parasitic capacitance attached to the common node X such as the junction capacitance and the gate capacitance becomes large, and the input data is selected. There is a possibility that the speedup of the data selection operation of outputting the data as a result may be impaired.

[0005]

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device capable of high speed selection operation even when a large number of data are selected.

[0006]

To achieve the above object, in a semiconductor integrated circuit device according to a first aspect of the present invention, a data selection circuit connected to a first power supply terminal and a second power supply. It has a precharge circuit connected to a terminal to which a precharge signal is input, and a wiring connected to a common node of the data selection circuit and the precharge circuit. The data selection circuit includes at least two first and second data transmission circuits, and inputs a first input data signal and a first selection signal to the first data transmission circuit, Two input data signals and a second selection signal are input to the second data transmission circuit.

The semiconductor integrated circuit device according to the second aspect of the present invention is characterized in that the common node is connected to a potential fixing circuit for fixing the potential of the common node to a predetermined potential.

Further, in the semiconductor integrated circuit device according to the third aspect of the present invention, the semiconductor integrated circuit device according to the first aspect or the second aspect is used for a data multiplex circuit of a semiconductor memory device. It is characterized by having been.

Further, in the semiconductor integrated circuit device according to the fourth aspect of the present invention, the semiconductor integrated circuit device according to the first aspect or the second aspect is used for the data multiplex circuit of the semiconductor memory device. At the same time, in addition to the normal mode in which the input data signal is selected by the selection signal, a test mode in which all the input data signals are selected by the selection signal is added.

[0010]

In the semiconductor integrated circuit device having the structure according to the first aspect, the parasitic capacitance added to the common node, particularly the junction capacitance, is the same as the connection point between the first data transmission circuit and the common node. Only the connection point between the second data transfer circuit and the common node and the connection point between the precharge circuit and the common node. Therefore, the parasitic capacitance added to the common node is reduced, and the semiconductor integrated circuit device operates at high speed.

With the semiconductor integrated circuit device having the configuration according to the second aspect, the above-mentioned object can be achieved, and
In the semiconductor integrated circuit device, malfunction due to noise is further suppressed. The potential of the common node becomes floating for a period of time after the precharge circuit is cut off and the data transmission circuit is turned on. By connecting a potential fixing circuit to this common node, the potential of the common node can be fixed to a predetermined potential during the above-mentioned period when the potential of the common node becomes floating. Therefore, malfunction due to noise is suppressed.

In the semiconductor integrated circuit device having the configuration according to the third aspect, the parasitic capacitance of the data multiplex circuit becomes small. Therefore, the semiconductor memory device operates at high speed.

The semiconductor integrated circuit device having the configuration according to the fourth aspect simplifies the test circuit. In the semiconductor integrated circuit device according to the first aspect or the second aspect, the OR operation can be performed by simultaneously transmitting all the input data signals to the common node. This logical sum operation function is used to determine whether the data is correct or incorrect. That is, the data multiplex circuit can be used as a logical sum operation circuit of the test circuit, and as a result, the test circuit is simplified.

[0014]

EXAMPLES The present invention will be described below with reference to examples. In this description, the same parts are denoted by the same reference numerals in all the drawings, and duplicated description will be avoided. 1 is a block diagram of a semiconductor integrated circuit device according to a first embodiment of the present invention, and FIG. 2 is a circuit diagram of a semiconductor integrated circuit device according to the first embodiment of the present invention.

As shown in FIG. 1, the integrated circuit device according to this embodiment includes a data selection circuit 100 and a precharge circuit 200, which are connected in series between a high potential power supply terminal VDD and a ground terminal GND. Including. Circuit 100 and circuit 200
The wiring 1 is arranged between the and. This wiring 1
It is connected to the common node X of the circuit 100 and the circuit 200. The common node X is an output terminal of the integrated circuit device according to this embodiment. From the output terminal (common node X),
The output data signal BQ is output. The output signal BQ
The sign "B" at the beginning of the symbol indicates that the level of the input data signal is inverted and output. Further, in this specification, the code "B" at the head indicates that the level of the input signal is inverted and output, or that the signal itself is negative logic, as described above. Define. Further, in the drawings, the leading code “B” is represented by the code “−” (bar).

As shown in FIG. 2, the data selection circuit 100.
Includes a plurality of PMOS series circuits 102. Multiple PM
The OS series circuit 102 is connected in parallel between the terminal VDD and the common node X. The PMOS series circuit 102 is
Two P-channel MOSFETs connected in series with each other
2 (hereinafter referred to as PMOS) and PMOS 3 are included. The PMOS 2 connected to the terminal VDD is a transistor for receiving an input data signal, and the PMOS 3 connected to the common node X is a transistor for receiving a data selection signal.

In the integrated circuit device according to this embodiment, PM
The OS series circuit 102 includes four sets (102-1 to 102-
4) It is provided. The PMOS series circuit 102-1 has P
The other PMOS series circuits 102-2, 102-3 and 102-4 each including PMOS 2-1 and PMOS 3-1 are P
MOS2-2 and 3-2, PMOS2-3 and 3-3, PMOS2-4
And 3-4 are included. Input data signals A to D are supplied to the gates of the PMOSes 2-1 to 2-4, respectively. PM
The OSs 2-1 to 2-4 become conductive when the potentials of the data signals A to D become low level. On the other hand, the selection signals Ba to Bd are supplied to the gates of the PMOSs 3-1 to 3-4, respectively. The PMOSs 3-1 to 3-4 become conductive when the potentials of the selection signals Ba to Bd become low level.

The precharge circuit 200 includes one N-channel MOSFET (hereinafter referred to as NMOS) 4 connected in series between the terminal GND and the common node X. N
The MOS4 is a transistor for receiving the precharge signal, and the gate of the NMOS4 is supplied with the precharge signal PRCH.

One of the important functions of the NMOS 4 is the output signal BQ in response to the precharge signal.
Is to set the initial state of the potential level of. Another function is in response to the precharge signal in FIGS.
Is to control activation / deactivation of the integrated circuit device itself shown in FIG.

The NMOS 4 conducts while the signal PRCH is at the high level, and charges the common node X to the ground potential. At this time, the initial state of the potential level of the output signal BQ is the ground potential. At the same time, since the common node X is charged to the ground potential, the integrated circuit device itself becomes inactive. That is, even if the data signal and the data selection signal are input to the data selection circuit 100, the potential of the common node X does not substantially change from the ground potential.

On the other hand, the NMOS 4 turns off during the period when the signal PRCH is at the low level. At this time, the integrated circuit device itself shown in FIG. 1 is activated, and the common node X is charged to a predetermined potential by the current output from the PMOS series circuit 100.

Next, the basic operation of the integrated circuit device shown in FIGS. 1 and 2 will be described. FIG. 3 is an operation waveform diagram showing an operation of the integrated circuit device according to the first embodiment of the present invention.

In the integrated circuit device shown in FIGS. 1 and 2,
The data signals A, B, C, D corresponding to the low level ones of the selection signals Ba, Bb, Bc, Bd are transmitted to the common node X. That is, the precharge signal PRC
First, H is set to a high level, and the common node X is fixed to a low level (ground potential) (T1). After that, the precharge signal PRCH is lowered to the low level (T2), and the common node X is set to the floating low level (T2).
3). Next, of the selection signals Ba, Bb, Bc, Bd,
Only one is low level. Suppose that the signal is Ba (T
4). At this time, it is determined whether the common node X is charged to a high level or remains at a low level (a floating low level in this embodiment) depending on whether the data signal A transits from a high level to a low level. Can be decided. In FIG. 3, the data signal A transits from the high level to the low level (T5). Therefore, the common node X is charged to a high level (T6).

The precharge level of the data signals A to D of the integrated circuit device shown in FIGS. 1 and 2 is a high level (high level precharge type). In the high level precharge type integrated circuit device, the input data signal is transmitted to the common node X depending on whether or not the potential level of the input data signal transits to the low level.

When outputting one data signal and then another data signal, first, the selection signal Ba is selected.
To a high level (T11). After that, the precharge signal PRCH is set to high level (T12), and the common node X is charged to low level (ground potential) (T13). By this operation, the integrated circuit device returns from the active period to the precharge period. After that, if the above operation is performed for the other selection signals Bb, Bc, Bd, the data signals B, C, D can be transmitted to the common node X.

As described above, the integrated circuit device according to the first embodiment of the present invention can function as a multiplexer, for example. This is because only one data signal line can be selected from the plurality of data signal lines and the selected data signal line can be electrically connected to one wiring 1.

FIG. 4 is a diagram showing parasitic capacitance on the common node X of the integrated circuit device shown in FIGS. 1 and 2. Similarly, FIG. 5 is a diagram showing parasitic capacitance on the common node X of the multiplexer shown in FIG. 37, and FIG. 8 is a diagram showing parasitic capacitance on the common node X of the multiplexer shown in FIG. 38.

As shown in FIG. 4, the parasitic capacitance attached to the common node X of the integrated circuit device shown in FIGS.
The N junction capacitance PN-J is used for selecting signals Ba and B.
PMOS3 in which b, Bc, and Bd are input to the gate
-1 to 3-4 has four drain junction capacitors and the precharge signal PRCH is input to the gate, NM
There is only one drain junction capacitance of OS4, a total of five.

On the other hand, as shown in FIG. 5, in the multiplexer shown in FIG. 37, the PN junction capacitance PN-J attached to the common node X has four junction capacitances of the drain of the PMOS of the CMOS type transfer gate circuit. , There are four NMOS drain capacitances, for a total of eight.

Further, as shown in FIG. 6, the PN junction capacitance PN-J of the multiplexer shown in FIG. 38 at the common node X has a junction capacitance of the drain of the PMOS of the CMOS type clocked inverter circuit of 4
There are four NMOS junction drain capacitances, for a total of eight.

Therefore, although the integrated circuit device shown in FIGS. 1 and 2 can function as a multiplexer, parasitic capacitance is significantly reduced and operates at high speed as compared with the multiplexers shown in FIGS. 37 and 38. To do.

Further, since the data signals A, B, C, D change from the high level (precharge state) to the low level, these signals are changed from the power supply voltage VDD to the absolute value of the PMOS threshold voltage Vth. If the value drops, PMOS2
(2-1 to 2-4) become conductive and the data signal is transmitted to the common node X. Therefore, the data signals A, B, C, D can be transmitted to the common node X at a very high speed.

Due to these advantages, the integrated circuit device shown in FIGS. 1 and 2 has the multiplexer shown in FIG.
It operates faster than any of the multiplexers shown in FIG.

The basic structure and operation are as described above. Next, a second embodiment of the present invention will be described. The second embodiment is a specific application example of the present invention, in which the integrated circuit device according to the present invention is applied to a data multiplex circuit of a dynamic RAM (DRAM).

FIG. 7 shows a D according to the second embodiment of the present invention.
A schematic block diagram of the RAM, FIG.
9 is a block diagram showing one of the megabit cell arrays in more detail, FIG. 9 is a block diagram showing one of the 256 kilobit cell arrays shown in FIG. 8 in more detail, and FIG.
3 is a circuit diagram showing in more detail one of the DQ buffers shown in FIG.

The DRAM shown in FIG. 7 is a 64-megabit D
RAM. 64 megabit DRA as shown in FIG.
M is four 16-megabit cell arrays A, B, C, D
including.

Further, as shown in FIG. 8, a row decoder is arranged at the center of each 16-megabit cell array. The row decoder has 13 pairs of row addresses A0R to
A12R and BA0R to BA12R are input. A column decoder is arranged at one end of the 16-megabit cell array. Eight pairs of column addresses A0C to A7C and BA0C to BA7C are input to the column decoder.
The 16 megabit cell array further includes 64 256 kilobit cell arrays.

As shown in FIG. 9, a bit line pair precharge circuit (PC), a sense amplifier (SA) and a DQ gate (DQG) are arranged on both sides of the 256 kilobit cell array (ARY). The bit line pair precharge circuit (PC) equalizes the potential difference between the bit line pair (the bit line pair includes the bit line BL and the inverted bit line BBL) to precharge the bit line pair. After the bit line pair is precharged, the data signal is read from the memory cell (CELL). At this time, a slight potential difference occurs between the bit line pair. Sense amplifier (SA)
Amplifies this slight potential difference. DQ gate (DQ
G) uses the data signal amplified by the sense amplifier (SA) as the data line pair (DQ line pair is D
It includes a Q line DQ and an inverted DQ line BDQ. ).
The signal CSL is a signal for selecting a column of the memory cell array and is output from the column decoder. In the DRAM according to this embodiment, one data line pair has 25
Four pairs are arranged on both sides of the 6K cell array (ARY).

The DRAM according to this embodiment inputs the data signal amplified by the sense amplifier (SA) to the four DQ buffers (DQB) shown in FIG. 9 during the normal read operation. The data signal input to the DQ buffer (DQB) is further amplified by the DQ buffer (DQB).
The data signal further amplified by the DQ buffer (DQB) is input to the read / write data line pair (the read / write data line pair includes the read / write data line RWD and the inverted read / write data line BRWD).

As shown in FIG. 10, the DQ buffer (DQ
B) is a DQ line equalizer 300 for equalizing the potential difference between the DQ line pair (DQ, BDQ) and a data signal
A transmission gate 302 for transmitting from the Q line pair to the internal DQ line pair (DQI, BDQI), an internal DQ line equalizer 304 for equalizing the potential difference between the internal DQ line pairs, and a sense amplifier for amplifying the potential difference between the internal DQ line pairs. 306 and the internal D
The data of the Q line pair is read / write data line pair (RWD,
RWD line-to-driving circuit 30 for outputting to BRWD)
8 and.

Further, the RWD line equalizer 310 for equalizing the potential difference between the read / write data line pair includes the read / write data line RWD and the inverted read / write data line BR.
It is connected to WD.

The DQ line equalizer 300 has a PMOS 3 connected in series between the high potential power supply terminal VDD and the DQ line.
21, a PMOS 322 connected in series between the power supply terminal VDD and the BDQ line, and a PMOS 323 connected in series between the DQ line and the BDQ line. PMOSs3
The gates of 21, 322 and 323 are connected to the wirings to which the DQ line equalize signal CEQ is supplied.

The transmission gate 302 includes a PMOS 324 connected in series between the DQ line and the DQI line, and a PMOS 325 connected in series between the BDQ line and the BDQI line. The gates of the PMOSs 324 and 325 are respectively the inversion signal LATCH of the inversion latch signal BLATCH.
Are connected to the supplied wiring.

The internal DQ line equalizer 304 has a PMOS 3 connected in series between the power supply terminal VDD and the DQI line.
26, a PMOS 327 connected in series between the power supply terminal VDD and the BDQI line, and a PMOS 328 connected in series between the DQI line and the BDQI line. PMO
The gates of Ss326, 327, and 328 are DQ, respectively.
It is connected to the wiring to which the line equalize signal CEQ is supplied.

The sense amplifier 306 includes a PMOS 329 connected in series between the power supply terminal VDD and the DQI line,
The PMOS 330 connected in series between the power supply terminal VDD and the BDQI line, and the NMO connected in series between the line to which the inverted latch signal BLATCH is supplied and the DQI line.
The NMOS 3 connected in series between S331 and the line to which the inverted latch signal BLATCH is supplied and the BDQI line.
32 and 32. The gate of the PMOS 329 is connected to the BDQI line. The gate of the PMOS 330 is connected to the DQI line. The gate of the NMOS 331 is connected to the BDQI line. The gate of the NMOS 332 is connected to the DQI line.

The RWD line pair driving circuit 308 is
Two-input NOR gate 333 having an input terminal connected to the QI line and two having an input terminal connected to the BDQI line
An input NOR gate 334, an NMOS 335 connected in series between the output terminal of the NOR gate 333 and the low potential power supply terminal GND, and a series connection between the output terminal of the NOR gate 334 and the power supply terminal GND. NMOS 33
6, an NMOS 337 connected in series between the RWD line and the power supply terminal GND, and an NMOS 338 connected in series between the BRWD line and the power supply terminal GND. NO
The other input terminal of each of the R gates 333 and 334 is
It is connected to the output terminal of the NAND gate 339. Address signal group ADDRE for block selection
SS is input to a plurality of input terminals of the NAND gate 339. The gates of the NMOSs 335 and 338 are connected to the output terminal of the NOR gate 334, respectively.
The gates of the NMOSs 336 and 337 are NOR
It is connected to the output terminal of the gate 333.

The RWD line equalizer 310 has a power supply terminal V
PMOS 34 connected in series between the DD and RWD lines
0, a PMOS 341 connected in series between the power supply terminal VDD and the BRWD line, and a PMOS 342 connected in series between the RWD line and the BRWD line. PMOS
The gates of s340, 341, and 342 are RWD, respectively.
The line inversion equalize signal BRWDEQL is connected to the line to which it is supplied.

FIG. 11 is an operation waveform diagram showing an operation of the DQ buffer shown in FIG. As shown in FIG. 11, DQ
When the line equalize signal CEQ and the RWD line inversion equalize signal BRWDEQL are both at high level, D
Q line equalizer 300, internal DQ line equalizer 304,
The RWD line equalizer 310 is off. When the inverted latch signal BLATCH is low level, the transmission gate 302 is off.

From this state, the DQ line equalize signal CE
Q and RWD line inversion equalize signal BRWDEQL
Is set to a low level and the inverted latch signal BLATCH is set to a high level, the DQ line equalizer 300, the internal DQ line equalizer 304, the RWD line equalizer 310, and the transmission gate 302 are turned on. When these circuits are turned on, the potential difference between the DQ line pair and the potential difference between the RWD line pair are equalized to high levels (high level precharge). After this, the DQ line equalize signal CEQ and the RWD line inverted equalize signal BRWDEQ
When L is set to a high level, the DQ line equalizer 30
0, the internal DQ line equalizer 304, and the RWD line equalizer 310 are turned off again. The data signal is transmitted to the transmission gate 3
It is transmitted from the DQ line pair to the internal DQ line pair via 02. The data signals transmitted to the internal DQ line pair are NOR gates 333 and 33 of the RWD line pair driving circuit 308.
4 is input. NOR gates 333 and 334 are NA
When activated by the output signal of the ND gate 339, one of the NMOSs 337 and 338 is turned on according to the level of the data signal transmitted to the internal DQ line pair. For example, when the NMOS 338 is turned on, the charge of the BRWD line is discharged toward the power supply terminal GND via the NMOS 338, and the potential of the BRWD line changes from high level to low level. At this time, the potential of the RWD line remains at the high level. In this way, from the DQ line pair, RWD
A data signal is transmitted to the line pair.

When the NMOS 337 is turned on, the charge on the RWD line is discharged, and the potential on the RWD line changes from high level to low level. At this time, the potential of the BRWD line remains at the high level.

In the DRAM according to this embodiment, two 256K cell arrays (ARY) arranged with the row decoder sandwiched therebetween are activated at the same time, and a total of 8 pairs on both sides by the column selection signal CSL shown in FIG. Data is selectively transmitted to the pair of DQ line pairs. After that, the data signal is amplified by eight DQ buffers (DQB), and eight pairs of RWD
The data signal will be transmitted to the line. Since such a read operation is performed in parallel in all four 16-megabit cell arrays at the same time, the total chip size is 8 ×.
Data of 4 = 32 bits is transmitted to the read multiplexer & write multiplexer (multiplex circuit) in the center of the chip through the RWD line pair. With the above multiplexer, 5 pairs of addresses (A7C to A12C, B
A7C to BA12C) selects the data of the pair of read / write data line pairs RWD and reads the read data line pair R
It is output to D. This enters the output buffer via the selection circuit and is output to the output pad Dout.
The DQ buffer shown in FIG. 10 can set the precharge level of the read / write data line pair to the “H” level, and is used in the multiplex circuit of the DRAM as shown in FIGS.
It is possible to use the integrated circuit device shown in the above.

On the other hand, at the time of normal write, the operation is reverse to the above, and the data input from the outside of the chip is input to the input buffer from the input pad Din and output to the write data line pair WD, BWD. . Then, the read multiplexer / write multiplexer selects one read / write data line pair RWD by five pairs of addresses (A7C to A12C, BA7C to BA12C), and this time, a write DQ buffer (not shown) is selected. Pass through, D
It is input to the bit line pair through the Q line pair and the DQ gate. Thereby, the data is written in the memory cell.

The operation during the test read will be described later. Next, in the above DRAM, a read multiplexer & write multiplexer to which the present invention is applied will be described.

FIG. 12 is a schematic block diagram of the read multiplexer & write multiplexer shown in FIG.
As shown in FIG. 12, the read multiplexer & write multiplexer includes a multiplex signal generation circuit 10,
Read multiplexer 11 and write multiplexer 1
Including 2 and.

The generating circuit 10 outputs 8 from 5 pairs of column addresses (A8C to A12C, BA8C to BA12C).
Multiplex signals BMUL1 to BMUL8 and four multiplex signals BMULA to BMULD,
A total of 12 multiplexed signals are generated.

The read multiplexer 11 is used during normal read operation and test read operation. During a normal read operation, 32 pairs of read / write data line pairs (RWD1 to RWD32, BRWD1 to BRWD3
From 2), 12 multiplexed signals BMUL1-B
Only one pair is selected by using MUL8 and BMULA to BMULD, and the selected one pair is electrically connected to one read data line pair (RD, BRD).

During the test read operation, 32 pairs of read / write data line pairs (RWD1 to RWD32, BR
WD1 to BRWD32) are all selected and all 32 pairs are electrically connected to one read data line pair (RD, BRD). And the logical sum of the signals flowing through all the read / write data line pairs is calculated.

On the other hand, the write multiplexer 12 is used during the normal write operation and the test write operation. During the normal write operation, 32 pairs of read / write data line pairs (RWD1 to RWD32, BRWD1 to BR
12 multiplexed signals MUL1 from WD32)
-MUL8, BMULA-BMULD, select only one pair and write data line pair (WD, BWD)
Are electrically connected to the selected read / write data line pair.

In the test write operation, 32 pairs of read / write data line pairs (RWD1 to RWD32, BR) are used.
WD1 to BRWD32) are all selected, and one pair of write data line pairs (WD, BWD) is electrically connected to all 32 pairs.

Next, the operation will be described with reference to the configuration of each unit. FIG. 13 is a circuit diagram of the multiplex signal generation circuit. As shown in FIG. 13, the multiplex signal generation circuit 10 includes 12 multiplex signal generation gate circuits 14-1 to 14-12. Of the 12 gate circuits, the eight gate circuits 14-1 to 14-8 have three pairs of column addresses A8C to A10C and B, respectively.
8 multiplexed signals B from A8C to BA10C
MUL1 to BMUL8 are generated. Further, the remaining four gate circuits 14-9 to 14-12 have two pairs of column addresses A11C, A12C, BA11C and BA12C.
These twelve gate circuits 14-1 to 14-12 for generating four multiplexed signals BMULA to BMULD.
The configurations are substantially the same. Therefore, the configuration of the gate circuits 14-1 to 14-12 is changed to the multiplex signal BM.
Description will be given focusing only on the gate circuit 14-1 that generates UL1.

The gate circuit 14-1 has a column address BA.
AND with 3 inputs of 8C, BA9C, BA10C
A gate 15 and a NOR gate 16 which uses this output as one input and outputs the output as a multiplexed signal BMUL1.
Including and

The test mode signal TEST is input to the other input of the NOR gate 16. The signal TEST has a low level in the normal mode and has a high level in the test mode. Therefore, in the normal mode, the NOR gate 16 shifts to the AND gate 15
The output level of the multiplex signal BMUL1 is inverted by the AND gate 15
It is determined by the output level of.

On the other hand, in the test mode, the NOR gate 16 always sets the multiplex signal BMUL1 to the low level regardless of the output level of the AND gate 15. The 12 multiplexed signals BMUL1 to BMUL8 and BMULA to BMULD generated in this way are
It is supplied to the read multiplexer 11 and the write multiplexer 12, respectively.

FIG. 14 is a block diagram schematically showing the internal structure of the read multiplexer 11. As shown in FIG. 14, the read multiplexer 11 includes a first multiplex stage 400 and a second multiplex stage 402.

The first multiplex stage 400 includes four multiplex circuits 17-1, 17-2, 17-3, 17-4. The multiplex circuit 17-1 includes eight pairs of read / write data line pairs R connected to the 16-megabit cell array A based on the multiplex signals BMUL1 to BMUL8.
WD1-RWD8 are multiplexed into a pair of internal lead pairs RDA. Similarly, the multiplex circuit 17-2
On the basis of the multiplex signals BMUL1 to BMUL8, multiplex eight pairs of read / write data line pairs RWD9 to RWD16 connected to the 16 megabit cell array B into one pair of internal read line pairs RDB. Similarly,
The multiplex circuit 17-3 uses the multiplex signal BM.
8 pairs of read / write data line pairs RWD connected to a 16 megabit cell array C based on UL1 to BMUL8
17-RWD 24 are multiplexed into a pair of internal lead pairs RDC. Similarly, the multiplex circuit 17-4
On the basis of the multiplex signals BMUL1 to BMUL8, multiplex eight pairs of read / write data line pairs RWD25 to RWD32 connected to the 16-megabit cell array D into one pair of internal read line pairs RDD.

The second multiplex stage 402 includes one multiplex circuit 18. Multiplex circuit 18
Multiplexes four pairs of internal lead lines RDA to RDD into one pair of read data line pairs RD based on the multiplex signals BMULA to BMULD.

FIG. 15 is a circuit diagram of the multiplex circuit 17-1 included in the first multiplex stage 400. The other multiplex circuits 17-2 to 17-4 included in the first multiplex stage 400 have substantially the same circuit configuration except that the read / write data line pair input to the multiplex circuit 17-1 is different. Is. Therefore, the circuit configuration of the multiplex circuit included in the first multiplex stage 400 will be described focusing only on the multiplex circuit 17-1.

The multiplex circuit 17-1 includes a normal phase signal multiplex circuit 19 for integrating eight read / write data lines RWD1 to RWD8 into one internal read data line RDA, and an inverted read / write data line BRWD1. ~
Eight BRWD8 and one inverted internal read data line R
And a multiplex circuit 20 for inverted signals which is integrated with DA.

The positive phase signal multiplex circuit 17 has the same structure as that of the apparatus shown in FIGS. Particularly, the difference is that the data signal transmission PMOS group 2 (2-1 to 2)
-8) and the output selection PMOS group 3 (3-1 to 3-8) are connected in series from four in parallel to eight in parallel, and the data signals A to D are read / write data signals RWD1 to RWD.
8 and the selection signals Ba to Bd become the multiplex signals BMUL1 to BMUL.

Further, the inverter 2 is connected to the common node X _0.
The input of 1 is connected, and the inverter 21 outputs the internal read data signal RDA which is an output signal. In FIG. 15, reference numeral VD indicates a high potential power source (potential VDD in this embodiment) in the integrated circuit, and reference numeral VS.
(Ground potential GND in this embodiment) indicates a low potential power supply in the integrated circuit.

The inversion signal multiplex circuit 20 has the same structure as the positive phase signal multiplex circuit 19.
However, the read / write data signals RWD1 to RWD8 are the inverted read / write data signals BRWD1 to BRWD8 because they are for the reverse phase signals.

In the circuit elements of the multiplex circuit 20 for the reverse phase signal, the PMO for transmitting the data signal is provided.
Reference numbers 2'-1 to 2'-8 are assigned to the S group and PMO for output selection
Reference numbers 3'-1 to 3'-8 are assigned to the S group and the common node BX ₀
Reference numeral 4'is provided for the NMOS for precharging
Further, the reference numeral 21 ′ is attached to the inverter having the input connected to the common node to correspond to the circuit element of the positive-phase signal multiplex circuit 19, and the description thereof will be omitted.

FIG. 16 is a circuit diagram of the multiplex circuit 18 included in the second multiplex stage 402. The multiplex circuit 18 includes multiplex circuits 17-1 to 17-1.
Similarly to -4, it includes a multiplex circuit 22 for a positive phase signal and a multiplex circuit 23 for an inverted signal. The multiplex circuit 22 uses the internal read data lines RDA to RD.
Four of D are integrated into one read data line DA. The multiplex circuit 23 uses the inverted internal read data line BR.
Four of DA to BRDD are integrated into one inverted internal read data line BRD.

The positive phase signal multiplex circuit 22 has the same structure as that of the apparatus shown in FIGS. Especially, the difference is that the data signal transmission PMOS group 2 (2-9 to 2
-12) to the internal read data signals RDA to R
Point to which DD is supplied, and output selection PMOS group 3
(3-9 to 3-12) multiplex signals BMULA to B
This is the point at which MULD is supplied.

Further, the inverter 2 is connected to the common node X _1.
4 inputs are connected, and this inverter 24 outputs a read data signal RD which is an output signal. The inversion signal multiplex circuit 23 also has the same configuration as the in-phase signal multiplex circuit 22. However, since it is for the reverse phase signal, the inverted internal read data signals BRDA to BRDD are supplied to the gates of the data signal transmitting PMOSs 2-9 to 2-12.

In the circuit elements of the multiplex circuit 23 for the reverse phase signal, the PMO for transmitting the data signal is provided.
Reference numbers 2'-9 to 2'-12 are assigned to the S group and PM for output selection
Reference numbers 3'-9 to 3'-12 are assigned to the OS group and the common node B
Reference numeral 4 is provided for the NMOS for precharging X _1.
By adding reference numeral 24 'to the inverter having the input connected to the common node, reference numeral 24' is made to correspond to the circuit element of the positive-phase signal multiplex circuit 22, and the description thereof will be omitted.

In the read multiplexer, the multiplex circuit is divided into a plurality of stages. When the multiplex circuit is divided into a plurality of stages in this way, 32 pairs of read / write data lines RWD are formed by one stage of the multiplex circuit.
The parasitic capacitance added to the read data line pair RD can be further reduced as compared with the case of selecting even one read data line pair RD.

The output signal lines of the multiplex circuits 17-1 to 17-4 included in the first multiplex stage 400,
That is, a total of four output buffers are provided, one for each of the four read data line pairs RDA to RDD. Then, the multiplex circuit 18 included in the second multiplex stage 402 is made inactive so that one pair of read data line pairs and one output buffer are connected. With this configuration,
A DRAM having a × 4 bit structure can be obtained in place of the DRAM having a × 1 bit structure.

Such a change in the number of output bits is changed to DR.
If the switching function added to the AM chip, or the wiring pattern is changed, from one DRAM chip,
It is possible to obtain a DRAM having either a 1-bit configuration or a x4-bit configuration.

The structure in which the multiplex circuit is divided into a plurality of stages can reduce the parasitic capacitance and can select either the × 1 bit structure or the × 4 bit structure.
This is suitable for the present invention because AM can be easily obtained.

FIG. 17 shows a DR in which the number of output bits can be changed.
It is a block diagram of a read multiplexer of AM. Figure 1
As shown in FIG. 7, a switch circuit group 450 is provided in the read data line pair RDA to RDD that connects the first multiplex stage 400 and the second multiplex stage 402 to each other. The switch circuit group 450 includes switch circuits 451-1 to 451 provided one for each read data line pair.
-4 is included. The switch circuits 451-1 to 451-4 connect the read data line pairs RDA to RDD to the second multiplex stage 4
02 and the output buffer group 452, and is connected. This switching is a switching signal x 4
It is performed based on the potential level of. Output buffer group 452
Includes four output buffers 453-1 to 453-4 corresponding to four read data line pairs RDA to RDD. Output buffer 453-1 is used in both the x1 bit configuration and the x4 bit configuration.
Therefore, it is connected to the read data line pair RD and the switch circuit 451-1 via the switch circuit 454. The switch circuit 454 is also the switch circuits 451-1 to 4-4.
The same switching as 51-4 is performed. This switching is also performed based on the potential level of the switching signal × 4. The other output buffers 453-2 to 453-4 are used only in the x4 bit configuration.

Further, the multiplexed signals BMULA-B
MULD and the precharge signal PRCH are supplied to the second multiplex stage 40 via the signal deactivating circuit 455.
2 is input to the multiplex circuit 18. The signal deactivating circuit 455 includes OR gate circuits 456-1 to 456-4 and an AND gate circuit 45, which are provided one for each signal line.
Including 6-5. The signals BMULA to BMULD are input to one input of each of the OR gate circuits 456-1 to 456-4, and the switching signal B × 4 is input to each of the other inputs.
Is entered. The signal PRCH is input to one input of the AND gate circuit 456-5, and the switching signal x4 is input to each of the other inputs.

When the switching signal × 4 is at high level,
The outputs of the OR gate circuits 456-1 to 456-4 and the AND gate circuit 456-5 are signals BMULA to BM, respectively.
It changes according to the potential levels of ULD and PRCH. Therefore, the multiplex circuit 18 becomes active.

When the switching signal x4 is at the low level, the outputs of the OR gate circuits 456-1 to 456-4 are fixed at the high level and the output of the AND gate circuit 456-5 is fixed at the low level. Therefore, the multiplex circuit 1
8 is inactive.

FIG. 18 is a circuit diagram of the switch circuit shown in FIG. In FIG. 18, in particular, the switch circuit 451-1,
A circuit diagram of the switch circuit 454 is shown. As shown in FIG. 18, the switch circuit 451-1 includes four Cs.
MOS type transfer gate circuit 470-1 to 470-4
including. Switching signal x4 is P of the gate circuit 470-1.
The signals are input to the MOS gate, the PMOS gate of the gate circuit 470-2, the NMOS gate of the gate circuit 470-3, and the NMOS gate of the gate circuit 470-4, respectively.
Further, the inversion switching signal B × 4 is applied to the gate circuit 470-1.
To the gate of the NMOS, the gate of the gate of the gate circuit 470-2, the gate of the PMOS of the gate circuit 470-3, and the gate of the PMOS of the gate circuit 470-4.

With such a switch circuit 451-1, when the switching signal × 4 is at a high level, the gate circuit 4
70-3 and gate circuit 470-4 turn on, and gate circuit 470-1 and gate circuit 470-2 turn off. Therefore, the read data lines RDA and BRDA are connected to the multiplex circuit 18.

When the switching signal x4 is at the low level, the gate circuits 470-1 and 470-2 are turned on and the gate circuits 470-3 and 470-4 are turned off. Therefore, the read data lines RDA and BR
DA is connected to the switch circuit 454.

The switch circuit 454 includes four CMOS type transfer gate circuits 471-1 to 471-4.
The switching signal × 4 is obtained by using the PMOS gate of the gate circuit 471-1, the PMOS gate of the gate circuit 471-2, the NMOS gate of the gate circuit 471-3, and the gate circuit 471.
-4 is input to the NMOS gate. Further, the inverted switching signal B × 4 is the NMO of the gate circuit 471-1.
The gate of S, the gate of the NMOS of the gate circuit 471-2,
Gate of PMOS of gate circuit 471-3, gate circuit 4
71-4 are input to the PMOS gates, respectively.

With such a switch circuit 454,
When the switching signal × 4 is at high level, the gate circuit 471
-3 and the gate circuit 471-4 turn on, and the gate circuit 47
1-1 and the gate circuit 471-2 are turned off. For this reason,
The read data lines RD and BRD are connected to the output buffer 45.
It is connected to 3-1.

When the switching signal x4 is at the low level, the gate circuits 471-1 and 471-2 are turned on, and the gate circuits 471-3 and 471-4 are turned off. Therefore, the read data lines RDA and BRDA via the switch circuit 451-1 are connected to the output buffer 4
53-1 is connected.

The circuits of the other switch circuits 451-2 to 451-4 are almost the same as the circuit of the switch circuit 451-1.
The different part is that it is directly connected to the output buffers 453-2 to 453-4 without passing through the switch 454.
Therefore, the illustration of the circuits of the switch circuits 451-2 to 451-4 will be omitted.

As described above, in the DRAM having the read multiplexer shown in FIGS. 17 and 18, by setting the switching signal x4 to the high level, the DRAM becomes x1.
It is possible to have a bit configuration, and conversely, by setting the switching signal x4 to a low level, the DRAM can have a x4 bit configuration.

Next, the normal read operation by the read multiplexer will be described. In addition, this explanation is
A case where the DRAM has a × 1 bit configuration will be taken as an example.
19 and 20 are operation waveform diagrams showing the operation of the read multiplexer 11, respectively.

As shown in FIG. 19, the read / write data line pairs RWD1 to RWD8 are initially at the high (H) level. Read / write data line pairs RWD1 to RWD8
This is because all of them are previously charged to the high potential VCC by the DQ buffer shown in FIG. Further, the precharge signal PRCH for precharging the read multiplexer 11 is at high level. In the multiplex signals BMUL1 to BMUL8, only the multiplex signal BMUL2 has a low (L) level, and the other signals have a high level.

From such a state, the precharge signal P
Transition RCH from high to low. This activates the read multiplexer 11. continue,
Data from the memory cell is read to the read / write data line pairs RWD1 to RWD8. Then, the potential of only one of the line pairs drops to a low level. For example, in FIG. 19, the read / write data line pair RWD1 remains at the high level, and its inverted read / write data line pair BRWD1.
Only falls to a low level. In the read / write data line pair RWD2, the potential drops to a low level,
The inverted read / write data line pair BRWD2 remains at the high level.

As described above, the read / write data line pair RWD
When the potential difference appears in the data signal, the data signal is read to the read / write data line pair RWD. When the data signal is read to the read / write data line pair RWD, the data signal is input to the multiplex circuits 17-1 to 17-4 of the first multiplex stage 400 of the read multiplexer 11. Now, focusing on only two pairs of read / write data line pairs RWD1 and RWD2, the PMOS of the multiplex circuit 17-1 shown in FIG. 15 will be described.
2-1 cuts off the data signal RWD1 because it is at a high level, while PMOS 2'-1 turns on because the data signal BRWD1 is at a low level. Also, the PMOS 2-2 is
Since the data signal RWD2 is at the low level, it conducts, and on the contrary, the PMOS 2'-2 shuts off because the data signal BRWD1 is at the high level. Also, the multiplex circuit 17-1
Contains the multiplex signal B for the first multiplex stage.
MUL1 to BMUL8 are input. Here, focusing on only the multiplex signals BMUL1 and BMUL2, the description will be given with the PMOS 3-1 and 3'-1 as the signal BMUL.
Since 1 is high level, it shuts off, and on the contrary, PMOS 3-2 and 3'-2 are conductive because the signal BRWD2 is low level. Therefore, only one pair of RWD2 is selected from the eight pairs of read / write data line pairs RWD, and this one pair is electrically connected to the internal read data line pair RDA.

The data of the read / write data line pair RWD2 depends on whether the common node X ₀ or BX ₀ is charged.
It is transmitted to the internal read data line pair RDA. In the case shown in FIG. 19, since the read / write data line RWD2 is at a low level and the inverted read / write data line BRWD2 is at a high level, the common node X ₀ is charged to a high level and the common node BX ₀ is at a low level. There is. The potentials of these common nodes X ₀ and BX ₀ are input to the inverters 21 and 21 ', respectively. Since only the inverter 21 inverts the potential of the output signal, only the internal read data line RDA falls to the low level and the potential of the inverted internal read data line BRDA remains at the high level, as shown in FIG.

Such an operation is also performed in parallel in the other three multiplexing circuits 17-2 to 17-4, and a potential difference appears between the internal read data line pairs RDA to RDD. Then, the data signal is transferred to the internal read data line pair RD.
This means that A to RDD have been read.

The data signal is the internal read data line pair RD.
When A to RDD are read, the data is input to the multiplex circuit 18 of the second multiplex stage 402 of the read multiplexer 11. In addition, the multiplex signals BMULA to BMULD for the second multiplex stage are input to the multiplex circuit 18. As shown in FIG. 20, multiplex signals BMULA-BMU
Of the MULD, only the signal BMULA has a low level, and the other signals have a high level. That is, the PMOS3 shown in FIG.
-9 and 3'-9 are conducting respectively, other output selection PM
All OS groups 3 are shut off. Therefore, only one pair of RDA is selected from the four pairs of internal read data lines, and this one pair is electrically connected to the read data line pair RD.

The data of the internal read data line pair RDA is
It is transmitted to the read data line pair RD depending on which _one of the common nodes X ₁ and BX ₁ is charged. In the case shown in FIG. 20, since the internal read data line RDA is at the low level and the inverted internal read data line BRDA is at the high level, the common node X ₁ is charged to the high level and the common node BX ₁ is at the low level. There is. The potentials of these common nodes X ₁ and BX ₁ are input to the inverters 24 and 24 ′, respectively.
Since only the inverter 24 inverts the potential of the output signal, only the read data line RD falls to the low level and the other read data line BRD remains at the high level as shown in FIG.

In this way, the potential difference appears on the read data line pair RD, so that the data signal is transmitted to the read data line pair R.
Read up to D. The data signal read to the read data line pair RD is input to the output buffer.

When the DRAM has a × 4 bit structure, the second multiplex stage 402 does not operate, and the signals read from the internal read data line pair RDA to RDD are directly output from the first multiplex stage 400. Input to the output buffer.

Next, the test circuit will be described. First, as shown in FIG. 7, the test circuit (TC) is arranged between the read multiplexer & write multiplexer and the output buffer. Furthermore, a test circuit (T.
A selection circuit (SC) is arranged between C) and the output buffer. The selection circuit (SC) electrically connects the read data line RD and the inverted read data line BRD directly to the input of the output buffer during the normal read operation. On the other hand, during the test read operation, the read data line RD and the inverted read data line BRD are input to the test circuit (TC), and the test circuit (T.C.
The output result showing the test result in C) is electrically connected to the input of the output buffer.

FIG. 21 is a circuit diagram of the test circuit shown in FIG. As shown in FIG. 21, a test circuit (TC)
Is a two-input NAND gate 25 to which the read data line RD and the inverted read data line BRD are input,
A two-input NOR gate 26 to which the read data line RD and the inverted read data line BRD are respectively input, and a NAN.
It includes an XOR (exclusive OR) gate 27 to which the output of the D gate 25 and the output of the NOR gate 26 are respectively input.

The output of the XOR gate 27 is connected to the test read data line TRD and the inverter 2
After that, it is connected to the inverted test read data line BTRD.

FIG. 22 is a circuit diagram of the selection circuit shown in FIG. 22, the selection circuit (SC) includes a CMOS type transfer gate 29 to which the read data line RD is connected to the input and a CMOS type transfer gate to which the inverted read data line BRD is connected to the input. 29 '
And the test read data line TRD is connected to the input C
It includes a MOS type transfer gate 30 and a CMOS type transfer gate 30 'to which the inverted test read data line BTRD is connected to the input.

The test signal TEST is input to the PMOS gate of the transfer gate 29 and the PMOS gate of the transfer gate 29 ', and the NMOS gate and the transfer gate 29' of the transfer gate 29 are input.
Inversion test signal BTES is applied to the NMOS gate of
T is input. In addition, PM of the transfer gate 30
The inverted test signal BTEST is input to the OS gate and the PMOS gate of the transfer gate 30 ',
The test signal TEST is input to the NMOS gate of the transfer gate 30 and the NMOS gate of the transfer gate 30 '. The transfer gates 29 and 29 'are in the normal operation, that is, the test signal TEST.
Is conductive only when is low level. Further, the transfer gates 30 and 30 'conduct only during a test operation, that is, when the test signal TEST is at a high level. Therefore, the selection circuit electrically connects the read data line pair RD to the output line pair OUT during the normal operation, while electrically connecting the test read data line pair TRD to the output line pair OUT during the test operation. Connecting.

Next, the operation in the test mode will be described. At the time of test read, data signals are simultaneously read out from all 32 read / write data line pairs RWD (hereinafter, referred to as 32-bit data signal). Thereafter, the 32-bit data signal is input to the multiplex circuits 17-1 to 17-4 of the first multiplex stage 400, where the first OR operation is performed and further OR operation is performed. The obtained data signal is input to the logical sum operation in the multiplex circuit 18 of the second multiplex stage 402, and the second logical sum operation is performed here. As shown in FIG. 13, in the test mode, the TEST signal is set to a high level and 12 multiplexed signals BMUL1 to BMUL are set.
This is because all of 8 and BMULA to BMULD are set to a low level (full selection state). The data signal subjected to the second OR operation is read out to the read data line pair RD.

At the time of test read, the same data is written in a plurality of memory cells. Then, the data is read from the plurality of memory cells at the same time. Therefore, it is correct that the 32-bit data signals read from the memory cells are all the same.

If all 32-bit data signals read from the memory cells have no error, the potential of the read data line RD and the potential of the inverted read data line BRD are
One will always be high and the other will be low.

This phenomenon will be briefly described. FIG. 23 is a diagram schematically showing an operating state of the multiplex circuit 17-1 shown in FIG. Since the 8-bit data signal is shown in FIG. 15, the 8-bit data signal is shown in FIG. If all the 8-bit data signals are the same, as shown in FIG.
When all 2-1 to 2-8 are turned off, PMOS 2'-1 to 2 '
-8 turns on all. This phenomenon similarly occurs in the other multiplex circuits 17-2 to 17-4. Therefore, the potentials of the internal read data lines RDA to RDD are all at the high level, and the potentials of the inverted internal read data lines BRDA to BRDD are all at the low level. This indicates that the input data signals of the multiplex circuit 18 are all the same. Therefore, one of the potential of the read data line RD and the potential of the inverted read data line BRD is high level and the other is low level.

When the data signal after such an OR operation is input to the test circuit (TC) shown in FIG. 21, the NAND gate 25 outputs a high level signal,
The NOR gate 26 outputs a low level signal. Therefore, a high level signal and a low level signal are input to the XOR gate 27, and the XOR gate 27 outputs a high level signal. Therefore, the test read data line T
RD potential is high level, inverted test read data line BT
The potential of RD becomes low level. This means that the tested data signal has been read to the test read data line pair TRD. The data signal after being tested is
It is input to the output buffer via the selection circuit (SC). Thereafter, for example, "H" data is output from the output pad (not shown) connected to the output of the output buffer.

On the other hand, if there is at least one error in the 32-bit data signal read from the memory cell, both the read data line RD and the inverted read data line BRD will be at the low level.

This phenomenon will be briefly described. FIG. 24 is a diagram schematically showing the operating state of the multiplex circuit 17-1 shown in FIG. 15, similar to FIG. It is assumed that one of the 8-bit data signals has an error and only the PMOS 2-4 is turned on. Then, a current flows here, and the common node X ₀ is charged to a high level. Therefore, the potential of the internal read data line RDA becomes low level. The inverted internal read data line BRDA is naturally at the low level. This is the input data signal RDA ~ of the multiplex circuit 18.
One of RDD and BRDA to BRDD indicates an error. The PMOS of the multiplex circuit 18 to which the error input data signal is input is the PMOS shown in FIG.
It turns on like 2-4. Therefore, the potential of the read data line RD and the potential of the inverted read data line BRD both become low level.

When the data signal after the logical sum operation is input to the test circuit (TC) shown in FIG. 21, the NAND gate 25 outputs a high level signal, but the NOR gate 26 outputs a low level signal. Instead of the level, a high level signal is output. Therefore, the XOR gate 2
A high-level signal and a high-level signal are input to 7, and the XOR gate 27 outputs a low-level signal. Therefore, the potential of the test read data line TRD is low level contrary to the above, and the inverted test read data line B
Contrary to the above, TRD also becomes high level. Therefore, for example, "L" data is output from the output pad (not shown), contrary to the above.

As described above, in the integrated circuit device according to the present invention, if all of the multiplexed signals are selected and all the input data signals are input, the logical sum operation of the input data signals can be performed. Using the function of this logical sum operation, D
If a test circuit for RAM is made, the test circuit can be simplified.

Next, the write multiplexer will be described. FIG. 25 is a block diagram of the write multiplexer shown in FIG. As shown in FIG. 25, the write multiplexer 12 outputs 1 to 32 pairs of read / write data lines.
Read / write data line pair selection circuit 31 provided one by one
including. Since the DRAM according to this embodiment has 32 pairs of read / write data line pairs RWD1 to RWD32,
The total number of the selection circuits 31 is 32, which is the selection circuits 31-1 to 31-32.

The 32 selection circuits 31 drive the read / write data line pairs, respectively, and the read / write data line pair driving circuits 35 (35-1 to 35-32).
And one of the 32 driving circuits 35-1 to 35-32 are connected to multiplex signals BMUL1 to BMUL8 and BM.
Driving circuit activating circuit (AC) 32 (32-1 to 3-3) for selecting and activating based on ULA to BMULD
2-32) and. The selection circuits 32-1 to 32-32 are provided one by one in the driving circuits 35-1 to 35-32.

Each of the 32 driving circuits 35 has an inverter 36 whose input end is connected to the write data line WD and whose output end is connected to the read / write data line RWD.
(36-1 to 36-32), the input end is connected to the inverted write data line BWD, and the output end is inverted read / write data line BWD.
Inverter 37 (37-1 to 37-32) connected to RWD
Including and The inverter 36 includes an activation circuit (AC) 3
The signal is output to the read / write data line RWD only when the output signal φ of 2 and its inverted signal Bφ are input. Similarly, the inverter 37 also has an activation circuit (AC) 3
The signal is output to the inverted read / write data line BRWD only when the output signal φ of 2 and its inverted signal Bφ are input.

FIG. 26 is a circuit diagram of the selection circuit shown in FIG. FIG. 26 particularly shows the selection circuit 31-1. As shown in FIG. 26, the activation circuit 32-1 includes a three-input type OR gate 33 and a two-input type NAND gate 34.
Including and The OR gate 33 supplies the multiplexed signal B
MUL1, BMULA, and the write timing signal WRT are input respectively. The NAND gate 34 has an output of the OR gate 33 and an inverted test signal BT.
Each EST is input. NAND gate 34 is
The output signal φ of the activation circuit 32-1 is output.

In the normal mode, the inverted test signal TES
T is at a high level. Therefore, the activation circuit 32
From -1, the output signal of the OR gate 33 is output from the output terminal of the NAND gate 34 with its potential level inverted. That is, the potential level of the output signal φ of the activation circuit 32-1 is determined by the potential level of the output of the OR gate 33.

On the other hand, in the test mode, the inverted test signal T
EST goes low. Therefore, the NAND gate 3
4 always makes its output high level regardless of the output level of the OR gate 33. That is, the gate circuit 32-1 has the same function as the gate circuits 14-1 to 14-12 that output the multiplex signal shown in FIG.

The other activation circuits 32-2 to 32-32 are similar to the activation circuits 32-2 to 32-32, except that the input multiplex signals are different. Next, the write operation will be described.

At the time of normal write, the activation circuit 32-1
Any one of .about.32-32 outputs a high level electric potential to activate one of the driving circuits 35-1.about.35-32. As a result, the pair of write data line pairs WD is electrically connected to the pair of read / write data line pairs RWD. Then, the data signal input from the outside of the chip is input to the selected pair of read / write data line pair RWD. Thereafter, the input data signal is input to the data line pair DQ via a DQ buffer (not shown) for writing, and the bit line pair B via the DQ gate.
Input to L. In this way, the data is written in the memory cell selected for writing.

At the time of test write, the activation circuit 3
2-1 to 32-32 all output a high level potential, and activate all of the driving circuits 35-1 to 35-32. As a result, the pair of write data line pairs WD is electrically connected to all the read / write data line pairs RWD.
Then, the data signal input from the outside of the chip is input to all the read / write data line pairs RWD. Thereafter, the input data signal is used for writing, and is not shown in DQ.
It is input to 32 pairs of data line DQ via the buffer,
It is input to 32 pairs of bit lines BL via the DQ gate. In this way, the same data is simultaneously written in all the memory cells selected for writing.

Next, 64 according to the third embodiment of the present invention
The megabit DRAM will be described. 27 is a schematic block diagram of a DRAM according to a third embodiment of the present invention, and FIG. 28 is a block diagram showing in more detail one of the 16-megabit cell arrays shown in FIG.

The DRAM according to the third embodiment is basically the same as the DRAM according to the first embodiment. The difference is that in the DRAM according to the third embodiment, five pairs of column addresses (A8C to A12C, BA8C to BA12C) are input to the cell array and the DQ buffer, and the test signal TEST is input to the DQ buffer. That is what I did. In this case, for example, four column addresses A1
4 using 1C, A12C, BA11C, BA12C
Group read / write data line pair group RWD1
RWD8, RWD9 to RWD16, RWD17 to RWD
24, RWD25 to RWD32, one group is selected. Remaining 6 column addresses A8C to A10C, B
Using A8C to BA10C, one pair is selected from the eight pairs of read / write data line pairs RWD.

By thus selecting the read / write data line pair, in the DRAM according to the third embodiment, one D of 32 DQ buffers is read at the time of reading.
Only the Q buffer can be operated and the remaining 31 DQ buffers can be disabled. A potential difference occurs between the read / write data line RWD connected to the selected one DQ buffer and the inverted read / write data line BRWD according to the data signal read from the memory cell.
On the other hand, both the read / write data line RWD and the inverted read / write data line BRWD connected to the 31 DQ buffers not selected maintain the high level.

In this manner, the column address is input to the cell array and the DQ buffer, and the 32 pairs of read / write data line pairs RWD to 1 pair of read / write data line pairs R.
By selecting WD, it is not necessary to input the multiplex signal BMUL to the multiplex circuit.

FIG. 29 is a circuit diagram of the multiplex circuit of the first multiplex stage included in the DRAM according to the third embodiment, and FIG. 30 is the second multiplex included in the DRAM according to the third embodiment. It is a circuit diagram of a multiplex circuit of a stage.

As shown in FIGS. 29 and 30, the multiplex circuit includes only the PMOS2 (or PMOS2 ') to which the read / write data line RWD is input. These PMOSs 2 are connected in parallel between the power supply terminal VS and the common node X ₀ (or the common node X ₁ ).

With this structure, the scale of the multiplex circuit can be reduced, and the speed of selecting the data signal can be increased. In the DRAM according to the third embodiment, the logical sum operation in the test mode can be performed as in the second embodiment. That is, in the test mode, by operating 32 DQ buffers at the same time, data can be output to all 32 pairs of read / write data lines RWD. Therefore, the logical sum operation is possible.

The write operation of the DRAM according to the third embodiment is the same as that of the second embodiment, and the configuration of the write multiplexer 12 is the same. The second and third
The following effects can be obtained from the DRAM according to the embodiment.

First, similarly to the first embodiment, an integrated circuit device which operates similarly to a multiplex circuit can be obtained by simply turning on / off the data signal transmitting PMOS group 2. In this integrated circuit device, the common node X ₀ ,
It is possible to reduce the parasitic capacitance attached to X ₁ , BX ₀ , BX _1, etc.
The data signal can be transmitted from the read / write data line pair RWD to the read data line pair RD at high speed.

The high-speed transmission of the data signal is performed by changing the precharge level of the read / write data line pair RWD to
It can be accelerated further by setting it to the high potential VCC. This is from the following viewpoint. The read / write data line pair RWD is a very long signal line which is generally arranged along the cell array. Moreover, since the read / write data line pair RWD is connected to the transistor of the DQ buffer for reading data, a junction capacitance is also added. Therefore, the read / write data line pair RWD has a very large parasitic capacitance. Therefore, the change in the potential of the read / write data line pair RWD is very gradual. Therefore, in the multiplexers shown in FIGS. 37 and 38, it is difficult to transmit the data signal from the read / write data line pair RWD to the read data line pair RD at high speed.

On the other hand, in the integrated circuit device according to the present invention, the data signal transmitting PMOS group 2 becomes conductive if the gate potential thereof is lowered by VCC- | Vthp (Vthp is the threshold voltage of PMOS 2) |. To do. Therefore, the time from the input of the data signal to the start of charging the common node X can be shortened. Therefore, the time from the input of the data signal to the read / write data line pair RWD to the completion of the charging of the common nodes X ₀ , X ₁ , BX ₀ , BX ₁ can be shortened.

In the integrated circuit device according to the present invention,
Has a logical sum operation function. The OR operation function is useful in the test mode, for example. The DRAM is equipped with a test time reduction mode by parallel reading in the test mode.

In the integrated circuit device according to the present invention, 32 bits corresponding to each cell array are simultaneously tested. At the time of test write, the same data is written in each of these 32 bits. After that, all the data are read in parallel, and if they match, "1" is output, and if they do not match, "0" is output. As a result, the test time can be shortened to 1/32 as compared with the method in which one bit is usually used.

At the time of test read, all of the multiplex signals BMUL1 to BMUL8 and BMULA to BMULD are set to low level. At this time, all the data signals read on the read / write data line pair RWD are transmitted to the read data line pair RD. Moreover, the read data line pair R
The output of D is the result of the logical sum operation of all the data signals read to the read / write data line pair RWD, like the wired OR. That is, if all the 32-bit data match, the matched data is transmitted to the read data line pair RD as in the normal operation mode. If an error occurs and the data do not match. , The potential of the read data line pair RD transits to the high level. In this way, the potential of the read data line pair RD is different between when there is an error and when there is no error. Separately, it can be transmitted to the output circuit.

As described above, D according to the second and third embodiments
The RAM not only has the ability to select data at high speed in the normal operation mode, but also can easily cope with the change in the selection signal input method in the test operation mode without changing the circuit.

The multiplex circuit shown in FIGS. 29 and 30 is an application of the integrated circuit device shown in FIG. FIG. 31 is a circuit diagram of a semiconductor integrated circuit device according to the fourth embodiment of the present invention.

As shown in FIG. 31, the data selection circuit 10
0 includes a plurality of data transmission circuits 500-1 to 500-4. The plurality of data transmission circuits 500 are connected in parallel between the terminal VDD and the common node X. The plurality of data transfer circuits 500 includes input data signals A to D and a selection signal B.
Selection circuit 501 to which a to Bd are input, and selection circuit 5
And the PMOS2 to which the output of 01 is input.

FIG. 32 is a circuit diagram of the selection circuit shown in FIG. In particular, FIG. 32 shows the selection circuit 501-1. The other selection circuits 501-2 to 501-3 are the selection circuit 5
It has the same circuit as 01-1.

As shown in FIG. 32, the selection circuit 501-1.
Includes an NOR gate 502 to which the input data signal A and the selection signal Ba are input, and an inverter 503 whose input is connected to the output of the NOR gate 502. Inverter 5
The signal output by 03 is the output signal of the selection circuit 501-1. The NOR gate 502 changes the potential level of its output signal according to the potential level of the input data signal A when the potential of the selection signal Ba is at a low level. Also,
NOR gate 502 fixes the potential level of its output signal to a low level regardless of the potential level of input data signal A when the potential of selection signal Ba is at a high level. Therefore, the integrated circuit device shown in FIG. 31 transmits the input data signals A to D to the gate of the PMOS 2 when the potentials of the selection signals Ba to Bd are at the low level.
And the same operation as the integrated circuit device shown in FIG. 2 can be performed.

Next explained is a semiconductor integrated circuit device according to the fifth embodiment of the invention. FIG. 33 is a circuit diagram of a semiconductor integrated circuit device according to the fifth embodiment of the present invention.

The device according to the fifth embodiment shown in FIG. 33 has basically the same configuration and operation principle as the device according to the first embodiment, but a small latch circuit 600 is added to the common node X. The points are different.

The common node X has a precharge signal PRC.
When H is cut off and the NMOS 4 for precharge is cut off,
Floating low level. Small latch circuit 6
00 fixes the potential to a low level (ground potential in this embodiment) so that the potential of the common node X does not fluctuate due to noise or the like while the common node X is at a floating low level.

In the integrated circuit device according to the present invention, when the signal selected among the data signals A, B, C and D is at the high level, the common node X is kept at the low level for a long period even after the data signal is transmitted. , Need to keep. Therefore, connecting the small latch circuit 600 to the common node X is useful from the viewpoint of stabilizing the operation and preventing malfunctions such as erroneous reading of data.

The small latch circuit means a weak latch circuit in which the output potential level of the latch circuit 600 is rapidly inverted. That is, PMO
When the potential of the common node X starts to rise due to the conduction of the S group 2 and the PMOS group 3, respectively, this rise is promptly detected and its output potential level is inverted.

By using the weak latch circuit as the latch circuit 600 for fixing the potential of the common node X, when the data is supplied to the common node X, the output potential level can be immediately inverted, so that high-speed data can be obtained. Communication is not impaired.

The latch circuit 600 shown in FIG. 33 has the configuration shown in FIG.
The common node X ₀ and common node BX ₀ shown in FIG. 30, the common node X ₁ and common node BX ₁ shown in FIG. 30, and the common node X shown in FIG.

Next explained is a semiconductor integrated circuit device according to the sixth embodiment of the invention. 34 is a circuit diagram of a semiconductor integrated circuit device according to a sixth embodiment of the present invention.

The integrated circuit device according to the sixth embodiment shown in FIG. 34 is a MOSF of the integrated circuit device shown in FIGS.
The conductivity type of ET is all inverted. Reference numerals 2N-9 to 2N-12 are used for the data signal transmission NMOS group.
, And reference symbols 3P-9 to 3P-1 for the output selection PMOS group.
PM for precharging 2 to common node BX ₁
A reference numeral 4P is attached to the OS to make it correspond to the integrated circuit device shown in FIGS. 1 and 2, and the description thereof will be omitted.

The operation principle of the device according to the sixth embodiment and the advantage of the device are the same as those of the first embodiment. FIG. 35 is an operation waveform diagram showing an operation of the device according to the sixth embodiment.

Next explained is a semiconductor integrated circuit device according to the seventh embodiment of the invention. FIG. 36 is a circuit diagram of a semiconductor integrated circuit device according to the seventh embodiment of the present invention.

The apparatus according to the seventh embodiment shown in FIG. 36 is
The small latch circuit 600 shown in FIG. 33 is added to the common node X of the device shown in FIG. This 7th
The operation principle of the device according to the embodiment and the advantage of the device are the same as those of the first embodiment, and the stabilization of the operation obtained by the device according to the fifth embodiment shown in FIG. 33, In addition, the effect of preventing malfunction can be obtained.

According to the present invention described in the above embodiments, a plurality of data are selected and transmitted to the next stage.
Since the influence of the parasitic capacitance can be reduced and the transmission threshold can be set low, high-speed transmission becomes possible. In particular, as the number of selected data increases, the effect increases.

In a test operation mode such as DRAM, it is possible to judge whether a plurality of pieces of read data match or do not match without changing the normal operation mode selection circuit. There is also an effect that an ideal test circuit in which there is no difference in access time between operation and test operation can be realized.

[0159]

As described above, according to the present invention,
It is possible to provide a semiconductor integrated circuit device capable of performing a high-speed selection operation even when the number of selected data is large.

[Brief description of drawings]

FIG. 1 is a block diagram of a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 3 is an operation waveform diagram of the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 4 is a diagram showing a parasitic capacitance of the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 5 is a diagram showing a parasitic capacitance of a conventional multiplexer.

FIG. 6 is a diagram showing a parasitic capacitance of another conventional multiplexer.

FIG. 7 is a DRAM according to a second embodiment of the present invention.
Block diagram of.

8 is a block diagram of the 16-megabit cell array shown in FIG.

9 is a block diagram of the 256 kilobit cell array shown in FIG.

10 is a circuit diagram of the DQ buffer shown in FIG.

11 is an operation waveform diagram of the DQ buffer shown in FIG.

FIG. 12 is a read multiplexer & shown in FIG.
Block diagram of a write multiplexer.

13 is a circuit diagram of the multiplex signal generation circuit shown in FIG.

14 is a block diagram of the read multiplexer shown in FIG.

15 is a circuit diagram of the multiplex circuit of the first multiplex stage shown in FIG.

16 is a circuit diagram of the multiplex circuit of the second multiplex stage shown in FIG.

FIG. 17 is a DRAM in which the number of output bits can be changed.
Block diagram of a read multiplexer of FIG.

18 is a circuit diagram of the switch circuit shown in FIG.

19 is an operation waveform diagram of the read multiplexer shown in FIG.

20 is an operation waveform diagram of the read multiplexer shown in FIG.

FIG. 21 is a circuit diagram of the test circuit shown in FIG. 7.

22 is a circuit diagram of the selection circuit shown in FIG. 7. FIG.

23 is a diagram showing an operating state of the multiplex circuit shown in FIG.

FIG. 24 is a diagram showing another operation state of the multiplex circuit shown in FIG. 15.

FIG. 25 is a block diagram of the write multiplexer shown in FIG. 12.

26 is a circuit diagram of the selection circuit shown in FIG. 25.

FIG. 27 is a DR according to a third embodiment of the present invention.
Block diagram of AM.

28 is a block diagram of the 16-megabit cell array shown in FIG. 27.

FIG. 29 is a DR according to a third embodiment of the present invention.
The circuit diagram of the multiplex circuit of the first multiplex stage included in the AM.

FIG. 30 is a DR according to a third embodiment of the present invention.
The circuit diagram of the multiplex circuit of the 2nd multiplex stage with which AM is equipped.

FIG. 31 is a circuit diagram of a semiconductor integrated circuit device according to a fourth embodiment of the present invention.

32 is a circuit diagram of the selection circuit shown in FIG. 31. FIG.

FIG. 33 is a circuit diagram of a semiconductor integrated circuit device according to a fifth embodiment of the present invention.

FIG. 34 is a circuit diagram of a semiconductor integrated circuit device according to a sixth embodiment of the present invention.

FIG. 35 is an operation waveform diagram of the semiconductor integrated circuit device according to the sixth embodiment of the present invention.

FIG. 36 is a circuit diagram of a semiconductor integrated circuit device according to a seventh embodiment of the present invention.

FIG. 37 is a circuit diagram of a conventional multiplexer.

FIG. 38 is a circuit diagram of another conventional multiplexer.

[Explanation of symbols]

1 ... Wiring, 2-1 to 2-14, 2'-1 to 2'-14 ... P channel type MOSFET for data transmission, 3-1 to 3-14, 3'-1
~ 3'-14 ... P-channel MOSFET for output selection,
4, 4 '... N-channel type MOSFET for precharge,
10 ... Multiplex signal generating circuit, 11 ... Read multiplexer, 12 ... Write multiplexer, 14-1 to 1
4-12 ... Gate circuit for generating multiplex signal, 17-1
... 17-4 ... Multiplex circuit, 18 ... Multiplex circuit, 19 ... Multiplex circuit for positive phase signal, 20 ... Multiplex circuit for inverted signal, 21, 21 '... Inverter for output, 22 ... Multiple for normal phase signal Plex circuit, 23
... Multiplex circuit for inverted signal, 24, 24 '... Inverter for output, 25 ... NAND gate, 26 ... NOR gate, 27 ... Exclusive OR gate, 28 ... Inverter, 29, 29' ... CMOS type transfer gate, 30, 30 '... CMOS type transfer gate,
31-1 to 31-32 ... Read / write data line pair selection circuit,
32-1 to 32-32 ... Driving circuit activation circuit, 35
-1 to 35-32 ... Read / write data line pair driving circuit, 100, 100 '... Data selection circuit, 102-1 to 1
02-12, 102'-1 to 102'-12 ... Data transmission circuit, 200, 200 '... Precharge circuit, 300 ... D
Q-line equalizer, 302 ... Transmission gate, 304 ... Internal D
Q-line equalizer, 306 ... Sense amplifier, 308 ... RW
D line pair driving circuit, 310 ... RWD line equalizer, 400 ... First multiplex stage, 402 ... Second multiplex stage, 450 ... Switch circuit group, 452 ... Output buffer group, 454 ... Switch circuit, 455 ... Signal inactive Circuit, 500-1 to 500-4 ... Data transmission circuit, 50
1-1 to 501-4 ... Selection circuit, 600 ... Latch circuit.

Claims (24)

[Claims] 1. A first and a second power supply terminal, a first data transmission circuit connected to the first power supply terminal, for receiving a first input data signal and a first selection signal, and A data selection circuit including at least a second data transmission circuit to which a second input data signal and a second selection signal are input; and a precharge connected to the second power supply terminal and to which a precharge signal is input. A semiconductor integrated circuit device comprising: a circuit; and a wiring connected to a common node of the data selection circuit and the precharge circuit. 2. The first data transfer circuit is the first data transfer circuit.
First insulation gate type FET which receives the input data signal of the gate at the gate, and a second insulation gate type FET which receives the first selection signal at the gate and is connected in series with the first insulation gate type FET. A second gate for receiving the second input data signal at the gate of the second data transmission circuit, and a gate for receiving the second selection signal. A fourth insulation gate type FET connected in series with the third insulation gate type FET
The semiconductor integrated circuit device according to claim 1, comprising: 3. The first data transfer circuit comprises:
First selection gate circuit to which the input data signal and the first selection signal are input, and a first insulation gate type FET whose gate receives an output of the first selection gate circuit.
And a second selection gate circuit to which the second input data signal and the second selection signal are input, and an output of the second selection gate circuit. 2. The semiconductor integrated circuit device according to claim 1, further comprising a second insulating gate type FET which receives the gate at the gate. 4. The first selection gate circuit transmits the first input data signal to a gate of a first insulation gate type FET based on the first selection signal, and the second selection gate circuit further comprises: 4. The semiconductor device according to claim 3, wherein the selection gate circuit transmits the second input data signal to the gate of the second insulation gate type FET based on the first selection signal. Integrated circuit device. 5. The first and second data transfer circuits transfer the first and second input data signals to the common node based on the first and second selection signals. The semiconductor integrated circuit device according to claim 1. 6. The first and second data transfer circuits transfer the first and second input data signals to the common node based on the first and second selection signals. The semiconductor integrated circuit device according to claim 2. 7. The first and second insulated gate FETs
5. The semiconductor integrated circuit device according to claim 4, wherein the first and second input data signals transmitted to the gate are transmitted to the common node. 8. The first data transmission circuit is provided with the first
The potential of the selection signal is input as a first level, and the potential of the second selection signal is input to the second data transmission circuit as a second level different from the first level. 6. The semiconductor integrated circuit device according to claim 5, wherein one of the second input data signals is transmitted to the common node. 9. The first and second data transfer circuits are input with the potentials of the first and second selection signals as the same level, and the logical sum of the first and second input data signals is input to the first and second data transfer circuits. 9. The semiconductor integrated circuit device according to claim 5, wherein the signal is transmitted to a common node. 10. The first and second input data signals,
10. The semiconductor integrated circuit device according to claim 5, wherein the common node is precharged by the precharge circuit after being transmitted to the common node. 11. The potential of the first selection signal is input to the first data transmission circuit as a first level, and the potential of the second selection signal is input to the second data transmission circuit. 7. The second level different from the first level is inputted, and either one of the first and second input data signals is transmitted to the common node.
The semiconductor integrated circuit device according to 1. 12. The first and second data transfer circuits,
The potentials of the first and second selection signals are input as the same level, and the logical sum of the first and second input data signals is transmitted to the common node. 7. A semiconductor integrated circuit device according to item 1. 13. The first and second input data signals,
13. The semiconductor integrated circuit device according to claim 6, wherein the common node is precharged by the precharge circuit after being transmitted to the common node. 14. The first insulation gate type FET, the second insulation gate type FET, and the third insulation gate type F.
7. The ET and the fourth insulating gate type FET are P-channel type FETs, respectively.
The semiconductor integrated circuit device according to claim 11, claim 12, or claim 13. 15. The potential of the first selection signal is input to the first selection gate circuit as a first level, and the potential of the second selection signal is input to the second selection gate circuit. Input as a second level different from the first level,
8. The semiconductor integrated circuit device according to claim 7, wherein one of the first and second input data signals is transmitted to the common node. 16. The first and second selection gate circuits are inputted with the potentials of the first and second selection signals as the same level, and a logical sum of the first and second input data signals is obtained. 16. The semiconductor integrated circuit device according to claim 7, wherein the semiconductor integrated circuit device is transmitted to the common node. 17. The first and second input data signals,
17. The semiconductor integrated circuit device according to claim 7, wherein the common node is precharged by the precharge circuit after being transmitted to the common node. 18. The method according to claim 3, wherein each of the first insulation gate type FET and the second insulation gate type FET is a P-channel type. ,
The semiconductor integrated circuit device according to any one of claims 15, 16 and 17. 19. The method according to claim 1, further comprising a potential fixing circuit connected to the common node for fixing the potential of the common node to a predetermined potential. 2. A semiconductor integrated circuit device according to item 1. 20. The semiconductor integrated circuit device according to claim 19, wherein the potential fixing circuit is a latch circuit. 21. A multiplexer including an input buffer, an output buffer, a memory cell array including a plurality of dynamic memory cells, a read multiplexer connected to the output buffer, and a write multiplexer connected to the input buffer. A plurality of read / write data lines electrically connecting the memory cell array and the multiplexer, and a plurality of inversion read / write pairs of the read / write data line electrically connecting the memory cell array and the multiplexer. A semiconductor integrated circuit device comprising: a data line and a multiplex signal generating circuit for generating a plurality of multiplex signals. 22. The read multiplexer comprises a first multiplexer.
A multiplex circuit and a second multiplex circuit, wherein the first multiplex circuit is connected to a first power supply terminal, and receives an input data signal of a first read / write data line and a first read / write data line. First data including at least a first data transmission circuit to which a multiplex signal is input, and a second data transmission circuit to which an input data signal of a second read / write data line and a second multiplex signal are input A selection circuit, a first precharge circuit connected to a second power supply terminal, to which a precharge signal is input, the first data selection circuit, and the first
And a first wire connected to a common node with the precharge circuit of the first multiplex circuit, wherein the second multiplex circuit includes input data of a first inverted read / write data line connected to the first power supply terminal. Third data transfer circuit to which a signal and the first multiplex signal are input, and fourth data transfer to which the input data signal of the second inverted read / write data line and the second multiplex signal are input A second data selection circuit including at least a circuit, a second precharge circuit connected to the second power supply terminal and to which the precharge signal is input, the second data selection circuit, and the second 22. The semiconductor integrated circuit device according to claim 21, further comprising a second wiring connected to a common node with the precharge circuit of FIG. 23. A multiplexer including an input buffer, an output buffer, a memory cell array including a plurality of dynamic memory cells, a read multiplexer connected to the output buffer, and a write multiplexer connected to the input buffer. A plurality of read / write data lines electrically connecting the memory cell array and the multiplexer, and a plurality of inversion read / write pairs of the read / write data line electrically connecting the memory cell array and the multiplexer. A semiconductor integrated circuit device comprising: a data line, a multiplex signal generation circuit for generating a plurality of multiplex signals, and a test circuit connected to a wiring connecting an output buffer and a read multiplexer. 24. The read multiplexer comprises a first multiplexer.
A multiplex circuit and a second multiplex circuit, wherein the first multiplex circuit is connected to a first power supply terminal, and receives an input data signal of a first read / write data line and a first read / write data line. First data including at least a first data transmission circuit to which a multiplex signal is input, and a second data transmission circuit to which an input data signal of a second read / write data line and a second multiplex signal are input A selection circuit, a first precharge circuit connected to a second power supply terminal, to which a precharge signal is input, the first data selection circuit, and the first
And a first wire connected to a common node with the precharge circuit of the first multiplex circuit, wherein the second multiplex circuit includes input data of a first inverted read / write data line connected to the first power supply terminal. Third data transfer circuit to which a signal and the first multiplex signal are input, and fourth data transfer to which the input data signal of the second inverted read / write data line and the second multiplex signal are input A second data selection circuit including at least a circuit, a second precharge circuit connected to the second power supply terminal and to which the precharge signal is input, the second data selection circuit, and the second 24. The semiconductor integrated circuit device according to claim 23, further comprising: a second wiring connected to a common node with the precharge circuit.