JPH07283706A - Switching circuit and switched capacitor circuit - Google Patents

Abstract

PURPOSE:To provide a new switching circuit which is suitable for reduction of the powerc voltage. CONSTITUTION:A switch 11 consists of an NMOS transistor TR. An input signal is supplied to the source of the NMOS TR with a control signal phi applied to the gate respectively. When the signal phi is set at a high potential VDD, the switch 11 is turned on. An analog ground setting means 12 sets the source- drain bias potential, i.e., the reference potential of the input signal at (VSS+ VDD-VthN)/2, where VthN is the threshold voltage of the NMOS TR. A charge extracting means 13 is connected to the drain of the NMOS TR. The means 13 consists of a MOS TR which is turned on and off complementarily to the NMOS TR with its drain kept open.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improvements in a switch circuit and a switched capacitor (hereinafter referred to as "SC") circuit.

[0002]

2. Description of the Related Art FIG. 13 shows a conventional positive phase type switched capacitor filter (hereinafter referred to as "SCF") circuit. One input terminal of the operational amplifier 1 is S
It is connected to the C circuit 2 and the other input terminal is connected to the analog ground. The capacitor C1 is connected between the output terminal of the operational amplifier 1 and one input terminal.

The SC circuit 2 is composed of four switch circuits and one capacitor. Switch circuit SW
1 and SW2 are connected in series between the input terminal of the input signal VIN and the analog ground. Switch circuit SW
3 and SW4 are connected in series between one input terminal of the operational amplifier 1 and the analog ground. Capacitor C
2 is connected between the connection point of the switch circuits SW1 and SW2 and the connection point of the switch circuits SW3 and SW4.

Each of the switch circuits SW1 to SW4 has a P
A CMOS switch circuit including a channel type MOS transistor (hereinafter referred to as “PMOS transistor”) and an N channel type MOS transistor (hereinafter referred to as “NMOS transistor”) is configured.

The control signal φ1 is applied to the switch circuits SW2 and S2.
The control signal / φ1 complementary to the control signal φ1 is input to the gate of the NMOS transistor of W3, and is input to the gate of the PMOS transistor of the switch circuits SW2 and SW3. The control signal φ2 is the switch circuit SW.
The control signal / φ2, which is input to the gates of the NMOS transistors 1 and SW4 and is complementary to the control signal φ2, is input to the gates of the PMOS transistors of the switch circuits SW1 and SW4.

In the above SCF circuit, the operational amplifier 1
And the bias potential (analog ground potential) of the source and drain of each MOS transistor that constitutes the switch circuits SW1 to SW4, that is, the potential that is the reference of the amplitude of the input signal (analog signal) is a high potential (for example, power supply potential). ) V
The potential is set to an intermediate potential (VDD + VSS) / 2 between DD and the low potential (for example, ground potential) VSS.

FIG. 14 shows only one switch circuit which constitutes the SCF circuit. In this switch circuit, the control signal φ1 is applied to the gate of the NMOS transistor N1, and the control signal / φ1 is applied to the gate of the PMOS transistor P1. Further, when the control signal φ1 is at the high potential VDD and the control signal / φ1 is at the low potential VSS, the switch circuit is turned on.

FIG. 15 shows the relationship between the input signal VIN and the ON / OFF state of the MOS transistor when the switch circuit of FIG. 14 is in the ON state (φ1 = VDD, / φ1 = VSS). In addition, analog ground VAGND
Is set to (VDD + VSS) / 2.

In this case, since the NMOS transistor N1 is in the ON state, the gate-source voltage Vgs (n) of the NMOS transistor N1 becomes equal to the threshold voltage V thereof.
must be greater than thN. That is, when the expression (1) is satisfied, the NMOS transistor N1 maintains the ON state. Vgs (n) = VDD−VIN ≧ VthN (1) Similarly, in order for the PMOS transistor P1 to be in the ON state, the gate-source voltage Vgs (p) of the PMOS transistor P1 becomes It must be higher than the threshold voltage VthP. That is, when the formula (2) is satisfied,
The PMOS transistor P1 maintains the ON state. Vgs (p) = VIN−VSS ≧ VthP (2) Therefore, from the above formulas (1) and (2), the range in which both the NMOS transistor N1 and the PMOS transistor P1 are in the ON state is represented by the formula (3). To be done. VSS + VthP ≤ VIN ≤ VDD-VthN (3) From the above equation (3), the following can be understood. The range in which both the NMOS transistor N1 and the PMOS transistor P1 are in the ON state is as the low potential VSS increases.
And the higher the high potential VDD, the narrower it becomes.

Now, assuming that the low potential VSS is the ground potential (constant) and the high potential VDD is the power supply potential, the range in which both the NMOS transistor N1 and the PMOS transistor P1 are in the ON state becomes narrower as the power supply potential is lowered. become.

If the power supply voltage is about 5 V, the NMO
Assuming that the threshold voltage VthN of the S transistor N1 and the threshold voltage VthP of the PMOS transistor P1 are both about 0.8V, the range in which both the MOS transistors N1 and P1 are in the ON state is 0.8 from the formula (3). ≤ VIN
≦ 4.2. Therefore, analog ground level VA
If GND is set to 2.5V, theoretically the input signal VI
When the amplitude of N is 1.7 V or less, the NMOS transistor N1 and the PMOS transistor P1 always maintain the ON state.

However, the power supply voltage is 2 V or less, for example, 1.
In the case of 8V, the threshold voltage VthN of the NMOS transistor N1 and the threshold voltage Vt of the PMOS transistor P1
If hP is about 0.8V, the range in which both the MOS transistors N1 and P1 are in the ON state is
From formula (3), 0.8 ≦ VIN ≦ 1.0. Therefore, even if the analog ground level VAGND is set to 0.9V, the NMOS transistor N1 or the PMOS transistor P1 is turned off when the amplitude of the input signal VIN exceeds 0.1V.

[0013]

As described above, since the conventional switch circuit is composed of the CMOS switch circuit, if the difference between the high potential VDD and the low potential VSS becomes small due to the reduction of the power supply voltage, the NMOS transistor is reduced. There is a drawback that the range in which both the PMOS transistor and the PMOS transistor are on is narrowed. Therefore, if the level of the input signal deviates from the range, the NMOS transistor or the PMO
The S transistor is turned off, and either one of the MO
There is a situation in which the S-transistor temporarily fails.

The present invention has been made to solve the above-mentioned drawbacks, and an object thereof is that even if the difference between the high potential VDD and the low potential VSS becomes small due to the low power supply voltage, the MOS transistor does not function. It is an object of the present invention to provide a novel switch circuit and a switched capacitor circuit that can eliminate the situation and reduce the number of elements.

[0015]

In order to achieve the above object, the switching circuit of the present invention comprises one N-channel type MO
A switch composed of an S-transistor, to which a high potential VDD or a low potential VSS is applied to the gate and an input signal is input to the source, and a bias potential of the source and the drain of the N-channel type MOS transistor. (VSS + VD
D) / 2 and means for setting the predetermined value lower than / 2.

The bias potential of the source and drain of the N-channel MOS transistor is (VSS + VDD-
VthN) / 2. However, VthN is the threshold voltage of the N-channel MOS transistor.

The switch circuit of the present invention comprises one P-channel MOS transistor, a switch to which a high potential VDD or a low potential VSS is applied to the gate, and an input signal is input to the source; The bias potential of the source and drain of the P-channel MOS transistor is set to (VSS
+ VDD) / 2, and means for setting a predetermined value higher than + VDD / 2.

The bias potential of the source and drain of the P-channel MOS transistor is (VSS + VthP
+ VDD) / 2. However, VthP is the threshold voltage of the P-channel MOS transistor.

The switch circuit of the present invention further comprises charge extracting means connected to at least one of the source and the drain of the N or P channel type MOS transistor. This charge extracting means is composed of a dummy MOS transistor whose source is connected to the source or drain of the MOS transistor and whose drain is open. The dummy-MOS transistor is turned on or off complementarily to the MOS transistor.

The switched capacitor circuit of the present invention has a plurality of switches and capacitors, and each switch has
One N-channel type MO in which a control signal is input to the gate
It is composed of an S transistor. Further, there is provided means for setting the source and drain bias potentials of the N-channel MOS transistor to a predetermined value lower than (VSS + VDD) / 2.

The bias potential of the source and drain of the N-channel MOS transistor is (VSS + VDD-
VthN) / 2. However, VthN is the threshold voltage of the N-channel MOS transistor.

The switched capacitor circuit of the present invention has a plurality of switches and capacitors, and each switch has
One P-channel MO with a control signal input to the gate
It is composed of an S transistor. Further, there is provided means for setting the source and drain bias potentials of the P-channel type MOS transistor to a predetermined value higher than (VSS + VDD) / 2.

The bias potential of the source and drain of the P-channel MOS transistor is (VSS + VthP
+ VDD) / 2. However, VthP is the threshold voltage of the P-channel MOS transistor.

The switched capacitor circuit of the present invention further comprises a charge extracting means connected to one of the source and the drain of the MOS transistor, which has a high impedance. The charge extracting means is a source
The MOS transistor is connected to the source or the drain of the MOS transistor, and is composed of a dummy MOS transistor having an open drain.

[0025]

According to the above structure, the switching circuit has one MO.
The bias potential of the source and drain of the MOS transistor, that is, the potential serving as the reference of the input signal, is set to a predetermined value higher or lower than (VSS + VDD) / 2.

Therefore, for example, when the high potential VDD is the power source potential and the low potential VSS is the ground potential, even if the power source potential becomes low, the MOS transistor can function as a switch and the voltage is lowered. It is possible to provide a switch circuit and a switched capacitor circuit having a simple structure suitable for the integrated circuit.

The bias potential of the source and drain of the MOS transistor is (VSS + VDD-VthN).
/ 2 or (VSS + VthP + VDD) / 2 is effective.

Further, since there is a charge extracting means capable of extracting the electric charge of the parasitic capacitance formed in the switch circuit, the jump of the channel electric charge and the clock signal are caused.
It is possible to prevent the potential change due to the drain and improve the characteristics of the switch circuit and the switched capacitor circuit.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The switch circuit of the present invention will be described in detail below with reference to the drawings. FIG. 1 shows the first of the present invention.
The switch circuit according to the embodiment of FIG. This switch circuit includes a switch 11 and an analog ground setting means 1.
2 and a charge extracting means 13.

The switch 11 is composed of an NMOS transistor. The control signal φ is input to the gate of this NMOS transistor. When the control signal φ is at the low potential VSS (for example, ground potential), the switch 11 is in the off state, and when the control signal φ is at the high potential VDD (for example, the power supply potential, about 1.8 V). The switch 11 is on.

The analog ground setting means 12 has a function of setting the analog ground, and is composed of, for example, a resistance division circuit. Traditionally, analog ground has always been
Although it was set to (VSS + VDD) / 2, in the present invention, the analog ground of the input signal VIN is (VSS +
VDD) / 2 is set to a lower potential.

Specifically, the analog ground is set as follows. That is, in order for the NMOS transistor forming the switch 11 to be in the ON state, the potential between the gate and the source of the NMOS transistor must be higher than the threshold value VthN. Therefore, the range of the input signal VIN in which the NMOS transistor is always on when the control signal φ is at the high potential VDD is VSS ≦ VIN ≦ VDD−VthN.

Therefore, the analog ground is (VSS +
A value lower than VDD) / 2, such as VSS and (VDD-
VthN) intermediate potential (VSS + VDD−VthN) /
Set to 2.

According to the above configuration, for example, as shown in FIG. 2, the input signal VIN can always change within a range in which the NMOS transistor forming the switch 11 is in the ON state. Therefore, it is possible to provide a switch circuit having a simple structure suitable for an integrated circuit having a low power supply voltage without impairing the function of the switch 11.

The charge extracting means 13 has a function of extracting charges accumulated in the parasitic capacitance formed in the switch 11. The charge extracting means 13 is, for example, an NMO.
It is composed of a dummy switch composed of an S transistor. In this case, the source of the NMOS transistor is
It is connected to the drain of the switch 11, and the drain is open without being connected to anything. Further, a control signal (eg, a signal obtained by inverting the phase of the clock signal φ) / φ complementary to the control signal φ is the charge extracting means 13.
Is input to the gate of the NMOS transistor constituting the.

As a result, when the switch 11 is in the off state, the charge extracting means 13 extracts the charge accumulated in the parasitic capacitance formed in the switch 11, so that the adverse effect of the charge can be prevented.

FIG. 3 shows a switch circuit according to the second embodiment of the present invention. This switch circuit has a switch 11, an analog ground setting means 12, and a charge extracting means 13.

The switch 11 is composed of a PMOS transistor. The control signal φ'is input to the gate of this PMOS transistor. When the control signal φ ′ is at the low potential VSS (eg, ground potential), the switch 11 is in the ON state, and the control signal φ ′ is at the high potential VD.
When D (for example, the power supply potential is about 1.8 V),
The switch 11 is off.

The analog ground setting means 12 has a function of setting the analog ground, and is constituted by, for example, a resistance division circuit. Traditionally, analog ground has always been
Although it was set to (VSS + VDD) / 2, in the present invention, the analog ground is set to a potential higher than (VSS + VDD) / 2.

Specifically, the analog ground is set as follows. That is, in order for the PMOS transistor forming the switch 11 to be in the ON state, the gate-source potential of the PMOS transistor must be higher than the threshold value VthP. Therefore,
The range of the input signal VIN in which the PMOS transistor is always on when the control signal φ ′ is at the low potential VSS is VSS + VthP ≦ VIN ≦ VDD.

Therefore, the analog ground is (VSS +
A predetermined value higher than VDD) / 2, for example (VSS + Vt
intermediate potential between hP) and VDD (VSS + VthP + VD
D) / 2 is set.

According to the above structure, as shown in FIG. 4, for example, the input signal VIN can always change within a range in which the PMOS transistor forming the switch 11 is in the ON state. Therefore, it is possible to provide a switch circuit having a simple structure suitable for an integrated circuit having a low power supply voltage without impairing the function of the switch 11.

The charge extracting means 13 has a function of extracting charges accumulated in the parasitic capacitance formed in the switch 11. The charge extracting means 13 is, for example, a PMO.
It is composed of a dummy switch composed of an S transistor and is connected to a terminal on the high impedance side of the switch 11.

In this case, the source of the PMOS transistor is connected to the drain of the switch 11, and the drain is open without being connected to anything. Also,
The complementary control signal (for example, a signal obtained by inverting the phase of the clock signal φ ′) / φ ′ to the control signal φ ′ is the gate of the PMOS transistor forming the charge extracting means 13.
Be entered into

As a result, when the switch 11 is in the off state, the charge extracting means 13 extracts the charge accumulated in the parasitic capacitance formed in the switch 11, so that the adverse effect of the charge can be prevented.

5 and 6 show a switch circuit according to the third and fourth embodiments of the present invention. This switch circuit is different from the first and second embodiments only in that the charge extracting means is connected to both the source and drain of the switch 11, and the other configurations are the same.

The switch circuit of FIG. 5 is a modification of the switch circuit of FIG. 1, in which the charge extracting means 13a is connected to the drain of the switch 11 and the charge extracting means 1 is connected.
3b is connected to the source of the switch 11.
The charge extracting means 13a and 13b are both NMOS
It can be constituted by a dummy switch composed of a transistor.

The drain of the NMOS transistor is open without being connected to anything. A control signal (for example, a signal obtained by inverting the phase of the clock signal φ) / φ that is complementary to the control signal φ is input to the gates of the NMOS transistors forming the charge extracting means 13a and 13b.

The switch circuit of FIG. 6 is a modification of the switch circuit of FIG. 3, in which the charge extracting means 13a is connected to the drain of the switch 11 and the charge extracting means 1 is connected.
3b is connected to the source of the switch 11.
The charge extracting means 13a and 13b are both PMOS
It can be constituted by a dummy switch composed of a transistor.

The drain of the PMOS transistor is open without being connected to anything. A control signal (for example, a signal obtained by inverting the phase of the clock signal φ ') / φ' which is complementary to the control signal φ'is input to the gates of the PMOS transistors forming the charge extracting means 13a and 13b. To be done.

FIG. 7 shows the S according to the fifth embodiment of the present invention.
The CF circuit is shown. This SCF circuit has an SC circuit using the switch circuit of FIG. Operational amplifier 1
One input terminal of 4 is connected to the SC circuit 15, and the other input terminal is connected to the analog ground. The capacitor C1 is connected between the output terminal of the operational amplifier 1 and one input terminal.

The SC circuit 15 includes four switches 16-1.
9 and one capacitor C2. The switches 16 and 17 are connected in series between the input terminal of the input signal VIN and the analog ground. Switch 18,
19 is connected in series between one input terminal of the operational amplifier 14 and the analog ground.

The capacitor C2 is connected between the connection point of the switches 16 and 17 and the connection point of the switches 18 and 19. Each of the switches 16 to 19 is composed of an NMOS transistor.

The control signal φ1 is input to the gates of the NMOS transistors forming the switches 17 and 19. Further, the control signal φ2 is N which constitutes the switches 16 and 18.
It is input to the gate of the MOS transistor. Therefore, this SCF circuit is of a reverse phase type.

The analog ground setting means 20 has a function of setting the analog ground. The analog ground is set to a value smaller than (VSS + VDD) / 2, for example, (VSS + VDD-VthN) / 2.

The charge extracting means 21 has a function of extracting charges accumulated in the parasitic capacitance formed in the switch 18. The charge extracting means 21 is composed of a dummy switch composed of, for example, an NMOS transistor, and prevents the charge from flowing to the capacitor C1 when the switch 18 is in the off state.

Therefore, the control signal (for example, the one obtained by inverting the phase of the clock signal φ2) / φ2 complementary to the control signal φ2 is the NMO constituting the charge extracting means 21.
It is input to the gate of the S transistor.

According to the above structure, the input signal VIN can always change within a range in which the NMOS transistors forming the switches 16 to 19 are in the ON state. Therefore,
It is possible to provide an SCF circuit having a simple configuration suitable for an integrated circuit having a low power supply voltage, without hindering the functions of the switches 16 to 19. Further, since the charge extracting means 21 is connected to the terminal having the high impedance, it is possible to suppress the change in the potential of the terminal.

FIG. 8 shows the S according to the sixth embodiment of the present invention.
The CF circuit is shown. This SCF circuit has an SC circuit using the switch circuit of FIG. Operational amplifier 1
One input terminal of 4 is connected to the SC circuit 15, and the other input terminal is connected to the analog ground. The capacitor C1 is connected between the output terminal of the operational amplifier 1 and one input terminal.

The SC circuit 15 includes four switches 16-1.
9 and one capacitor C2. The switches 16 and 17 are connected in series between the input terminal of the input signal VIN and the analog ground. Switch 18,
19 is connected in series between one input terminal of the operational amplifier 14 and the analog ground. Capacitor C2
Is the connection point of the switches 16 and 17 and the switches 18 and 19
It is connected between the connection point and. Each switch 16
.About.19 are composed of PMOS transistors.

The control signal φ1 is input to the gates of the PMOS transistors forming the switches 17 and 19. Further, the control signal φ2 is P which constitutes the switches 16 and 18.
It is input to the gate of the MOS transistor. Therefore, this SCF circuit is of a reverse phase type.

The analog ground setting means 20 has a function of setting the analog ground. The analog ground is set to a value larger than (VSS + VDD) / 2, for example, (VSS + VthP + VDD) / 2.

The charge extracting means 21 has a function of extracting charges stored in the parasitic capacitance formed in the switch 18. The charge extracting means 21 is composed of, for example, a dummy switch composed of a PMOS transistor, and prevents the charge from flowing to the capacitor C1 when the switch 18 is in the off state.

Therefore, the control signal (eg, the signal obtained by inverting the phase of the clock signal φ2) / φ2 complementary to the control signal φ2 is the PMO constituting the charge extracting means 21.
It is input to the gate of the S transistor.

According to the above structure, the input signal VIN can always change within a range in which the PMOS transistors forming the switches 16 to 19 are in the ON state. Therefore,
It is possible to provide an SCF circuit having a simple configuration suitable for an integrated circuit having a low power supply voltage, without hindering the functions of the switches 16 to 19. Further, since the charge extracting means 21 is connected to the terminal having the high impedance, it is possible to suppress the change in the potential of the terminal.

FIG. 9 shows the S according to the seventh embodiment of the present invention.
The CF circuit is shown. This SCF circuit has an SC circuit using the switch circuit of FIG. Capacitor C
1 is connected between the output terminal of the operational amplifier 14 and one input terminal. The other input terminal of the operational amplifier 14 is connected to the analog ground. SC circuit 15
Are connected between one end and the other end of the capacitor C1.

The SC circuit 15 includes four switches 16-1.
9 and one capacitor C2. The switches 16 and 17 are connected in series between one end of the capacitor C1 and the analog ground. Switches 18, 19
Are connected in series between the other end of the capacitor C1 and the analog ground.

The capacitor C2 is connected between the connection point of the switches 16 and 17 and the connection point of the switches 18 and 19. Each of the switches 16 to 19 is composed of an NMOS transistor.

The control signal φ1 is input to the gates of the NMOS transistors forming the switches 17 and 19. Further, the control signal φ2 is N which constitutes the switches 16 and 18.
It is input to the gate of the MOS transistor.

The analog ground setting means 20 has a function of setting the analog ground. The analog ground is set to a value smaller than (VSS + VDD) / 2, for example, (VSS + VDD-VthN) / 2.

The charge extracting means 21 has a function of extracting charges accumulated in the parasitic capacitance formed in the switch 17. The charge extracting means 21 is composed of, for example, a dummy switch composed of an NMOS transistor, and prevents the charge from flowing to the capacitor C1 when the switch 17 is in the off state.

Therefore, the control signal (eg, a signal obtained by inverting the phase of the clock signal φ1) / φ1 complementary to the control signal φ1 is the NMO constituting the charge extracting means 21.
It is input to the gate of the S transistor.

According to the above structure, the input signal VIN can always change within a range in which the NMOS transistors forming the switches 16 to 19 are in the ON state. Therefore,
It is possible to provide an SCF circuit having a simple configuration suitable for an integrated circuit having a low power supply voltage, without hindering the functions of the switches 16 to 19. Further, since the charge extracting means 21 is connected to the terminal having the high impedance, it is possible to suppress the change in the potential of the terminal.

FIG. 10 shows an SCF circuit according to the eighth embodiment of the present invention. This SCF circuit has an SC circuit using the switch circuit of FIG. The capacitor C1 is connected between the output terminal of the operational amplifier 14 and one input terminal. The other input terminal of the operational amplifier 14 is connected to the analog ground. SC circuit 15
Are connected between one end and the other end of the capacitor C1.

The SC circuit 15 includes four switches 16-1.
9 and one capacitor C2. The switches 16 and 17 are connected in series between one end of the capacitor C1 and the analog ground. Switches 18, 19
Are connected in series between the other end of the capacitor C1 and the analog ground.

The capacitor C2 is connected between the connection point of the switches 16 and 17 and the connection point of the switches 18 and 19. Each of the switches 16 to 19 is composed of a PMOS transistor.

The control signal φ1 is input to the gates of the PMOS transistors forming the switches 17 and 19. Further, the control signal φ2 is P which constitutes the switches 16 and 18.
It is input to the gate of the MOS transistor.

The analog ground setting means 20 has a function of setting the analog ground. The analog ground is set to a value larger than (VSS + VDD) / 2, for example, (VSS + VthP + VDD) / 2.

The charge extracting means 21 has a function of extracting charges accumulated in the parasitic capacitance formed in the switch 17. The charge extracting means 21 is composed of a dummy switch composed of, for example, a PMOS transistor, and prevents the charge from flowing to the capacitor C1 when the switch 17 is in the off state.

Therefore, the control signal (eg, the signal obtained by inverting the phase of the clock signal φ1) / φ1 complementary to the control signal φ1 is used as the PMO constituting the charge extracting means 21.
It is input to the gate of the S transistor.

According to the above structure, the input signal VIN can always change within a range in which the PMOS transistors forming the switches 16 to 19 are in the ON state. Therefore,
It is possible to provide an SCF circuit having a simple configuration suitable for an integrated circuit having a low power supply voltage, without hindering the functions of the switches 16 to 19. Further, since the charge extracting means 21 is connected to the terminal having the high impedance, it is possible to suppress the change in the potential of the terminal.

FIG. 11 shows an SCF circuit according to the ninth embodiment of the present invention. This SCF circuit has an SC circuit using the switch circuit of FIG. The capacitor C1 is connected between the output terminal of the operational amplifier 14 and one input terminal. The other input terminal of the operational amplifier 14 is connected to the analog ground. SC circuit 15
Are connected between one end and the other end of the capacitor C1.

The SC circuit 15 includes two switches 18, 1
9 and one capacitor C2. The switches 18 and 19 are connected in series between one input terminal of the operational amplifier 14 and the analog ground.

The capacitor C2 is connected between the analog ground setting means 20 and the connection point of the switches 18 and 19. Each switch 18, 19 is composed of an NMOS transistor.

The control signal φ1 is input to the gate of the NMOS transistor forming the switch 18. The control signal φ2 is input to the gate of the NMOS transistor that forms the switch 19.

The analog ground setting means 20 has a function of setting the analog ground. The analog ground is set to a value smaller than (VSS + VDD) / 2, for example, (VSS + VDD-VthN) / 2.

The charge extracting means 21 has a function of extracting charges accumulated in the parasitic capacitance formed in the switch 18. The charge extracting means 21 is composed of a dummy switch composed of, for example, an NMOS transistor, and prevents the charge from flowing to the capacitor C1 when the switch 18 is in the off state.

Therefore, the control signal (eg, the signal obtained by inverting the phase of the clock signal φ1) / φ1 complementary to the control signal φ1 is the NMO constituting the charge extracting means 21.
It is input to the gate of the S transistor.

According to the above structure, the input signal VIN can always change within a range in which the NMOS transistors forming the switches 18 and 19 are in the ON state. Therefore,
It is possible to provide an SCF circuit having a simple structure suitable for an integrated circuit having a low power supply voltage without impairing the functions of the switches 18 and 19. Further, since the charge extracting means 21 is connected to the terminal having the high impedance, it is possible to suppress the change in the potential of the terminal.

FIG. 12 shows an SCF circuit according to the tenth embodiment of the present invention. This SCF circuit has an SC circuit using the switch circuit of FIG. The capacitor C1 is connected between the output terminal of the operational amplifier 14 and one input terminal. The other input terminal of the operational amplifier 14 is connected to the analog ground. SC circuit 1
5 is connected between one end and the other end of the capacitor C1.

The SC circuit 15 has two switches 18, 1
9 and one capacitor C2. The switches 18 and 19 are connected in series between one input terminal of the operational amplifier 14 and the analog ground.

The capacitor C2 is connected between the analog ground setting means 20 and the connection point of the switches 18 and 19. Each switch 18, 19 is composed of a PMOS transistor.

The control signal φ1 'is input to the gate of the PMOS transistor which constitutes the switch 18. Also,
The control signal φ2 ′ is input to the gate of the PMOS transistor forming the switch 19.

The analog ground setting means 20 has a function of setting the analog ground. The analog ground is set to a value larger than (VSS + VDD) / 2, for example, (VSS + VthP + VDD) / 2.

The charge extracting means 21 has a function of extracting charges accumulated in the parasitic capacitance formed in the switch 18. The charge extracting means 21 is composed of a dummy switch composed of, for example, an NMOS transistor, and prevents the charge from flowing to the capacitor C1 when the switch 18 is in the off state.

Therefore, the complementary control signal (for example, a signal obtained by inverting the phase of the clock signal φ1 ′) / φ1 ′ to the control signal φ1 ′ is supplied to the gate of the NMOS transistor forming the charge extracting means 21. Is entered.

According to the above structure, the input signal VIN can always change within a range in which the PMOS transistors forming the switches 18 and 19 are in the ON state. Therefore,
It is possible to provide an SCF circuit having a simple structure suitable for an integrated circuit having a low power supply voltage without impairing the functions of the switches 18 and 19. Further, since the charge extracting means 21 is connected to the terminal having the high impedance, it is possible to suppress the change in the potential of the terminal.

[0098]

As described above, the switch circuit and the switched capacitor circuit of the present invention have the following effects. The switch circuit is composed of one MOS transistor, and the analog ground is set to a predetermined value other than the intermediate potential between the high potential and the low potential.

Therefore, for example, the high potential is the power supply potential,
When the low potential is the ground potential, the MOS transistor can function as a switch even when the power supply potential becomes low, and a switch circuit and a switched capacitor circuit having a simple structure suitable for a low-voltage integrated circuit are provided. Can be provided.

Moreover, since the means for extracting the charge of the parasitic capacitance formed in the switch circuit is provided, it is possible to prevent the jump of the channel charge and the change of the potential due to the clock feedthrough, and the switch circuit and the switched capacitor. The characteristics of the circuit can be improved.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a switch circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing characteristics of the switch circuit of FIG.

FIG. 3 is a circuit diagram showing a switch circuit according to a second embodiment of the present invention.

FIG. 4 is a diagram showing characteristics of the switch circuit of FIG.

FIG. 5 is a circuit diagram showing a switch circuit according to a third embodiment of the present invention.

FIG. 6 is a circuit diagram showing a switch circuit according to a fourth embodiment of the present invention.

FIG. 7 is a circuit diagram showing an SCF circuit according to a fifth embodiment of the present invention.

FIG. 8 is a circuit diagram showing an SCF circuit according to a sixth embodiment of the present invention.

FIG. 9 is a circuit diagram showing an SCF circuit according to a seventh embodiment of the present invention.

FIG. 10 is a circuit diagram showing an SCF circuit according to an eighth embodiment of the present invention.

FIG. 11 is a circuit diagram showing an SCF circuit according to a ninth embodiment of the present invention.

FIG. 12 is a circuit diagram showing an SCF circuit according to a tenth embodiment of the present invention.

FIG. 13 is a circuit diagram showing a conventional SCF circuit.

FIG. 14 is a circuit diagram showing a conventional switch circuit.

15 is a diagram showing characteristics of the switch circuit of FIG.

[Explanation of symbols]

 11, 16 to 19 ... Switch, 12, 20 ... Analog ground setting means, 13, 13a, 13b, 21 ... Charge extracting means, 14 ... Operational amplifier, 15 ... SC circuit, C1-C3 ... Capacitor.

Claims (10)

[Claims] 1. A low potential VSS or a high potential VDD for a gate, which is composed of one N-channel MOS transistor.
Is applied and an input signal is input to the source, and means for setting the source and drain bias potentials of the N-channel MOS transistor to a predetermined value lower than (VSS + VDD) / 2. A switch circuit, comprising: 2. The bias potential of the source and drain of the N-channel type MOS transistor is (VSS + VDD).
-VthN) / 2 (where VthN is N
The threshold voltage of the channel MOS transistor is used. ) The switch circuit according to claim 1. 3. A high potential VDD or a low potential VSS is formed on the gate, which is composed of one P-channel MOS transistor.
And a means for setting the bias potentials of the source and drain of the P-channel MOS transistor to a predetermined value higher than (VSS + VDD) / 2. A switch circuit, comprising: 4. The source and drain bias potentials of the P-channel MOS transistor are (VSS + Vth).
P + VDD) / 2 (where VthP is P
The threshold voltage of the channel MOS transistor is used. ) The switch circuit according to claim 3. 5. The switch circuit according to claim 1, further comprising a charge extracting means connected to at least one of a source and a drain of the MOS transistor, wherein the charge extracting means is a source. Is the MO
The dummy MOS transistor is connected to the source or the drain of the S-transistor and has an open drain, and the dummy-MOS transistor is the MOS transistor.
A switch circuit which is turned on or off complementarily to a transistor. 6. A switched capacitor circuit composed of a plurality of switches and a capacitor, each switch being composed of one N-channel type MOS transistor to which a control signal is inputted to the gate, and said N-channel MOS transistor. A switched capacitor circuit further comprising means for setting a bias potential of a source and a drain of a channel type MOS transistor to a predetermined value lower than (VSS + VDD) / 2. 7. The bias potential of the source and drain of the N-channel MOS transistor is (VSS + VDD).
-VthN) / 2 (where VthN is N
The threshold voltage of the channel MOS transistor is used. ) The switched capacitor circuit according to claim 6. 8. A switched capacitor circuit composed of a plurality of switches and capacitors, each switch being composed of one P-channel type MOS transistor to which a control signal is inputted to a gate, and said P-channel MOS transistor. A switched capacitor circuit further comprising means for setting a bias potential of a source and a drain of a channel type MOS transistor to a predetermined value higher than (VSS + VDD) / 2. 9. A bias potential of a source and a drain of the P-channel MOS transistor is (VSS + Vth).
P + VDD) / 2 (where VthP is P
The threshold voltage of the channel MOS transistor is used. ) The switched capacitor circuit according to claim 8. 10. The switched capacitor circuit according to claim 6, wherein the source of the MOS transistor is
The device further comprises charge extracting means connected to one of the source and the drain having a high impedance, the source of the charge extracting means is connected to the source or the drain of the MOS transistor, and the drain is connected to the source. A switched-capacitor circuit comprising a dummy-MOS transistor which is a bun.