JPH07281870A - Unit and method for shift arithmetic - Google Patents

Abstract

PURPOSE:To efficiently perform the shift arithmetic of multiple-precision data. CONSTITUTION:The shift arithmetic unit is equipped with a shifter 20 which outputs high-order digit bit data (B), intermediate-order digit bit data (D), and low-order digit bit data (C) by shifting data according to a shift number, a multiplexer 30 which is coupled with the output of the shifter 20 and selects one of the high-order digit bit data (B) and low-order digit bit data (C) according to the shift direction, a register 40 which is coupled with the output of the multiplexer 30 and stores the data selected by the multiplexer 30, a computing element 60 which is coupled with the output of the shifter 20 and the output of the register 40 and outputs its arithmetic result by processing the intermediate-order digit bit data (D) and the data stored in the register 40, and a register group 8 which is coupled with the output of the computing element 60 and stores the arithmetic result.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shift arithmetic unit and a shift arithmetic method, and more particularly, to a shift arithmetic unit and a shift arithmetic unit for executing a multiple precision shift arithmetic using hardware for processing single precision data. Regarding the method.

[0002]

2. Description of the Related Art With the rapid development of digital technology in recent years, there has been a demand for a processor capable of executing sophisticated processing such as digital signal processing at high speed. Some of these processes require high calculation accuracy. For example,
It is said that short-term predictive analysis processing in a CELP (Code Excited Linear Prediction) type speech codec requires a calculation accuracy of about 36 bits. The CELP-based voice codec is one of the voice codecs essential for digital voice communication. However, it is not a good idea to realize high calculation accuracy with hardware.
This is because the circuit scale of the processor becomes large and there are many disadvantages in terms of cost and power consumption. Therefore, there has been developed a method of executing a double-precision operation by combining a plurality of instructions using hardware that processes single-precision data. Double-precision arithmetic includes double-precision addition, double-precision subtraction, and double-precision shift arithmetic.

FIG. 9 shows the configuration of a conventional shift operation device for executing a double precision shift operation using hardware for processing 24-bit data. This shift operation device includes registers 110 and 111 that store the number of shifts, a shifter 120 that shifts 24-bit data (A) according to the number of shifts stored in the register 110 or 111, and 24-bit data (E). An arithmetic unit (AL that performs arithmetic on the 24-bit data (D) output from the shifter 120)
U) 160 and stores the calculation result of the ALU 160 24
It has bit registers 170, 171, and 172.

A method of shifting double-precision data to the left by N bits by using the shift arithmetic unit having the above-mentioned structure will be described below. Here, the double-precision data is the upper 2
It consists of 4-bit data and lower 24-bit data,
N is an integer of 1 or more. It is assumed that the upper data of the double-precision data to be shifted is stored in the register 170, and the lower data of the double-precision data to be shifted is stored in the register 171. In addition, the upper data of the result of the double precision shift operation is the
It is assumed that the lower-order data stored in 0 and the double-precision shift operation result is stored in the register 172.

The processing of the left N-bit double-precision shift operation is
It is executed according to the following procedure. FIG. 10 schematically shows the procedure.

[1] The shift number “N” is stored in the register 110.

[2] The lower data stored in the register 171 is input to the shifter 120 as data (A). The shifter 120 shifts the lower data to the left by N bits. The ALU 160 outputs the output (data (D)) of the shifter 120 as it is (through output). ALU
The output of 160 is stored in the register 172 as lower data.

[3] The shift number "-(2
4-N) "is stored.

[4] The lower data stored in the register 171 is input to the shifter 120 as data (A). The shifter 120 shifts the lower data to the right by (24-N) bits. The ALU 160 outputs the output (data (D)) of the shifter 120 as it is (through output). The output of the ALU 160 is stored in the register 171.

[5] The upper data stored in the register 170 is input to the shifter 120 as data (A). The shifter 120 shifts the upper data to the left by N bits. The data stored in the register 171 is input to the ALU 160 as data (E). ALU160
Performs an OR operation on the output (data (D)) of the shifter 120 and the data (E). ALU160
Is stored in the register 170 as upper data.

[0011]

However, the conventional left N-bit double-precision shift operation requires three shift operations except for the setting of the shift number. As a result, the double precision shift operation requires more operations including the setting of the shift number. On the other hand, other double-precision operations (double-precision addition, double-precision subtraction, etc.) need only be performed twice. Therefore, in general, the double-precision shift operation has a problem that it is extremely inefficient as compared with other double-precision operations.

LD-CELP (Low-Delay CELP) is CE
It is one of the LP-based voice codecs. LD-CEL
P has a characteristic that the delay is small, and has been attracting attention mainly as a corded codec (ISDN or the like). In LD-CELP, the weight of short-term predictive analysis processing is much higher than that of other codecs.
Therefore, in the LD-CELP, a double precision shift operation of about 500,000 times / second is executed. This is VSELP
(Vector Sum Excited Linear Prediction), PSI-S
This is about 25 times the number of double-precision shift operations executed in the voice codec of a portable digital telephone such as an ELP (Pitch Synchronous Innovation CELP). Therefore, in order to realize LD-CELP, it is essential to improve the efficiency of double-precision shift calculation.

An object of the present invention is to provide a shift operation device and a shift operation method which can efficiently perform a shift operation of multiple precision data.

[0014]

The shift arithmetic unit of the present invention shifts data according to the number of shifts,
Shifting means for outputting upper bit data, middle order bit data and lower bit data, and output of the shift means, and selects one of the upper bit data and the lower bit data according to a shift direction. First selecting means and first storing means coupled to the output of the first selecting means for storing data selected by the first selecting means;
Arithmetic means coupled to the output of the shift means and the output of the first storage means, and operating on the middle-order bit data and the data stored in the first storage means to output an operation result; , Second storage means coupled to the output of the arithmetic means for storing the arithmetic result, whereby
The above object is achieved.

The shift operation device further includes second selecting means for receiving further data and selecting one of the further data and the data stored in the first storing means in response to a control signal. It may be provided, and the output of the second selecting means may be input to the calculating means.

The shift means decodes the m 2 ^k- bit shifters (k = 0, 1, ..., M-1), the 2 ^m- bit shifters, and the m shifts to decode the ^m 2 ^k- bit shifters. ^{A k-} bit shifter (k = 0, 1, ..., M-1) and a decoding unit that supplies a control signal indicating whether or not the shift operation is performed to the 2 ^m- bit shifter may be provided. Here, m is an integer of 1 or more.

A part of the output of the 2 ^m-1 bit shifter is
It may be equal to the output of the first selecting means.

The second storage means may include a plurality of registers for respectively storing the operation result portions.

The second storage means may include a plurality of registers for respectively storing the data portions and a plurality of registers for respectively storing the operation result portions.

The shift operation method of the present invention is a shift operation method for performing double-precision shift operation using the first data and the second data, and a) shifts the first data according to the number of shifts. To output the high-order bit data, the middle-order bit data, and the low-order bit data, and b) storing the middle-order bit data output in step a) as a part of the result of the shift operation. , C) selecting one of the upper bit data and the lower bit data output in step a) according to the shift direction, and d) storing the data selected in step c), e) Shifting the second data according to the shift number to output upper bit data, middle bit data, and lower bit data. And-up, and coupling the said data stored in step d) and middle order bit data output in f) step e), g)
Storing the combined data in step f) as part of the result of the shift operation, whereby the above objective is achieved.

The combining in step f) may be accomplished by performing an OR operation on the middle bit data output in step e) and the data stored in step d).

Steps a) to d) are executed in one step in the execution of the program, and steps e) to g) are executed in one step in the execution of the program.

Another shift operation method of the present invention is a shift operation method for performing a multi-precision shift operation using the first data and at least one second data and third data. Shifting the first data in accordance with the number to output upper bit data, middle bit data, and lower bit data; and b) shifting the middle bit data output in step a). Storing as a part of the result of the operation, c) selecting one of the upper bit data and the lower bit data output in step a) according to the shift direction, and d) in step c). Storing the selected data, e) shifting one of the at least one second data according to the shift number, Of the high-order bit data, the middle-order bit data, and the low-order bit data, and f) selecting one of the high-order bit data and the low-order bit data output in step e) according to the shift direction. , G) storing the data selected in step f), and h) combining the middle bit data output in step e) with the data most recently stored in steps d) and g). And i) storing the data combined in step h) as a part of the result of the shift operation, and j) shifting the third data according to the number of shifts to obtain high-order bit data. And outputting middle-order bit data and lower-order bit data, k).
Combining the middle bit data output in step j) with the most recently stored data in step g), and l) combining the data combined in step k) with the portion of the result of the shift operation. And the step of storing as, thereby achieving the above object.

The combination in step h) is to perform an OR operation on the middle bit data output in step e) and the most recently stored data in steps d) and g). May be achieved by

The combining in step k) is accomplished by performing an OR operation on the intermediate bit data output in step j) and the data most recently stored in step g). Good.

Steps a) to d) are executed in one step in the execution of the program, steps e) to i) are executed in one step in the execution of the program, and steps j) to l) are executed. , Is executed in one step in the execution of the program.

The shift calculation method may further include a step of repeating steps e) to i).

[0028]

According to the present invention, when the double-precision data is shifted to the left, the data overflowed from the lower data by the left shift is stored in the register, and the data stored in the register and the upper data are shifted to the left. The result is combined with. Also, when shifting double-precision data to the right,
The right shift causes the data overflowing from the upper data to be stored in the register, and the data stored in the register and the result of right shifting the lower data are combined. In this way, the shift calculation of double-precision data is realized by two shift operations. Similarly, a shift operation of M double precision data can be realized by M shift operations. Here, M is an integer of 3 or more. As a result, the shift calculation of multi-precision data can be efficiently performed.

[0029]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a shift arithmetic unit according to the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of an embodiment of a shift arithmetic unit according to the present invention. The shift operation device shifts the data (A) according to the given shift number,
A shifter 20 that outputs upper bit data (B), lower bit data (C), and middle bit data (D), and an output of the shifter 20 are coupled to the upper bit data (B) and the lower bit according to the shift direction. A multiplexer 30 for selecting one of bit data (C), and a multiplexer 30
Of the shifter 20 and the output of the register 40 and the register 40 for storing the data selected by the multiplexer 30 and the intermediate bit data (D) output from the shifter 20 and the multiplexer 5
An arithmetic unit (A that performs an arithmetic operation on the data selected by 0
LU) 60 and the output of ALU60,
It has a register group 80 for storing the operation result by 0.

In this embodiment, the data (A) to (D) are
Both are 16-bit data. However, the present invention is not limited to the number of bits of data.

The shift number given to the shifter 20 is stored in the register 10. When the shift number stored in the register 10 is a negative number, the shifter 20 shifts the data (A) to the left by the absolute value of the shift number. Register 1
If the shift number stored in 0 is a positive number, the shifter 20
Shifts the data (A) to the right by the number of shifts.

The shifter 20, the multiplexer 30, and the A
A control circuit 90 supplies a control signal to the LU 60 and the register group 80.

The shifter 20 is supplied with a control signal indicating whether it is an arithmetic shift or a logical shift. The shifter 20 performs one of arithmetic shift and logical shift according to the control signal.

A control signal indicating the shift direction is input to the multiplexer 30. When a control signal indicating that the shift direction is left is input, the multiplexer 3
0 selects the upper bit data (B) output from the shifter 20. When a control signal indicating that the shift direction is right is input, the multiplexer 30
The lower bit data (C) output from the shifter 20 is selected. The shift direction can be determined by referring to the most significant bit of the shift number stored in the register 10. Therefore, the operation of the multiplexer 30 may be controlled according to the value of the most significant bit of the shift number.

The ALU 60 executes various arithmetic operations or logical operations according to control signals. Arithmetic operations include binary and decimal addition, subtraction, multiplication and division, arithmetic shifts, and the like. The logical operation includes logical product (AND), logical sum (OR), exclusive logical sum (XOR), and the like. A
The control signal for the LU 60 is obtained by decoding the instruction in the program. For example, the ALU 60 operates as an adder for an add instruction, and the ALU 60 operates as an OR adder for an OR instruction. However, in order to execute the double precision shift operation, AL
It is sufficient for U60 to have at least two functions. The two functions are a function of directly outputting one of the two data input to the ALU 60 (through output) and a function of performing a logical sum operation on the two data input to the ALU 60. is there.

The register group 80 has a register 70 and a register 71. Before the double-precision shift operation is executed, the upper 16 bits of the double-precision data to be shifted are
Bit data is stored in the register 70, and lower 16-bit data of the double-precision data to be shifted is stored in the register 71. After the double precision shift operation is executed, the upper 16-bit data of the operation result by ALU 60 is stored in register 70, and the lower 16-bit data of the operation result by ALU 60 is stored in register 71.

Alternatively, the register for storing the high-order data and the low-order data before the double-precision shift operation is different from the register for storing the high-order data and the low-order data after the double-precision shift operation is executed. Alternatively, the register group 80 may be configured.

FIG. 2 shows the configuration of another embodiment of the shift arithmetic unit according to the present invention. The configuration of the shift operation device shown in FIG. 2 is the same as the configuration of the shift operation device shown in FIG. 1 except that a multiplexer 50 is added. Therefore, description of components other than the multiplexer 50 is omitted.

The multiplexer 50 outputs one of the two inputs according to the control signal. Multiplexer 5
One of the inputs of 0 is coupled to the output of register 40 and the other of the inputs of multiplexer 50 is coupled to the data (E). The control signal is supplied to the multiplexer 50 by the control circuit 90.

When a double precision shift operation is executed,
The multiplexer 50 is controlled to always select the data stored in the register 40. Therefore, the multiplexer 50 is not necessary to execute the double precision shift operation.
When an operation other than the double-precision shift operation (for example, a logical product operation) is executed, the multiplexer 50 may be controlled to select the data (E). By performing such control, it becomes possible to execute various calculations using the ALU 60.

FIG. 3 shows the structure of the shifter 20 shown in FIG. The shifter 20 realizes shifting from left (2 ⁵ −1) bits to right ²⁵ bits by combining 6 shifters. The shifter 20 includes a 1-bit left shifter 301, a 2-bit left shifter 302, a 4-bit left shifter 303, and a 8-bit left shifter 303.
Bit left shifter 304 and 16 bit left shifter 305 and 3
It includes a 2-bit right shifter 306. Shifter 20
Control signal CO by decoding the shift number.
A decoder 307 for generating L1 to COL6 is further included. The states of the control signals COL1 to COL6 are either active or inactive.
A control signal indicating the arithmetic shift or the logical shift from the control circuit 90 is supplied to each of the shifters 301 to 306 (however, the control signal is not shown in FIG. 3).

The 1-bit left shifter 301 receives the 16-bit data input to the shifter 20, and receives the control signal CO
Depending on L1, it is determined whether the 16-bit data is shifted to the left by 1 bit. When the control signal COL1 is active, the shifter 301 shifts 16-bit data to the left by 1 bit. When the control signal COL1 is inactive, the shifter 301 does not perform the shift operation and outputs the input data as it is. The shifter 301 outputs 17-bit data. Shifter 30
The least significant bit of the 17-bit data output from 1 is
It corresponds to the least significant bit of 16-bit data input to the shifter 301.

The 2-bit left shifter 302 is the shifter 301.
It receives the 17-bit data output from, and determines whether to shift the 17-bit data to the left by 2 bits according to the control signal COL2. When the control signal COL2 is active, the shifter 302 shifts the 17-bit data to the left by 2 bits. Control signal COL
When 2 is inactive, the shifter 302 does not perform the shift operation and outputs the input data as it is.
The shifter 302 outputs 19-bit data. The least significant bit of the 19-bit data output from the shifter 302 corresponds to the least significant bit of the 17-bit data input to the shifter 302.

The shifters 303 to 305 are also the shifters 3 described above.
It operates similarly to 01 and 302.

The 32-bit right shifter 306 is the shifter 30.
The 47-bit data output from 5 is received, and it is determined whether to shift the 47-bit data to the right by 32 bits according to the control signal COL6. Control signal COL
If 6 is active, shifter 306 shifts 47-bit data to the right by 32 bits. When the control signal COL6 is inactive, the shifter 306
Outputs the input data as it is without performing the shift operation. The shifter 306 is the 78th bit (most significant bit)
To 0th bit (least significant bit). The 32nd bit of the shifter 306 corresponds to the least significant bit of the 47-bit data output from the shifter 305. The shifter 306 outputs 16-bit data from the 63rd bit to the 48th bit as upper bit data (B). The shifter 306 outputs the 16-bit data from the 47th bit to the 32nd bit as the middle-order bit data (D).
The shifter 306 has 16 bits from the 31st bit to the 16th bit.
The bit data is output as lower bit data (C).

For example, when shifting the data by 10 bits to the left, the decoder 307 uses the control signal COL2.
And COL4 are activated, and the control signals COL1 and C
Deactivate OL3, COL5, and COL6.
As a result, the shifter 302 and the shifter 304 perform the shift operation, and the shifter 301, the shifter 303, the shifter 305, and the shifter 306 do not perform the shift operation and output the input data as they are.

When shifting data by 10 bits to the right, the decoder 307 controls the control signals COL2 and COL.
3 and COL5 and COL6 are activated, and the control signal C
Deactivate OL1 and COL4. as a result,
The shifter 302 and the shifter 303 shifter 305 shift data to the left by 22 bits, and then shifter 306 shifts the data to the right by 32 bits.
As a result, data shifted by 10 bits to the right is obtained.

FIG. 4 shows the structure of the 2-bit left shifter 302 shown in FIG. The shifter 302 receives a control signal indicating whether it is an arithmetic shift or a logical shift and a control signal indicating whether to shift. The shifter 302 includes a plurality of multiplexers and a plurality of AND circuits. The AND circuit is
In the case of arithmetic shift, and when not shifting, it is used to sign-extend the upper 2 bits output from the shifter 302 according to the value of the most significant bit input to the shifter 302. Shifter 301, 303-30
The configuration of 6 is similar to that of the shifter 302.

Similar to the structure of the shifter 20 shown in FIG. 3, by combining (m + 1) shifters, a shift of (2 ^m −1) bits left to 2 ^m bits right is realized. It is also possible to configure 20. Here, m is an integer of 1 or more. In this case, the shifter 20
Are m 2 ^k- bit left shifters (k = 0, 1, ...,
m-1) and a 2 ^m- bit right shifter. Here, k is an integer of 0 or more and m-1 or less. The configuration of the shifter 20 shown in FIG. 3 is an example when m = 5.

Further, in the configuration of the shifter 20 shown in FIG. 3, 16-bit data of the 47th bit to the 32nd bit of the shifter 306 is output as the middle-order bit data (D) and the 31st bit of the shifter 305 is output. From 16th
16-bit data of bits may be output as upper / lower bit data. In this case, the top /
The lower bit data is the multiplexer 3 shown in FIG.
It becomes equal to the output of 0. Therefore, when the shifter 20 is modified so as to output the middle-order bit data (D) and the high-order / low-order bit data, the shifter 20 outputs AL.
By coupling to one input of U60, the multiplexer 30 can be omitted.

Further, the shifter 20 has m 2 ^k- bit right shifters (k = 0, 1, ..., M) in order to realize a shift from right (2 ^m -1) bits to left 2 ^m bits. -1) and a 2 ^m- bit left shifter may be included.

Next, a method of executing a double precision shift operation using the shift operation device having the above-mentioned configuration will be described.

A method of logically shifting double-precision data to the left by N bits will be described below. Here, the double precision data is composed of upper 16-bit data and lower 16-bit data, and N is an integer of 1 or more. The upper 16-bit data is stored in the register 70, and the lower 16 bits are stored.
It is assumed that the bit data is stored in the register 71. It is also assumed that the upper data of the double-precision shift operation result is stored in the register 70, and the lower data of the double-precision shift operation result is stored in the register 71.

FIG. 5 schematically shows the processing of a double N-bit double-precision shift operation. In FIG. 5, the numbers in parentheses correspond to the numbers of the respective steps shown below.

Step 1: The shift number "-N" is stored in the register 10.

Step 2-1: Lower data is read from the register 71, and the lower data is input to the shifter 20 as data (A).

Step 2-2: The shifter 20 logically shifts the lower data to the left by N bits to output the upper bit data (B), the intermediate bit data (D) and the lower bit data (C). To do.

Step 2-3: The ALU 60 uses the shifter 2
The middle-order bit data (D) output from 0 is output as it is (through output). The output of the ALU 60 is stored in the register 71 as lower data.

Step 2-4: The multiplexer 30
The upper bit data (B) is selected from the upper bit data (B) and the lower bit data (C) output from the shifter 20. The selected upper bit data (B) is stored in the register 40.

Step 3-1: The upper data is read from the register 70, and the upper data is input to the shifter 20 as data (A).

Step 3-2: The shifter 20 logically shifts the upper data to the left by N bits to output the upper bit data (B), the intermediate bit data (D) and the lower bit data (C). To do.

Step 3-3: The ALU 60 is the shifter 2
Middle-order bit data (D) output from 0 and register 4
The logical sum operation is performed on the data (F) stored in 0. The output of the ALU 60 is stored in the register 70 as upper data.

In this way, the left N-bit double precision shift operation is realized. In the above process, steps 2-1 to 2-4 are executed in one step in executing the program, and steps 3-1 to 3-3 are
It is executed in one step in the execution of the program.

When double-precision data consisting of upper 16-bit data and lower 16-bit data is arithmetically shifted to the left by N bits, arithmetic shift is executed instead of logical shift in step 3-2 described above. do it. This is because the logical shift or arithmetic shift is related only to the upper data.

A method for logically shifting the double precision data rightward by N bits will be described below. Here, the double precision data is composed of upper 16-bit data and lower 16-bit data, and N is an integer of 1 or more. The upper 16-bit data is stored in the register 70, and the lower 16 bits are stored.
It is assumed that the bit data is stored in the register 71. It is also assumed that the upper data of the double-precision shift operation result is stored in the register 70, and the lower data of the double-precision shift operation result is stored in the register 71.

FIG. 6 schematically shows the processing of the right N-bit double precision shift operation. In FIG. 6, the numbers in parentheses correspond to the numbers of the respective steps shown below.

Step 1: The shift number "N" is register 1
Stored in 0.

Step 2-1: Upper data is read from the register 70, and the upper data is input to the shifter 20 as data (A).

Step 2-2: The shifter 20 logically shifts the upper data to the right by N bits to output the upper bit data (B), the middle bit data (D) and the lower bit data (C). To do.

Step 2-3: The ALU 60 uses the shifter 2
The middle-order bit data (D) output from 0 is output as it is (through output). The output of the ALU 60 is stored in the register 70 as upper data.

Step 2-4: The multiplexer 30
The lower bit data (C) is selected from the upper bit data (B) and the lower bit data (C) output from the shifter 20. The selected lower bit data (C) is stored in the register 40.

Step 3-1: Lower data is read from the register 71, and the lower data is input to the shifter 20 as data (A).

Step 3-2: The shifter 20 logically shifts the lower data to the right by N bits to output the upper bit data (B), the middle bit data (D) and the lower bit data (C). To do.

Step 3-3: The ALU 60 is the shifter 2
Middle-order bit data (D) output from 0 and register 4
The logical sum operation is performed on the data (F) stored in 0. The output of the ALU 60 is stored in the register 71 as lower data.

In this way, the right N-bit double precision shift operation is realized. In the above process, steps 2-1 to 2-4 are executed in one step in executing the program, and steps 3-1 to 3-3 are
It is executed in one step in the execution of the program.

When double-precision data consisting of upper 16-bit data and lower 16-bit data is arithmetically shifted to the right by N bits, arithmetic shift is executed instead of logical shift in step 2-2. do it. This is because the logical shift or arithmetic shift is related only to the upper data.

Further, in this embodiment, it is assumed that the 2-word double precision data is stored in the register 70 and the register 71. However, the present invention is not limited to this. When the 2-word double-precision data is stored in another holding circuit, the 2-word double-precision data may be input to the shift arithmetic unit as data (A) or data (E).

Next, a method of logically shifting triple precision data to the left by N bits will be described. Here, the triple precision data is composed of upper 16-bit data, middle 16-bit data, and lower 16-bit data, and N is an integer of 1 or more. In this example, register 7 shown in FIG.
In addition to 0, 71, a register 72 (not shown) is used.

The upper 16-bit data is stored in the register 70, and the middle 16-bit data is stored in the register 7.
1 and the lower 16-bit data is assumed to be stored in the register 72. The upper data of the result of the triple precision shift operation is stored in the register 70, the middle data of the result of the triple precision shift operation is stored in the register 71, and the lower data of the result of the triple precision shift operation is stored. Are stored in register 72.

FIG. 7 schematically shows the processing of the left N-bit triple precision shift operation. In FIG. 7, the numbers in parentheses correspond to the numbers of the respective steps shown below.

Step 101: The shift number "-N" is stored in the register 10.

Step 102-1: Lower data is read from the register 71, and the lower data is input to the shifter 20 as data (A).

Step 102-2: The shifter 20 logically shifts the lower data to the left by N bits,
The high-order bit data (B), the middle-order bit data (D), and the low-order bit data (C) are output.

Step 102-3: The ALU 60 directly outputs the middle-order bit data (D) output from the shifter 20 (through output). The output of the ALU 60 is stored in the register 72 as lower data.

Step 102-4: Multiplexer 30
Is the upper bit data (B) output from the shifter 20.
And the upper bit data (B) is selected from the lower bit data (C). Selected upper bit data (B)
Are stored in the register 40.

Step 103-1: The middle level data is read from the register 71, and the middle level data is input to the shifter 20 as data (A).

Step 103-2: The shifter 20 logically shifts the middle data to the left by N bits,
The high-order bit data (B), the middle-order bit data (D), and the low-order bit data (C) are output.

Step 103-3: The ALU 60 logically processes the middle-order bit data (D) output from the shifter 20 in step 103-2 and the data (F) stored in the register 40 in step 102-4. Performs a sum operation. The output of the ALU 60 is stored in the register 71 as medium data.

Step 103-4: Multiplexer 30
Is the upper bit data (B) and the lower bit data (C) output from the shifter 20 in step 103-2.
Of these, the upper bit data (B) is selected. The selected upper bit data (B) is stored in the register 40.

Step 104-1: The upper data is read from the register 70, and the upper data is input to the shifter 20 as data (A).

Step 104-2: The shifter 20 logically shifts the upper data to the left by N bits,
The high-order bit data (B), the middle-order bit data (D), and the low-order bit data (C) are output.

Step 104-3: The ALU 60 logically processes the middle-order bit data (D) output from the shifter 20 in step 104-2 and the data (F) stored in the register 40 in step 103-4. Performs a sum operation. The output of the ALU 60 is stored in the register 70 as upper data.

In this way, the left N-bit triple precision shift operation is realized. In the above process, steps 102-1 to 102-4 are executed in one step in the execution of the program, and step 103-
1 to 103-4 are executed in one step in the execution of the program, and steps 104-1 to 104-3 are executed.
Is executed in one step in the execution of the program.

When triple-precision data consisting of upper 16-bit data, middle 16-bit data, and lower 16-bit data is arithmetically shifted to the left by N bits, logical shift is performed in step 104-2 described above. Instead of, you can do an arithmetic shift. This is because the logical shift or arithmetic shift is related only to the upper data.

Similarly, a right N-bit triple precision shift operation can be performed.

Further, in general, an N-bit M double precision shift operation can be performed. Here, M is an integer of 3 or more. The processing of the triple precision shift operation already described with reference to FIG. 7 is an example of M = 3.

The procedure of the N-bit M double precision shift operation will be described below with reference to FIG. The processing of the N-bit M double precision shift operation includes processing 1 and processing 2 and processing 3 which are repeated (M−2) times. Here, the M double precision data which is the shifted data is one single precision first
It is assumed that the data consists of (M-2) single-precision second data and one single-precision third data. However, when the shift direction is left, the third data, the second data,
If the shift direction is right, the first data, the second data,
It is assumed that the higher-order data is the third data in order.

Process 1 is the following steps 801 to 804.
Is included.

Step 801: By shifting the first data by N bits, upper bit data (B), middle bit data (D) and lower bit data (C) are output.

Step 802: The middle-order bit data (D) output at step 801 is stored as a part of the result of the shift operation.

Step 803: Upper bit data (B) output in step 801 according to the shift direction
And lower bit data (C) are selected.

Step 804: The data selected in step 803 is stored.

In step 803 of process 1, if the shift direction is left, the upper bit data (B) is selected, and if the shift direction is right, the lower bit data (C) is selected. . Process 1 corresponds to steps 102-1 to 102-4 described above.

The process 2 includes the following steps 805 to 809.
Is included.

Step 805: Shifting one of the (M-2) second data by N bits,
The high-order bit data (B), the middle-order bit data (D), and the low-order bit data (C) are output.

Step 806: Upper bit data (B) output at step 805 according to the shift direction
And lower bit data (C) are selected.

Step 807: The data selected in step 806 is stored.

Step 808: The middle-order bit data (D) output in step 805 is combined with the most recently stored data in steps 804 and 807. This combination is achieved, for example, by performing an OR operation.

Step 809: The data combined in step 808 is stored as a part of the result of the shift operation.

In step 806 of process 2, if the shift direction is left, the upper bit data (B) is selected, and if the shift direction is right, the lower bit data (C) is selected. . Process 2 corresponds to steps 103-1 to 103-4 described above.

Process 3 is the following steps 810 to 812.
Is included.

Step 810: The upper bit data (B), the middle bit data (D) and the lower bit data (C) are output by shifting the third data by N bits.

Step 811: The middle-order bit data (D) output at step 810 and the data most recently stored at step 807 are combined. This combination is achieved, for example, by performing an OR operation.

Step 812: The data combined in step 811 is stored as a part of the result of the shift operation.

Process 3 is the above-described step 104-1.
It corresponds to 104-3.

In this way, M double precision shift operations are realized by M times of shift operations. Process 1 and process 2
And the process 3 are each executed in one step in the program execution. Process 2 is repeated (M-2) times. Therefore, the M double precision shift operation is realized in M steps except for the setting of the shift number. A large number of registers are required to perform the M double precision shift operation. However, the number of registers can be reduced by using a known method such as temporarily saving data.

[0118]

According to the present invention, when the double-precision data is shifted to the left, the data that overflows from the lower data is stored in the register by the left shift, and the data stored in the register and the upper data are combined. The result of the left shift is combined with the result. When the double-precision data is shifted to the right, the data shifted from the upper data is stored in the register by the right shift, and the data stored in the register and the result of right-shifting the lower data are combined. .
In this way, the shift calculation of double-precision data is realized by two shift operations. Therefore, the number of shift operations can be reduced once as compared with the shift calculation of double precision data using the conventional shift calculation device. As mentioned above, LD
In -CELP, a double precision shift operation of about 500,000 times / sec is executed. By reducing the shift operation once in the double-precision shift operation, it is possible to reduce the number of dynamic steps during program execution by 500,000 steps / second. This significantly speeds up the processing including the double-precision shift operation. Further, other processing may be executed at a time corresponding to the reduction of dynamic steps when executing a program. Alternatively, it is possible to reduce the power consumption by not performing the processing in the time corresponding to the reduction.

Similarly, according to the present invention, a shift operation of M double precision data can be realized by M shift operations. Here, M is an integer of 3 or more. As a result, the shift calculation of multi-precision data can be efficiently performed.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of a shift arithmetic unit according to the present invention.

FIG. 2 is a diagram showing a configuration of another embodiment of the shift arithmetic unit according to the present invention.

FIG. 3 is a diagram showing a configuration of a shifter 20 shown in FIG.

4 is a diagram showing a configuration of a left 2-bit shifter 302 shown in FIG.

FIG. 5 is a diagram schematically showing processing of a left N-bit double precision shift operation according to the present invention.

FIG. 6 is a diagram schematically showing a process of a right N-bit double precision shift operation according to the present invention.

FIG. 7 is a diagram schematically showing processing of left N-bit triple precision shift operation according to the present invention.

FIG. 8 is a flowchart showing a process of an N-bit M double precision shift operation according to the present invention.

FIG. 9 is a diagram showing a configuration of a conventional shift calculation device.

FIG. 10 is a diagram schematically showing a conventional double precision shift calculation process.

[Explanation of symbols]

 10, 40, 70, 71 register 20 shifter 30, 50 multiplexer 60 arithmetic unit (ALU) 90 control circuit

Claims (14)

[Claims] 1. A shift means for outputting high-order bit data, middle-order bit data, and low-order bit data by shifting data according to the number of shifts, and a shift means coupled to the output of the shift means, depending on the shift direction. A first selecting means for selecting one of the upper bit data and the lower bit data, and a first storage coupled to an output of the first selecting means for storing the data selected by the first selecting means. Means, and an output of the shift means and an output of the first storage means, and outputs a calculation result by performing an operation on the middle-order bit data and the data stored in the first storage means. A shift arithmetic device comprising: arithmetic means; and a second storage means coupled to an output of the arithmetic means and storing the arithmetic result. 2. The shift computing device receives second data, and selects one of the further data and the data stored in the first storage device according to a control signal. Is further equipped with
The shift arithmetic unit according to claim 1, wherein an output of the second selecting unit is input to the arithmetic unit. 3. The shift means decodes the ^m 2 ^k- bit shifters (k = 0, 1, ..., M-1), 2 ^m- bit shifters, and the shift number to obtain the ^m bits.
2 ^k- bit shifters (k = 0, 1, ..., M-1)
The shift operation device according to claim 1, further comprising: a decoding unit that supplies a control signal indicating whether or not to perform a shift operation to each of the 2 ^m bit shifters, and m is an integer of 1 or more. 4. The shift arithmetic unit according to claim 3, wherein a part of the output of the 2 ^m-1 bit shifter is equal to the output of the first selecting means. 5. The shift operation device according to claim 1, wherein the second storage means includes a plurality of registers that respectively store the operation result portions. 6. The shift according to claim 1, wherein the second storage means includes a plurality of registers that respectively store the data portion and a plurality of registers that respectively store the operation result portion. Arithmetic unit. 7. A shift operation method for performing a double-precision shift operation using first data and second data, comprising: a) shifting the first data in accordance with the number of shifts to obtain high-order bits. Outputting data, middle-order bit data, and lower-order bit data, b) storing the middle-order bit data output in step a) as a part of the result of the shift operation, and c) in the shift direction. Accordingly, the step of selecting one of the upper bit data and the lower bit data output in step a), d) the step of storing the data selected in step c), and e) the shift number. Outputting the high-order bit data, the middle-order bit data, and the low-order bit data by shifting the second data accordingly, and f) the step e) combining the middle bit data output in step d) with the data stored in step d), and g) storing the data combined in step f) as part of the result of the shift operation. A shift operation method including steps. 8. The combining in step f) is accomplished by performing an OR operation on the middle bit data output in step e) and the data stored in step d). The shift calculation method according to claim 7. 9. The method according to claim 7, wherein steps a) to d) are executed in one step in the execution of the program, and steps e) to g) are executed in one step in the execution of the program. Shift calculation method. 10. A shift operation method for performing a multiple precision shift operation using first data and at least one second data and third data, comprising: a) the first data according to the number of shifts. To output the high-order bit data, the middle-order bit data, and the low-order bit data, and b) store the middle-order bit data output in step a) as a part of the result of the shift operation. And c) selecting one of the upper bit data and the lower bit data output in step a) according to the shift direction, and d) storing the data selected in step c). And e) shifting one of the at least one second data according to the shift number to obtain a high-order bit data and a middle-order bit. Data and lower bit data, f) selecting one of the higher bit data and the lower bit data output in step e) according to the shift direction, and g) step f) storing the selected data, h) combining the middle bit data output in step e) with the most recently stored data in steps d) and g), i) storing the combined data in step h) as a part of the result of the shift operation; and j) shifting the third data according to the number of shifts to obtain upper bit data and middle bit data. And k) outputting the lower-order bit data, and k) the step of outputting the middle-order bit data output in step j). Most recently stored the data coupling a, l) shift operation method comprising the steps of storing the data combined in step k) as a result of part of the shift operation in g). 11. The combining in step h) performs an OR operation on the middle-bit data output in step e) and the most recently stored data in steps d) and g). The shift arithmetic method according to claim 10, which is achieved by 12. Combining in step k) is accomplished by performing an OR operation on the middle bit data output in step j) and the data most recently stored in step g). Will be
The shift calculation method according to claim 10. 13. Steps a) to d) are executed in one step in the execution of the program, steps e) to i) are executed in one step in the execution of the program, and steps j) to l are executed. ) Is executed in one step in the execution of the program, the shift operation method according to claim 10. 14. The shift calculation method comprises step e).
~ Further comprising repeating step i),
The shift calculation method according to claim 10.