JPH07281838A - Information recording device and its setting method - Google Patents

Abstract

PURPOSE:To decrease switches, etc., such as a jumper set and provide a magnetic recording device which is small-sized and has high reliability as to a general purpose magnetic recording device which is adaptive to an interface of different specifications according to host computer. CONSTITUTION:A control IC 2 is provided with an input/output circuit 10 and selectors 12-16 select attributes of external terminals of the control IC 2. A select signal is also stored in a storage circuit 30 which is provided in the control IC 2 and uses a fuse to simplify the constitution of the magnetic recording device. Consequently, the external terminals of the control IC 2 and an interface connector 3 can be connected directly, so changeover switches, etc., are omitted to reduce the size of the magnetic recording device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information recording apparatus for recording and reproducing information using a recording medium such as a magnetic disk.

[0002]

2. Description of the Related Art In an information recording device such as a floppy disk drive, it is sometimes necessary to change the arrangement of interface connectors depending on the specifications of a host computer to be connected. For example, a computer of a certain manufacturer needs to be assigned an input side to a predetermined connector pin, and a computer of another manufacturer needs to be assigned an output side to the same connector pin. Even when the input side is assigned to a predetermined connector pin, if the connection interface with the computer has a plurality of input lines, these input sides may be replaced by the computer.

Therefore, in a mass-produced information recording device, a control chip for information control mounted on the information recording device is provided with terminals that can be used in all cases so as to interface with various models. The connection between these terminals and the interface connector is set by switches such as short pins, jumper sets and dip switches provided on the board.

Similarly to these, an address selection input is initially set by the switches provided on the substrate. This is a selection input for instructing which information recording device is selected when a plurality of information recording devices are connected and used in a daisy chain method. With this address selection input, for example, either the information recording apparatus A or B is selected, but it is not known whether A or B is set at the beginning of manufacturing the information recording apparatus. For this reason, a short pin and a DIP switch are provided so that the side where this address selection input can also be input to the control chip can be set later. Further, there is a specification switching such as a terminal resistance of an input or output terminal or a logic setting of a signal, which is set by using a short pin or the like.

[0005]

As described above, in the conventional information recording apparatus, circuit parts such as short pins and dip switches occupy a large space on the substrate in order to have versatility. There is also a large space for connecting wiring. In addition, if the switches are set incorrectly, the predetermined function will not be achieved, and if there are many mechanical parts, the probability of failure such as connection failure will increase.

Therefore, in the present invention, parts occupying a lot of space on these substrates are omitted, and it is possible to reduce the size and weight required in recent years, especially in the field of information equipment, and to provide highly reliable information. It is intended to provide a memory device. Also, by making the output terminal of the control chip itself applicable to each specification of the external device,
It is also intended to reduce the number of terminals of the control chip and further promote the downsizing and weight saving of the information recording apparatus.

Further, the terminal chip setting, the address selection input setting, the terminal resistance setting corresponding thereto, and the specification switching setting are not individually performed by the corresponding short pins, but the control chip is used. It is an object of the present invention to provide an information recording device that can be collectively carried out inside, or the number of setting switches outside the control chip can be minimized. Another object of the present invention is to provide an information recording apparatus having a structure in which the control chip does not grow even if such many functions are installed. Another object of the present invention is to provide an information recording device capable of suppressing the power consumption of the control chip even if the number of functions is increased. And
It is also an object to provide an information recording device capable of recording and reproducing a selection signal defining these functions without error.

[0008]

An information recording apparatus according to the present invention has a control integrated circuit device for controlling information between a stored recording medium and an external information processing apparatus,
This control integrated circuit device is connectable to an interface control means for controlling input / output provided with an internal input and an internal output and an external terminal of the control integrated circuit device by selecting either the internal input or the internal output. It is characterized by having an input / output selection means.

As described above, in the control integrated circuit device, if the input or the output is determined according to the specifications of the information processing device to which the information recording device is connected and the connection is made to the external terminal of the control integrated circuit device, It is not necessary to provide a switch such as a short pin between the interface connector of the recording device and the external terminal of the control integrated circuit device. Therefore, the area occupied by the short pins and the like on the substrate of the information recording apparatus can be omitted, and the space for wiring connecting these can be reduced, so that the information recording apparatus can be made smaller and lighter.

Further, if the specifications of the external terminals of the control integrated circuit device are determined in the integrated circuit, it is not necessary to prepare a number that can satisfy all the specifications as the external terminals of the control integrated circuit device. . Therefore, since the number of external terminals can be minimized, the size of the control integrated circuit device can be reduced. Further, as a result, the area occupied by the control integrated circuit device on the substrate also becomes small, so that miniaturization of the information recording device can be promoted.

Further, when an external terminal which is both an input and an output is selected as an output, the terminating resistor load of the input circuit is added and the output load becomes heavy. Therefore, when the output is selected It is desirable to increase the termination resistance value. Therefore, the control integrated circuit device is provided with resistance value adjusting means capable of selecting the termination resistance value of the external terminal according to the selection status of the input / output selection means, and the termination resistance value can be switched within the control integrated circuit device. The size of the information recording device can be reduced.

Further, there is a case in which one of a plurality of inputs or a plurality of outputs is selected and connected to a predetermined interface connector in accordance with the specifications of the information processing apparatus. Even in this case, interface control means for controlling input / output having a plurality of internal inputs or outputs in the control integrated circuit device, and one internal input or an internal output from the plurality of internal inputs or a plurality of internal outputs. It suffices to provide connection selecting means capable of selecting an output and connecting to an external terminal of the control integrated circuit device. Since the external terminals can be determined in the control integrated circuit device in accordance with the specifications of the information processing device, selection switches such as short pins on the substrate of the information recording device are not required, and the size and weight can be reduced.
Further, since the number of terminals of the control integrated circuit device can be reduced as in the above case, the size can be reduced in this respect as well.

These input / output selection means and connection selection means can be constituted by selector means which can be switched by a selection signal. The selection signal can be set by a memory outside the control integrated circuit device, a DIP switch, or the like. But,
If the control integrated circuit device itself has a selection signal storage means capable of storing and outputting a selection signal, the interface connector can be switched by a single chip, so that the configuration of the information recording device is simple and compact. It can be realized.

Further, if the control integrated circuit device is provided with a plurality of address input means and an address input selection means for selecting one of the address input means and connecting it to the internal address input of the interface control means, control is performed. It becomes possible to select the address input inside the integrated circuit device. Therefore, it is not necessary to provide a switch such as a short pin on the substrate of the information recording device to switch the connection, and the information recording device can be miniaturized.

Similarly, if the control integrated circuit device is provided with resistance value adjusting means capable of selecting the termination resistance value of each address input means according to the selection state of the address input means, the termination resistance is switched on the substrate. A selection switch such as a short pin is not required, and the information recording device can be downsized. If the terminal resistance on the non-selected side of the address input means is increased by the resistance value adjusting means, the output load on the drive side of the address signal when the daisy chain connection is made without opening the non-selected atres input means. Can be reduced.

The signal for selecting the address input means is
It may be stored in the selection signal storage means prepared inside the control integrated circuit device in the same manner as the input / output selection. Alternatively, the control integrated circuit device may be provided with address selection signal applying means capable of applying a plurality of levels of signals for switching the address input selecting means. In this case, if a permitting means is provided that enables reading and writing of the selection signal storage means when an intermediate level signal that is not supplied to the address selection signal application means in a normal use state is applied,
The selection signal storage means can be read and written only at a predetermined timing such as at the time of initial setting. By restricting the reading and writing of the selection signal storage means by such a method, the contents set in the selection signal storage means can be protected, and for this purpose, it is not necessary to provide a dedicated terminal or switch in the control integrated circuit device.

Further, for controlling the means for enabling the writing to the selection signal storage means or the reading from the selection signal storage means by the signal inputted from any of the plurality of address input means and the signal from the permission means. If provided in the integrated circuit device, a double safety mechanism for protecting the selection signal storage means can be incorporated without increasing the number of terminals. Also, the same function can be realized by using a signal input to the specification switching setting means instead of the address input means.

Further, when the required functions cannot be realized by these address input means and specification switching setting means, these means are used as permitting means and actual control is performed via a connection signal with the information processing apparatus. You can solve it.

If a resistance memory element whose resistance value changes when a write voltage is applied and a write control means capable of turning the write voltage on and off are employed as the selection signal storage means, the same manufacturing process as the logic circuit portion is performed. Build in the process,
Further, since the stored contents can be read at the same operating voltage, the control integrated circuit device can be downsized, the cost can be reduced, and the reliability can be improved. Further, since the selection signal is stored by the change in the resistance value, the storage stability is high.

As such a resistance memory element, a fuse using polysilicon or the like, a resistor, an aluminum wiring, a contact connecting an aluminum wiring and an aluminum wiring, a transistor, a diode or the like can be adopted.

When reproducing the selection signal stored in the resistance memory element, it is necessary to pass a current through the resistance memory element. Therefore, a read control means capable of turning on / off a read current supplied to the resistance memory element and a temporary memory means capable of storing a selection signal reproduced in the resistance memory element by the read current are integrated in the control integrated circuit device. In this case, the read current may be supplied only when the selection signal is loaded into the temporary storage means, and the current consumption of the control integrated circuit device can be reduced.

In order to control the read control means, an initial setting means for outputting a pulse signal for turning on the read control means after a predetermined time from a reset signal for resetting the information recording device by turning on the power supply is provided as an integrated circuit for control. It may be installed in the device. The read current is supplied to the resistance memory element only during this pulse signal, and the selection signal stored in the resistance memory element can be set in the temporary memory means. Then, the information recording device can be operated by the selection signal set in the temporary storage means to set the interface connector etc. to the preset specifications.

When a resistance memory element is used as the selection signal memory means, since the resistance memory element is an irreversible memory, it is desirable to confirm the signal to be written before writing the selection signal to the resistance memory element. Therefore, it is effective to provide the selection signal storage means with a temporary storage means capable of setting a signal for controlling the write control means.

When a temporary storage means capable of setting a signal for writing is provided, if this temporary storage means can be preset by a selection signal reproduced in the resistance storage element, the temporary storage means for writing and the reading storage The temporary storage means can be shared, the structure of the control integrated circuit device is simplified, and the miniaturization and high reliability can be achieved.

Further, when controlling a plurality of resistance memory elements and write control means, it is desirable to employ a shift register capable of setting bit signals to be controlled corresponding to the respective write control means and resistance memory elements. If a shift register is adopted, it is only necessary to provide a data input and a clock input for setting data in the shift register in order to set a plurality of selection signals from outside the control integrated circuit device. Therefore, the number of external terminals of the control integrated circuit device can be reduced and the size can be reduced. Further, if the shift register can be preset by a selection signal reproduced in a resistance memory element corresponding to each bit, the shift register can be used as a temporary memory means to be referred to during normal operation of the control integrated circuit device. .

To set a control integrated circuit device having such a resistance memory element, a selection signal supplied from an external terminal of the control integrated circuit device is loaded into a temporary storage means in the control integrated circuit device. Then, the pre-setting step of confirming the signal output from the temporary storage means, and the write voltage is controlled based on the signal set in the temporary storage means to change the resistance value of the resistance storage element of the selection signal storage means. It is desirable to go through a writing step and a verification step of determining the resistance value of the resistance memory element. Since the resistance memory element is an irreversible memory, it is desirable to prevent errors by confirming the data to be written in the preset step. Further, in the verification process, if the resistance memory element determines a change in the resistance value of each element, the stored content of the memory element can be easily confirmed. Further, when the resistance value of the resistance memory element is not sufficiently changed, the above steps are repeated to reliably set the data.

The write / read method for such a resistance memory element can be similarly used for a memory element such as an EEPROM or EPROM.

[0028]

Embodiments of the present invention will be described below with reference to the drawings. The information recording apparatus 1 of this example shown in FIG. 1 is a magnetic recording apparatus using a floppy disk as a recording medium.
The magnetic recording device 1 interfaces with an information processing device such as a host computer to which the magnetic recording device is connected, and includes a control IC 2 for controlling the operation of the magnetic recording device 1 and the input / output of data. . The control IC 2 is connected to the interface connector 3 of the magnetic recording device 1 to manage the input / output, the data input from the input / output circuit 10, or the input / output circuit 1.
An interface control circuit 5 for controlling data to be output to 0, and a system control circuit 6 for operating the magnetic recording device 1 by the data from the interface control circuit 5. Further, the control IC 2 also includes a storage circuit 30 that stores data that sets the specifications of the input / output circuit 10, and an initialization circuit 50 that outputs a reset signal to the storage circuit. Further, the magnetic recording device 1 is provided with a switch 60 for setting its own address in the case of daisy chain connection, and is connected to the address selection terminal T6 of the control IC 2.

The external terminal T1 of the control IC 2 is a terminal corresponding to the connector number C1 of the interface connector 3. The connector pin C1 is a connector number that can be switched to the input side or the output side according to the specifications of the host computer. In the control IC 2 of this example, the terminal T1 is connected to the input / output selector 12 provided in the input / output switching block 11 of the input / output circuit 10. The input / output selector 12 receives the selection signal F0 supplied from the memory circuit 30.
The input side IN-A or IN-B and the output side OUT-A or OUT-B, which will be described later, connected to the input / output selector 12 can be selected.

The terminal T2 of the control IC 2 is a terminal corresponding to the connector number C2 of the interface connector 3. The connector pin C2 is a connector number that can be switched to either IN-A or IN-B among the inputs prepared in the interface control circuit 5 according to the specifications of the host computer. In the control IC 2 of this example, the terminal T2 is connected to the input selector 13 and the input selector 14 provided in the input / output switching block 11 of the input / output circuit 10. The input / output selector 12 is also connected to the input selectors 13 and 14. The input selector 13 is connected to the input terminal IN-A of the interface control circuit 5, and the input selector 14 is connected to the input terminal IN-B. These input selectors 13 and 14 are configured to be able to select opposite input sides, that is, either the input selector 12 or the external terminal T2, by the selection signal F2 supplied from the memory circuit 30.

Further, the terminal T3 of the control IC 2 is a terminal corresponding to the connector number C3 of the interface connector 3. The connector pin C3 is a connector number that can be switched to either OUT-A or OUT-B prepared in the interface control circuit 5 according to the specifications of the host computer. In the control IC 2 of this example, the terminal T3 is connected to the output selector 16 provided in the input / output switching block 11 of the input / output circuit 10.
The output selector 16 receives output signals OUT-A and O of the interface control circuit 5 connected to the output selector 16 according to the selection signal F1 supplied from the memory circuit 30.
UT-B can be selected. Further, output terminals OUT-A and OUT-B of the interface control circuit 5
The output selector 15 that can be selected is prepared, and this output selector 15 is connected to the input / output selector 12.
Further, the output selector 15 is configured to make a selection opposite to that of the output selector 16 by the same selection signal F1 as that of the output selector 16.

As described above, in the control IC 2 of this example, the IC
The external terminals T1 to T1 of the IC are controlled by the internal input / output circuit 10.
Attributes such as input / output of T3 or types of input and output can be changed. Therefore, depending on the specifications of the host computer, the connector numbers C1 to C1 of the interface connector 3
Even if the attributes of C3 are different, a highly versatile magnetic recording device can be provided by setting matching with these attributes in the IC. Therefore, in a conventional magnetic recording device, a jumper set, which is provided on the connection wiring between the control IC and the interface connector 3,
A changeover switch such as a short pin or a DIP switch is unnecessary, and the control IC 2 of this example can be directly connected to the interface connector 3.

In the conventional magnetic recording apparatus, since the attribute of the interface connector 3 is set by the mechanical changeover switch or the pattern on the board, a considerable space on the board of the magnetic recording apparatus is used for the changeover switch and the wiring area therefor. Was used as. However, by using the control IC of this example, the area occupied by the changeover switch on the substrate can be omitted, so that the size of the magnetic recording device can be greatly reduced. Further, since the connection with these switches can be omitted, the magnetic recording device can be easily manufactured. Furthermore, the number of parts can be reduced, and troubles such as wiring and switches can be prevented, so that reliability can be improved.

Further, when the attribute of the interface connector is determined using the changeover switch as in the conventional case,
It is necessary to provide the control IC with terminals capable of handling all kinds of inputs and outputs. However, if the attributes of the terminals can be set in the control IC like the control IC of this example, only the number of terminals corresponding to the interface connector 3 may be provided, and the number of terminals of the chip 2 can be reduced. Can be reduced. Therefore, the size of the IC can be reduced, and the number of wirings connected to the terminals can also be reduced, so that the magnetic recording device can be downsized.

FIG. 2 shows the configuration of the input / output circuit 10. In this example, 2-bit data selectors are used as the input selectors 13 and 14, and the input sides of the respective input selectors 13 and 14 are connected to the terminals T1 and T2 via the input buffer. Further, the input selector 13 and the input selector 14 invert and input the selection signal F2 for controlling them. Therefore, when the selection signal F2 is at a high level, the signal from the terminal T1 is connected to the input terminal IN-A via the input selector 13, and the signal from the terminal T2 is connected to the input terminal IN-B via the input selector 14. When the selection signal F2 is low level, these connections are reversed.

The output selectors 15 and 16 are also composed of 2-bit data selectors, and the terminals OUT-A and OUT-B are connected to the input sides of the respective data selectors 15 and 16. Also, output selector 1
In 5 and 16, the selection signal F1 for controlling them is inverted and input. Therefore, when the selection signal F1 is at a high level, the output terminal OUT-A has the output selector 15
To the input / output selector 12 connected to the terminal T1 via
The output terminal OUT-B passes through the output selector 16 and the terminal T3.
to go into. These connections are reversed when the low level selection signal F1 is supplied.

The input / output selector 12 of this example has a selection signal F.
It is composed of an AND gate controlled by 0. Therefore, when the selection signal F0 is at a high level, the output terminal OUT-A or OUT supplied to the input / output selector 12
A signal from -B can drive the output transistor connected to the terminal T1. In this way, at the terminal T1 on the input side or the output side, when the output side is selected, the host side must also drive the load of the input circuit of the magnetic recording device with the same termination resistance value as that on the input side. Occurs, and the output load increases.

Therefore, it is necessary to change the terminating resistance value when the input side is selected and when the output side is selected.
In this example, the terminal T1 is provided with the resistance value adjusting circuit 17, and the termination resistance value is changed by the selection signal F0. In the resistance value adjusting circuit 17, the selection signal F0 is at a high level, that is, the terminal T1.
Switch 18 that turns off when is selected as the output side
And a resistance means 19 having a low resistance value are connected in series to the terminal T1. If the value of the terminating resistor can be switched inside the control IC 2 as described above, switches such as short pins set on the substrate of the magnetic recording device can be reduced, so that the magnetic recording device can be made compact and highly functional. Can be realized.

The input / output circuit 10 provided in the control IC 2 of this example further includes an address selection block 20. The address selection block 20 includes two address pins C4 and C5 of the interface connector 3.
The terminals T4 and T5 connected to are connected. In this example, the address signal supplied to the address terminals T4 and T5 is a signal indicating which magnetic recording device is selected when the two magnetic recording devices are daisy chain connected. The address selection block 20 of this example includes an address selector 21 controlled by an address switch 60 for selecting its own address provided on the magnetic recording device, and the address selector 21 and the address terminals T4 and T5 are connected to each other. ing. When the address selection signal from the address switch 60 supplied to the terminal T6 is at high level, the terminal T5 is connected to the address terminal D-SEL of the interface control circuit 5 via the address selector 21 and supplied to the terminal T5. This address signal causes the magnetic recording device to move.
Conversely, when the address selection signal is at the low level, the terminal T
4 is connected to the interface control circuit 5 via the address selector 21, and the magnetic recording device is operated by the address signal supplied to the terminal T4.

In the conventional control IC, only the address terminal of the interface control circuit is provided, and a mechanical switch such as a jumper is used on the substrate of the magnetic recording device to provide one of the plurality of address terminals in the interface connector 3. The connection of the address terminal of the control IC was set. However, like the control IC 2 of this example, it accepts both address signals that have entered the interface connector 3,
If one of them is selected in the IC, mechanical switches can be omitted. Then, the size of the magnetic recording device can be reduced.

At the address terminals T4 and T5, it is desirable to increase the termination resistance value of the address terminals on the non-selected side to reduce the driving load on the host side. Conventionally, the termination resistance value is also switched using switches on the board. However, in the control IC 2 of this example, the resistance value adjusting circuits 22a and 22b are provided in the address selection block 20, and the terminating resistance is switched by the address selection signal supplied to the terminal T6. The configuration of these resistance value adjusting circuits 22a and 22b is the same as that of the resistance value adjusting circuit 17 described above, and the description thereof will be omitted. Therefore, by using the control IC 2 of this example, it is possible to omit the switches for switching the terminating resistance value, so that the size of the magnetic recording device can be reduced and the number of parts can be reduced.

Further, in the control IC 2 of this example, the address selection block 20 can be used to generate the write permission signal W / G for permitting the writing of the memory circuit 30 and the read permission signal R / G for permitting the reading. I have to. The memory circuit 30 needs to be set when the magnetic recording device is initialized, but if the permission signals W / G and R / G are created using the address selection block 20, the number of terminals required for the initial setting is set. Can be reduced, and the size of the control IC can be reduced.

In the address selection block 20 of this example, first, when the intermediate level between the high level and the low level is supplied to the terminal T6 to which the address selection signal is supplied, the enable signal output circuit 23 capable of outputting the enable signal. Is provided. In normal operation, no intermediate level signal is applied to the terminal T6 which is not connected to the interface connector 3. Therefore, if the permission signal is output by using the permission signal output circuit 23, the memory circuit 30 is in the normal state.
It is possible to prevent problems such as rewriting of the memory of.

In the permission signal output circuit 23 of this example, two buffer gates 24a and 24b having different threshold values are connected in parallel. And these two thresholds V
When a signal at an intermediate level between th1 and Vth2 is applied to the terminal T6, the output results of the buffer gates 24a and 24b are determined and the permission signal AL is output. Next, the permission signal AL is supplied to the gate signal output circuit 25 and the terminal T
The write enable signal W / G and the read enable signal R / G can be output to the memory circuit 30 by the signals respectively input from 4 and T5.

As described above, in the control IC 2 of this example, a plurality of functions can be assigned to the input / output terminals and the address terminals. Therefore,
It can perform many functions with a small number of terminals, and it can be made into a small chip with multiple functions.

Of course, the intermediate level permission signal assigned to the address terminal can also be assigned to the specification switching setting terminal for switching the logic of the connection signal with the information processing apparatus.

Further, specification switching setting such as switching the logic of a connection signal with the information processing apparatus can be performed using these storage circuits.

FIG. 3 shows the configuration of the memory circuit 30. The storage circuit 30 of this example is a circuit that can store and output four selection signals F0 to F3. The memory circuit 30 is
A storage unit 31 that stores and outputs these selection signals and a read control unit 45 that controls the reading of the storage unit 31 are provided.
The storage unit 31 includes a storage block 32 including four fuse blocks 33a to 33d, and these fuse blocks 3
Register block 4 for temporarily recording selection signals 3a to 3d
0 is set. The register block 40 includes four registers 4 corresponding to the fuse blocks 33a to 33d.
1a to 1d are composed of shift registers connected in series.

Each of the fuse blocks 33a to 33d has the same structure and is provided with a fuse 34 whose resistance value changes according to a write pulse signal W / P (bar) described later. This fuse 34 has a short circuit resistance of 300Ω.
The resistance value is 300 KΩ or more when the write pulse signal W / P (bar) causes an open state.
The fuse block capable of storing information by such a change in resistance value can be formed in the IC by the same manufacturing process as the logic circuit and can be operated at the same power supply level.
It is excellent in that the control IC is small and can be easily manufactured.
In addition, the manufacturing process is simple, so reliability is high.

The input / output circuit 11 is connected to both ends of the fuse 34.
Gates 35a and 35b which are turned on by either the write signal W supplied to the W / G terminal or the read signal R from the read control unit are connected in series. The on-resistance of the gate 35a connected to the high potential side of the fuse 34 is sufficiently larger than the resistance of the fuse 34 and the on-resistance of the gate 35b at the time of short circuit, and the gate 35a also functions as a pull-up resistor. Fulfill The high potential side of the fuse 34 is input to the preset terminal of the register 41a via the AND gate 42. Since the read signal R is also input to the AND gate 42, in the read state in which the read signal R becomes high level, the fuse 34a
Can be set in the register 41a.

A fuse selection transistor 36 is connected to the high potential side of the fuse 34a, and the fuse 3
A write pulse signal W / P (bar) is connected to the low potential side of 4a. The fuse selection transistor 36 can be turned on / off by a selection gate 37 controlled by the level of the write signal R and the corresponding shift register 41a. Therefore, the shift register 41a
Is set to a high level, the fuse selection transistor 36 is turned on by the selection gate 37 in a write state in which the write signal R is at a high level. When the write pulse signal W / P (bar) is supplied, the fuse 34a
A write voltage is applied to the fuse 34a and the fuse 34a changes to an open state. As described above, in the memory circuit 30 of this example, after the states of the selection signals F0 to F3 are loaded into the shift register 40, the write pulse signal W / P (bar) is set as the writing state.
Is supplied to select the fuses 34a to 34d from the selection signals F0 to F0.
Can be fixed according to F3.

Select signals F0 to F3 are applied to the shift register 40.
In order to load the data corresponding to, the memory circuit 30 of this example is provided with a data input terminal DATA-IN and a clock terminal CLOCK. Therefore, even when a plurality of selection signals are loaded in order to be recorded in a plurality of fuses, these signals are loaded into one data input terminal DATA.
Since serial transfer can be performed from -IN, the number of external terminals of the control IC 2 can be minimized and the size can be reduced.

Further, the memory circuit 30 includes a read control circuit 45.
The read signal R is output at a timing at which the contents of the storage block 32 can be read even after the magnetic recording device 1 is reset, in addition to reading the contents of the storage block 32 when the control IC 2 is initialized. is doing. Therefore, the read control circuit 45 is input with the read pulse signal R / P output from the initial setting circuit 50 in addition to the read enable signal R / G output from the input / output circuit 11.
When either of these becomes high level, the read signal R is set to high level and the memory block 32 can be brought into a read state.

The initial setting circuit 50 of this example has a reset signal from the host side or an internal reset signal R when the power is turned on.
It is a circuit that outputs EST (bar). Further, a delay circuit 51 is provided so that the read pulse signal R / P, which is a pulse signal for a fixed time, can be output after a predetermined time has elapsed after the internal reset signal REST (bar) was output.

First, when the reset signal REST (bar) is input to the memory circuit 30, the shift register 40 can be reset. Next, when the read pulse signal R / P is input, the read control circuit 45 outputs the read signal R, and the storage block 32 is in the read state during the pulse signal. As a result, the gates 35a and 35b are turned on, and the fuse blocks 33a to 33d are turned on. The high potential side voltage of the fuse 34 generated at this time presets the registers 41a to 41d corresponding to the fuse blocks 33a to 33d. The read pulse signal R / P becomes low level after a lapse of a predetermined time, and the storage block 32 is not in the read state and is not energized, but the insides of the registers 41a to 41d remain set to the state of the storage block 32. The selection signal output terminals F0 to F3 of the storage circuit 30 have corresponding registers 41a.
Since it is connected to the outputs of ~ 41d, even if the read state ends, the inside of the control IC 2 of this example is stored in the storage block 32.
It can be set according to the initial data set in. further,
Since the storage block 32 is not energized for a short period of time when the read pulse signal R / P is at a high level, the control IC
The power required to set 2 can be minimized.

A selection signal is written in the memory block 32 using the timing charts shown in FIGS. 4 and 5, and
The process of reading the set selection signal will be described. Figure 4
Shows the process of writing data to the memory block 32. First, at time t1, the reset signal REST (bar)
Is input, the shift register 40 is reset. Then, the read enable signal R / P is output at the time t2 delayed by the delay circuit 51 of the initial setting circuit 50, whereby the pulsed read signal R is generated. Next, from time t3, the memory circuit 30 is transferred via the external terminal T7 of the control IC 2.
A data input signal is supplied to the data input terminal DATA-IN. At the same time, the clock signal is supplied to the clock terminal CLOCK of the memory circuit 30 via the external terminal T8 of the control IC 2. As a result, the data input signal can be serially input to the shift register 40.

The data input signal shown in FIG. 4 is (1010).
Therefore, when the data input signal is input together with the clock signal, the register outputs F0 to F3 of the shift register 40 become (1010). Since the setting of the shift register 40 is completed at time t4, the contents of the shift register outputs F0 to F3 are checked. Since data is irreversibly written in the memory block 32 using the fuse 34, it is desirable to check the register output before changing the resistance value of the fuse 34 by the write pulse signal W / P (bar). . Temporarily storing the data to be written in the storage block 32 by the shift register 40 also allows the serial transfer of a plurality of data to reduce the number of input terminals, and the data loaded before writing the data in the storage block 32 can be reduced. There is also an advantage in terms of confirmation.

When the confirmation of the data loaded in the shift register 40 is completed, an intermediate level signal is supplied to the external terminal T6 of the control IC 2 to bring it into a write enable state. Further, at time t5, a high level signal is supplied to the external terminal T4, and a write enable signal is sent from the W / G terminal to the memory circuit 3.
0 to supply the write signal W to a high level. As a result, the fuse selection transistors 36 of the fuse blocks 34a and 34c are turned on according to the corresponding register outputs F0 and F2. The fuse selection transistors 36 of the fuse blocks 33b and 33d do not turn on because the corresponding register outputs F1 and F3 are low level.

Next, a write pulse signal is supplied to the write pulse terminal W / P (bar) of the memory circuit 30 via the external terminal T9 of the control IC 2. This write pulse signal applies a voltage of about −10 V to −20 V across the fuse and is set according to the shape of the fuse. This write pulse signal is applied to the fuse selection transistors 36a to 36d.
Is applied to the fuses 34 of the fuse blocks 33a and 33c, and the resistance value of these fuses 34 changes from low resistance to high resistance. Therefore,
After time t6 when the write pulse signal is applied, the fuses in the fuse blocks 33a and 33c change to high resistance. If the write enable input supplied to the external terminal T6 or T4 is stopped at time t7, the write signal W
Goes low and the writing is completed.

After that, the storage block 32 will be described later.
This state is preset in the shift register 40, and it is confirmed whether or not the states of the fuse blocks 33a to 33d are set according to the input data. Since the memory states of the fuse blocks 33a to 33d appear in the resistance value of the fuse 34, the written state can be confirmed by measuring the current value flowing through the fuse 34.
Then, when the resistance value of each fuse 34 does not change according to the input data, the above steps are repeated to write in the memory block 32. By repeating the above steps, the setting of the storage block 32 can be surely performed.

FIG. 5 shows a step of reading the selection signal set in the memory block 32. First, time t11
When the reset signal REST (bar) is input to, each of the registers 41a to 41d can be reset. Next, time t1
When the pulsed read permission signal R / P output from the delay circuit 51 of the initial setting circuit 50 is input to the memory circuit 30, the read control circuit 45 outputs the pulsed read signal R / P.
Can be supplied. As a result, each fuse block 33
The gates 35a and 35b of a to 33d are turned on, and a current flows through each fuse 34. Each fuse block 33a
The output of 33d differs depending on whether the fuse 34 has a high resistance or a low resistance. In this example, since the resistance value of each fuse 34 is set as described above, the outputs of the fuse blocks 33a to 33d are (1010). These bit signals are input to the preset terminals of the registers 41a to 41d of the corresponding shift register 40, so that the shift register 40 can be set to (1010). When the read signal R becomes low level at time t13, the gates 35a and 35b of each fuse block are
Turns off and no current flows through the fuse 34. However, since the shift register 40 is set corresponding to the state of each fuse 34, each of the registers 41a ...
At the output terminals F0 to F3 of the storage circuit 30 connected to 41b, the selection signal according to the data set in the storage block 32 appears. Since the data in the shift register 40 does not change until it is reset at time t14, the input / output attribute of the control IC can be determined by each selection signal supplied from the storage circuit 30.

In this example, although the fuse used in the fuse block is of a type in which the resistance value fluctuates, it is of course possible to use a type of fuse that is cut by the voltage for writing. Further, it is also possible to use an aluminum wire that is opened by a writing voltage, a contact between aluminum wires, or the like as a fuse.

Further, the setting method for such a resistance memory element is also effective for a memory element such as EEPROM or EPROM.

[0064]

As described above, the information recording apparatus according to the present invention makes it possible to determine the interface specifications such as the attributes of input / output terminals and the setting of address terminals in the control IC. Therefore, the external terminal of the control IC and the interface connector can be directly connected, and a versatile information recording device can be realized without using mechanical switches such as a jumper set. Therefore, according to the present invention, it is possible to reduce the space occupied by these switches and the wiring related to the switches, so that the size and weight of the information recording apparatus can be reduced. it can. Further, since the number of parts constituting the information recording device can be reduced, the manufacturing cost can be reduced and the reliability can be improved. Further, since the attribute of the terminal can be determined inside the control IC, the number of external terminals of the control IC can be reduced and the size of the control IC can be reduced.

Further, a fuse, an EEPROM, an EPR
A resistance memory element such as an OM is used so that a selection signal for determining an attribute can also be held in the control IC. Therefore, the configuration of the information recording device is simple and suitable for information processing devices of recent miniaturization. It is possible to realize various information recording devices. In addition, by using the shift register as a temporary storage means for writing and reading, the resistance storage element and the EEPRO can be reliably performed.
Data can be set in storage elements such as M and EPROM, and the number of terminals of the control IC can be reduced. Further, it has various effects as disclosed above, such as limiting the time for which a current is passed through the memory element and reducing the current consumption for determining the specifications. The present invention enables miniaturization and functions. Also, a highly reliable information recording device can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a magnetic recording device according to an embodiment of the invention.

FIG. 2 is a circuit diagram showing an outline of an input / output circuit of the magnetic recording device shown in FIG.

3 is a circuit diagram showing an outline of a storage circuit of the magnetic recording device shown in FIG.

FIG. 4 is a timing chart showing a step of setting data in the memory circuit shown in FIG.

5 is a timing chart showing a process of reading data from the memory circuit shown in FIG.

[Explanation of symbols]

 1 ... Magnetic recording device 2 ... Control IC 3 ... Interface connector 5 ... Interface control circuit 6 ... System control circuit 10 ... Input / output circuit 11 ... Input / output switching block 12-16 ... Selector 17, 22 .. Resistance adjustment circuit 20 .. Address selection block 23 .. Enable signal output circuit 30 .. Memory circuit 32 .. Memory block 34 .. Fuse 36 .. Fuse selection transistor 40 .. Shift register 50 .. Initial setting Circuit 60 ... Address switch

Claims (16)

[Claims] 1. An information recording device having a control integrated circuit device for controlling information between a stored recording medium and an external information processing device, wherein the control integrated circuit device has at least one internal input and one internal output. Interface control means for controlling input / output, and input / output connectable to an external terminal of the control integrated circuit device by selecting at least one internal input or internal output from the internal input and the internal output. An information recording apparatus comprising: a selection unit. 2. The control integrated circuit device according to claim 1, further comprising resistance value adjusting means capable of selecting a terminating resistance value of the external terminal according to a selection situation of the input / output selecting means. Information recording device. 3. The input / output selection means according to claim 1 or 2, wherein the input / output selection means is selector means that can be switched by a selection signal, and the control integrated circuit device can store and output the selection signal. An information recording apparatus comprising means. 4. An information recording device having a control integrated circuit device for controlling information between a stored recording medium and an external information processing device, wherein the control integrated circuit device is connected to an external information processing device. An information recording apparatus having a selection signal storage means capable of storing and outputting a selection signal for selecting the logic of the signal or the operating speed. 5. The specification according to claim 3 or 4, wherein the control integrated circuit device has at least one specification setting input means, and a plurality of levels of signals can be applied to switch the specification setting input selecting means. An information recording device comprising: a setting signal applying unit; and a permitting unit that enables reading and writing of the selection signal storage unit by a signal of an intermediate level applied to the specification setting signal applying unit. 6. The control integrated circuit device according to claim 3 or 4, further comprising a plurality of address input means for inputting a plurality of address signals used for selecting the information recording device, and further inputting these addresses. Address input selection means for selecting one of the means to connect to the address internal input of the interface control means, address selection signal application means capable of applying a plurality of levels of signals for switching the address input selection means, and this address An information recording apparatus, comprising: an enabling unit that enables reading and writing of the selection signal storage unit by an intermediate level signal applied to the selection signal applying unit. 7. The method according to claim 5 or 6, wherein writing to the selection signal storage means or reading from the selection signal storage means is performed by a part of a signal from the permission means and a connection signal with an external information processing device. An information recording apparatus having means for enabling the information recording apparatus. 8. The information recording apparatus according to claim 3 or 4, wherein the selection signal storage means has a temporary storage means capable of setting a signal for controlling the write control means. 9. The information recording apparatus according to claim 8, wherein the temporary storage means can be preset by the selection signal reproduced in the selection signal storage means. 10. The selection signal storage means according to claim 3, wherein the selection signal storage means includes a resistance storage element whose resistance value changes when a write voltage is applied, and write control means capable of turning on / off the write voltage. An information recording apparatus comprising: 11. The read control means capable of turning on / off a read current supplied to the selection signal storage means, and the read current reproduced in the selection storage means according to claim 3. An information recording apparatus comprising: a temporary storage unit capable of storing the selection signal. 12. The initial setting means according to claim 11, wherein the control integrated circuit device outputs a pulse signal for turning on the read control means a predetermined time after a reset signal for resetting the control integrated circuit device. An information recording device comprising: 13. The selection signal storage means according to claim 11, wherein the selection signal storage means has a plurality of storage elements and write control means, and further has a shift register capable of setting a bit signal for controlling each of the write control means. An information recording device characterized by. 14. The information recording device according to claim 13, wherein the shift register can be preset by the selection signal reproduced by the storage element corresponding to each bit. 15. An information recording device having a control integrated circuit device for controlling information between a stored recording medium and an external information processing device, wherein the control integrated circuit device controls an input / output. And a plurality of address input means for respectively inputting a plurality of address signals used for selecting the information recording device, and address input selection means for selecting one of these address input means and connecting it to the address internal input of the interface control means. And an resistance value adjusting means capable of selecting a termination resistance value of each of the address input means according to a selection situation of the address input selecting means. 16. A method of setting an information recording device having a control integrated circuit device for controlling information between a stored recording medium and an external information processing device, comprising: selecting signal storage of the control integrated circuit device. When setting in the means, first, based on the pre-setting step of loading the selection signal from the outside into the temporary storage means and confirming the signal output from the temporary storage means, based on the signal set in the temporary storage means. An information recording apparatus comprising: a writing step of controlling a writing voltage to change a resistance value of a resistance memory element of the selection signal memory means; and a verification step of determining a resistance value of the resistance memory element. Setting method.