JPH0727479B2 - Microprogram logic verification method - Google Patents

Description

The present invention relates to a microprogram logic verification method, and more particularly to a microprogram emulation method suitable for verifying microprogram logic in various execution environments. is there.

[Conventional technology]

Conventionally, in order to pseudo-execute H / W logic at the LSI gate level, as shown in FIG. 9, an execution format is executed on a logic simulator 93 composed of a program group called a pseudo procedure described in a dedicated language. After the conversion processing of the micro program 91 is performed by the conversion processing program 92, the verification of the micro program is performed by a method of pseudo execution at the signal level.

As a related micro program verification method,
For example, as described in JP-A-62-290944 and JP-A-62-293357, the validity of logic is confirmed by operating a microprogram on a target computer system or a gate level logic simulator. The method is known.

[Problems to be Solved by the Invention]

The above-mentioned conventional technique is premised on the existence of a target computer system or a gate-level logic simulator, and no consideration is given to the microprogram verification before the completion of the system or the simulator and further on the hardware logic specification.

In view of the above-noted conventional consideration, the purpose of the present invention is to construct a pseudo hardware environment at the time when the microprogramming specification is decided, and to perform the early logic verification of the microprogram efficiently and highly accurately. It is to provide a microprogram logic verification method.

[Means for Solving the Problems]

In order to achieve the above object, the microprogram logic verification method of the present invention is a verification method in which a microprogram is run in a pseudo environment equivalent to a target computer system to perform logic verification, and means for storing hardware information and a microprogram A means for storing the source, a means for recording the microprogram specification information, a means for storing the test program, and a means for pseudo-executively executing an instruction group that is not subject to microprogram emulation in the computer system. It is characterized in that it is provided with a means for setting a test environment consisting of and a means for simulating the microprogram source in order.

The hardware information is composed of control interface information between the hardware and the microprogram, and hardware registers, latches, and memory. The means for simulating the microprogram source in order unit is hardware environment setting. Specification information read from the means for initializing based on the information, the means for controlling the timing of the pseudo operation, the microprogram source is read in step units, divided into order units, and the microprogram specification information is stored. It is also characterized in that it is provided with means for sequentially executing the following, and means for registering the executed microprogram source step.

[Action]

According to the present invention, when the microprogram is simulated, the microprogram source step is divided into orders, the specification information corresponding to the micro instruction issued in each order is extracted, and the data transfer level pseudo process is executed according to the specification information. To do.

Thereby, the verification of the microprogram can be performed without waiting for the determination of the hardware logic specification at the time when the microprogramming specification is determined. Further, since the processing is simulated on an order-by-order basis, the microprogram can be verified in detail at the order level.

〔Example〕

An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of a microprogram logic verification system (microprogram emulation system) showing an embodiment of the present invention.

In FIG. 1, 11 is a test program file storing a program for testing a target function, 12 is an instruction interpreter, 13 is an initial setting section for setting initial conditions (test environment), and 14 is a microprogram. A microinstruction simulator unit that pseudo-executes the source in order, 15 is a post-processing unit that performs interrupt processing, order update, microprogram source step read address update, and the like. 16 is an operation timing for each microinstruction simulation. A processing control unit that has a function to specify and an interactive processing function with an operator and performs various kinds of processing control, 17 is an interface information file storing control interface information between hardware and a microprogram, and 18 is a microprogram source. Microprogram source information file that stores, 19 is a microphone A microprogram specification information file that stores program specification information, 20 is a pseudo register / latch that realizes the register / latch of the target computer system by software, 21 is a pseudo memory that realizes the memory of the target computer system by software, and 22 is A terminal for interactively performing microprogram logic verification, and a printer 23 for outputting a processing result.

FIG. 2 is a diagram showing an example of the contents of the interface information file 17 of FIG.

In the interface information file 17, as shown in FIG. 2, a mnemonic and an instruction code corresponding to the target instruction, and hardware setting information for executing the instruction (initial value of pseudo register / latch, initial of pseudo memory). (Value) etc. are stored.

FIG. 3 is a diagram showing an example of the contents of the microprogram source information file 18 of FIG.

In the microprogram source information file 18, as shown in FIG. 3, the source steps of the microprogram (self address, branch address, process 1 (order 1), process 2 (order 2), ...) Are described. ing. This source information is not limited to this example, and can be described in a form depending on the use of the micro programming language.

FIG. 4 is a diagram showing an example of the contents of the microprogram specification information file 19 of FIG.

In the micro program specification information file 19, as shown in FIG. 4, micro instruction names and operation descriptions corresponding to each order are written. The microprogram emulation operation of this embodiment will be described below.

After loading the program for testing the target function from the test program file 11 into the pseudo memory 21, the instruction interpreter 12 executes the instruction group that is not the target of the micro program emulation in an interpretive manner. For the instruction to be emulated by the micro program, the instruction interpreter 12 issues the micro program execution instruction to start the pseudo execution, and the initial condition when the instruction is executed is extracted from the interface information file 17 and initialized. Part 13 is pseudo register / latch
20, register to the pseudo memory 21. In the micro instruction simulation section 14, the micro program source information file
The micro program source information is read from 18 in step units, divided into order units, the corresponding specification information is read from the micro program specification information file 19 according to the micro instruction issued in each order, and the pseudo register / The data transfer of the latch 20 and the pseudo memory 21 is executed. In the post-processing unit 15, interrupt processing when an interrupt factor occurs in the micro instruction simulation unit 14,
When the order is updated, the micro program source step read address is updated, and all the orders of the relevant step are processed, when the next micro program source step read address setting and the end of all the relevant step processing are detected, the target instruction execution is completed and control is performed. To the command interpreter 12. In the processing control unit 16, in response to a human intervention request from the terminal 22, the processing in the microinstruction simulating unit 14 and the post-processing unit 15 is interrupted midway, and the pseudo register / latch 20 and the pseudo memory at that time are interrupted. 21 content on terminal 22
Alternatively, output or writing to the printer 23 is performed.

FIG. 5 is a processing flowchart of the processing setting unit 13 in FIG. The initial setting process will be described below according to the flow of FIG.

The hardware environment setting information when the command is issued is read from the interface information file 17 (step 50
1) Write to the relevant pseudo register, latch, and pseudo memory (step 502).

FIG. 6 is a microinstruction simulating section in FIG.
14 is a processing flowchart of 14. The microinstruction simulation will be described below according to the flow of FIG.

The micro program step is read from the micro program source information file 18 (step 601), this is divided into order units (step 602), and the corresponding micro instruction operation specifications are read from the micro program specification information file 19 (step 603). , Data transfer between pseudo registers and latches, and pseudo memory according to the operation specifications.

FIG. 7 is a processing flowchart of the post-processing unit 15 in FIG. The post-processing will be described below according to the flow of FIG.

The microinstruction simulating unit 14 determines whether or not an interrupt factor has occurred (step 701), and if it has, sets an interrupt flag (step 702), and after all orders have been completed (step 703), the interrupt flag If is ON (step 705), the break-in destination address is set (step 710), and the process is terminated. Further, the end judgment of all orders is performed (step 703), and if all orders are not ended, the order read address is updated (step 70).
Four). If the interrupt factor is OFF (step 705), it is determined whether all steps are completed (step 706). If not all steps are completed, the step read address is updated (step 707). When all steps are completed, the next execution address is set to the next address of the target instruction (step 70
8) Return control to instruction interpreter (step 70)
9).

FIG. 8 is a processing flowchart of the processing control unit 16 in FIG. The process control will be described below according to the flow of FIG.

The addresses of the processing steps are registered in the processing order until the processing is completed (step 801). When an operator intervention request or address compare stop condition occurs (step 802,
803), according to the operator request (805) from the terminal, processing such as compare stop address designation, display of pseudo register or latch information, rewriting, display of pseudo memory information, rewriting, and the processing step registered in step 801. Then, processing such as coverage of test data, calculation and display of performance value of microprogram, designation of data transfer timing when simulating microinstruction is executed (step 804).

As described above, in the present embodiment, the verification of the microprogram can be performed without waiting for the determination of the hardware logic specification at the time when the microprogramming specification is determined.

〔The invention's effect〕

As described above, according to the present invention, the microprogram operating environment can be easily determined when the microprogramming specification is determined, so that the microprogram can be executed regardless of the hardware logic development process of the target computer system. It is possible to perform verification while operating, and it is possible to perform microprogram early development and efficient and highly accurate verification, as compared with conventional methods.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a microprogram logic verification method showing an embodiment of the present invention, FIG. 2 is a diagram showing an example of contents of the interface information file of FIG. 1, and FIG.
FIG. 4 is a diagram showing an example of the contents of the microprogram source information file of FIG. 4, FIG. 4 is a diagram showing an example of the contents of the microprogram specification information file of FIG. 1, and FIG. FIG. 6 is a processing flowchart of the microinstruction simulator in FIG.
FIG. 7 is a processing flowchart of the post-processing section in FIG. 1, FIG. 8 is a processing flowchart of the processing control section in FIG. 1, and FIG. 9 is a diagram for explaining a conventional program logic verification method. 11: Test program file, 12: Instruction interpreter, 1
3: Initial setting section, 14: Micro instruction simulation section, 15: Post processing section, 16: Processing control section, 17: Interface information file, 18: Micro program source information file, 19: Micro program specification information file, 20: Pseudo register / latch, 21: pseudo memory, 22: terminal, 23: printer.

Claims (3)

[Claims] 1. In a verification method for running a microprogram in a pseudo environment equivalent to a target computer system to perform logic verification, means for storing hardware information, means for storing microprogram source, and microprogram specification information. A means for storing a test program, a means for storing a test program, and a means for setting a test environment comprising means for interpretively simulating an instruction group that is not subject to microprogram emulation in the computer system. A microprogram logic verification method comprising means for pseudo-executing a program source on an order-by-order basis. 2. The microprogram logic verification method according to claim 1, wherein the hardware information comprises control interface information between the hardware and the microprogram, and a hardware register, a latch, and a memory. 3. The means for quasi-executing the microprogram source in order unit comprises means for initializing based on hardware environment setting information, means for controlling timing of quasi operation, and stepping the microprogram source. It is characterized in that it is provided with means for reading in units, dividing into order units, sequentially executing according to the specification information read from the means for storing the microprogram specification information, and means for registering the executed microprogram source step. The microprogram logic verification method according to claim 1.