JPH07274166A - Device for efficiently encoding and decoding video and scramble and descramble system therefor - Google Patents

Abstract

PURPOSE:To stably encode variable length without varying a generated code quantity even at the time of scramble processing. CONSTITUTION:A video signal is DCT-processed by DCT device 16, quantized by a quantizer 17, variable-length-encoded by a variable length encoder 26, and sent to a transmission line through a multiplexer 27 and an output buffer 28. Either one or the combination of data or vector encoding data in the variable length coder 26, a processing discrimination signal in the DCT device, quantization control information and data conversion control information in the quantizer 17 or a motion vector searching range information in a motion vector detector is scrambled to one optional bit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scrambling system in a high efficiency coding system for video signals.

[0002]

2. Description of the Related Art In a high-efficiency video coding system for moving images such as a television signal (hereinafter abbreviated as TV signal), DCT (intermediate frame predictive coding including motion compensation such as MPEG2 standard) is used. A method combining discrete cosine transform) processing is widely adopted. It is highly conceivable that pay broadcasting will be performed even in digital TV broadcasting using this method. In this case, as for security of the video signal transmission, it is conceivable to use the scramble technique as in the conventional analog TV broadcasting.

An example of the configuration of a video high-efficiency coding device that can be considered when the scramble technology is introduced into the video high-efficiency coding device will be described below with reference to FIG. The inter-frame predictive coding method uses the fact that the correlation between video signals of consecutive frames is generally large, and the difference signal between the current frame and the previous frame is coded to reduce temporal redundancy. is there. Furthermore, in the case of a pattern with a relatively large motion, a method of motion compensation is combined to determine the direction and size of the motion between the current frame and the previous frame (hereinafter, motion vector).
Is detected and the signal of the previous frame is corrected to further compress information.

First, the operation of the interframe coding process will be described. In FIG. 14, a video signal is input to the input terminal 11. This input video signal is input to the input buffer 12
Given to. The input buffer 12 divides the input video signal into a subtractor 13 and a motion vector detection device 14 for each predetermined pixel unit (pixel block) and outputs the divided video signal. Subtractor 1
3 is also given the motion-compensated block data (prediction signal) of the previous frame from the motion compensation predictor 15, and obtains a difference signal (prediction error signal) from the block data of the input signal, DC via terminal b of switch 23
Input to the T unit 16. The DCT unit 16 performs a two-dimensional DCT (discrete cosine transform) process on the input block data, converts it into horizontal and vertical DCT frequency components, and outputs it to the quantizer 17. The quantizer 17 quantizes the output of the DCT unit 16 and outputs it to a scrambler 18 (described later) and an inverse quantizer 19.

The inverse quantizer 19 inversely quantizes the output of the quantizer 17 and supplies it to the inverse DCT unit 20. The inverse DCT unit 20 performs inverse DCT processing on the output of the inverse quantizer 19 and adds it to the adder 21.
Output to. The prediction error signal is decoded by these processes.

The adder 21 adds the block data (prediction signal) of the motion-compensated previous frame from the motion-compensation predictor 15 via the terminal b of the switch 24 and the difference data from the inverse DCT unit 20 to add the current frame. The input block data of is reproduced and output to the frame memory 22. The frame memory 22 delays the input block data for one frame period and stores it as the previous frame data in the motion compensation predictor 15
And output to the motion vector detection device 14.

The motion vector detecting device 14 receives the block data of the current frame from the input buffer 12 and the block data of one frame before from the frame memory 22, which are used as input data and reference data, respectively. The motion vector detection device 14 obtains a motion vector between the current frame and the previous frame for the input block data, and outputs it to the motion compensation predictor 15 and the variable length encoder 26. The motion compensation predictor 15 is supplied with the block data of the previous frame from the frame memory 22, and the block data of this block data is motion-compensated by the above-described motion vector, so that the subtracter 1 as a prediction signal.
It is designed to output to 3.

The above is the operation when the motion compensation interframe predictive coding is performed. In addition, in a motion compensation interframe predictive coding apparatus for video signals, generally, in order to avoid accumulation and propagation of errors and the like caused by transmission, cyclically forced intraframe direct coding processing (intra processing) is performed. In addition, the intra-frame direct encoding process is performed even when the motion compensation prediction is greatly deviated.

Then, the operation of the intra-frame direct encoding process will be described below. In this case, switch 2 in FIG.
3 falls to the terminal a, and the output signal of the input buffer 12 is directly input to the DCT device 16. Then, it is converted into a DCT conversion frequency component and output to the quantizer 17. The quantizer 17 quantizes each of the above components and outputs them to a scrambler 18 (described later) and an inverse quantizer 19. The inverse quantizer 19 inversely quantizes the output of the quantizer 17 and inverse DC
The inverse DCT unit 20 applies the inverse DCT processing to the output of the inverse quantizer 19 and outputs the output to the adder 21. The input signal is decoded by these processes.

In this case, the adder 21 does not input the motion-compensated block data (prediction signal) of the previous frame from the motion compensation predictor 15 when the switch 24 falls to the terminal a. Therefore, only the data from the inverse DCT device 20 is output to the frame memory 22 via the adder 21 as a reproduction signal of the input block data of the current frame.

The above is the operation when the intra-frame direct encoding processing is performed. In the intra / inter processing decision unit 25, in principle, the variance of the input signal and the prediction error signal is compared and the smaller one is selected as to whether the intra-frame direct coding process or the inter-frame predictive coding process is performed. The switches 23 and 24 are controlled so as to operate.

The video signal quantized in the motion compensation interframe predictive coding apparatus is scrambled by the scrambler 18.
In the variable length encoder 26, the video signal is basically two-dimensional Huffman encoded, and the DPCM component of the motion vector is also variable length encoded using the Huffman encoding, and is output to the multiplexer 27. It The multiplexer 27 multiplexes the variable length data, the fixed length intra / inter processing determination signal, and the quantization information signal for determining the quantization step width, and outputs the variable length bit stream data to the output buffer 28. The coding rate controller 29 outputs the quantized information signal, and the quantizer 17 outputs the quantized information signal according to the occupied amount of the output buffer 28.
Also, the size of the quantization step width of the inverse quantizer 19 is determined, and the output buffer 28 is controlled so that variable-length bit stream data is output at a constant rate.

Here, the configuration of the scrambler 18 will be described with reference to FIG. In FIG. 15, the scramble block selector 21 designates the area to be scrambled on the screen in block units, and the AND circuit 23
To enter. The scramble frequency selector 22 designates the DCT frequency component to be scrambled within the screen in the block and inputs it to the AND circuit 23 as well.
The AND circuit 23 designates the DCT frequency component in the designated block and generates a scramble control signal. And
In the AND circuit 25, the pseudo random number output of the PN generator 24 is generated as noise, which is controlled by the output of the AND circuit 23 and input to the adder 26. The adder 26 adds the noise output and the output of the quantizer 17 in the motion compensation predictive coding device, encrypts the video signal, and outputs the encrypted video signal to the variable length coder 26 in the subsequent stage.

As described above, in the high-efficiency video coding apparatus, it is possible to scramble an arbitrary pixel block area on the screen and encrypt the video signal. However, in the above case, since the scrambled quantized video signal is variable-length coded, the consistency with the two-dimensional Huffman coding table used at the time of variable-length coding is deteriorated, and the coding efficiency is increased. Will cause a decrease in.

[0015]

When the scrambled video data is variable-length coded in the high-efficiency video coding apparatus, the consistency with the variable-length coding table is deteriorated, and the coding efficiency is lowered. Therefore, there is a problem in that the image quality of the encoded moving image itself deteriorates.

Therefore, according to the present invention, the generated code amount does not change even if scramble processing is performed, and a stable variable length coding can be performed, a high efficiency video coding apparatus and a scramble system therefor, and a video height corresponding thereto. An object is to provide an efficient decoding device and a descrambling method.

[0017]

[Means for Solving the Problems]

(Sign bit of non-zero coefficient) Image division means for dividing the input video signal into a plurality of pixel blocks, orthogonal transformation means for performing an orthogonal transformation process on each of the pixel blocks or each of the pixel blocks further divided into a plurality of the pixel blocks, Video high efficiency having a quantizing means for quantizing each orthogonal transform coefficient obtained in the orthogonal transforming means and a variable length coding means for variable length coding the output of the quantizing means by a two-dimensional Huffman coding process. The encoding device is provided with scrambling means for bit-inverting the code bits of the fixed-length non-zero coefficient generated during the two-dimensional Huffman encoding process.

(Fixed-length code part of two-dimensional Huffman code) Image dividing means for dividing an input video signal into a plurality of pixel blocks, and orthogonal transformation processing is performed for each of the pixel blocks or each of the pixel blocks obtained by further dividing the pixel block. Orthogonal transforming means, quantizing means for quantizing each orthogonal transform coefficient obtained by the orthogonal transforming means, and variable length coding means for variable-length coding the output of the quantizing means by two-dimensional Huffman coding processing. And a scramble means for bit-reversing at least one bit of a fixed-length code part of 1 bit or more generated in the two-dimensional Huffman coding process.

(Motion vector) A motion vector for obtaining a motion vector between an image dividing means for dividing an input video signal into a plurality of pixel blocks and a prediction signal for each of the pixel blocks or each of the pixel blocks obtained by further dividing the plurality of pixel blocks. In a video high efficiency coding device having a detection means, a motion compensation means for performing motion compensation prediction of a prediction signal based on the obtained motion vector, and a motion vector coding means for coding the motion vector, a motion vector code At least one of the fixed-length code parts of 1 bit or more generated during the coding process
A scramble means for bit-reversing one bit is provided.

(DCT processing identification signal) An image dividing means for dividing an input video signal into a plurality of pixel blocks, and the pixel block having a frame structure for each of the pixel blocks or each of the pixel blocks obtained by further dividing the pixel block into a plurality of pixel blocks has a field structure. Pixel block conversion means for converting into pixel blocks, and orthogonal transformation determination means for determining which of the frame structure and field structure orthogonal transformation processing is to be applied,
A video high-efficiency encoding apparatus having a pixel block selection unit that selects the pixel block having either a frame structure or a field structure based on the result of the orthogonal transformation determination unit, and an orthogonal transformation unit that performs an orthogonal transformation process,
A scramble means for bit-inverting the orthogonal transformation process identification signal indicating the result of the orthogonal transformation determination means is provided.

(Quantization Information Signal) Image dividing means for dividing the input video signal into a plurality of pixel blocks, and orthogonal transformation means for performing an orthogonal transformation process on each of the pixel blocks or each of the pixel blocks further divided into a plurality of blocks. In a high-efficiency video coding apparatus having a quantizing means for quantizing each orthogonal transform coefficient obtained by the orthogonal transforming means, among the quantized information signals having a fixed length of 1 bit or more for determining a quantizing step width, Scrambling means is provided for bit-reversing at least one bit.

(Quantization Characteristic Table Identification Signal) Image dividing means for dividing the input video signal into a plurality of pixel blocks,
Video high efficiency having orthogonal transform means for performing orthogonal transform processing on each of the pixel blocks or pixel blocks obtained by further dividing the pixel blocks, and quantizing means for quantizing each orthogonal transform coefficient obtained by the orthogonal transform means. The encoding device is provided with a scramble means for bit-reversing at least one bit of the fixed-length quantization characteristic table identification signal of 1 bit or more for identifying the quantization characteristic table used for quantization.

(Scan Order Identification Signal) Image division means for dividing the input video signal into a plurality of pixel blocks, and orthogonal transformation means for performing an orthogonal transformation process on each of the pixel blocks or each of the pixel blocks further divided into a plurality of blocks. Video height having quantizing means for quantizing each orthogonal transform coefficient obtained in the orthogonal transforming means, and variable length coding means for variable length coding the output of the quantizing means by two-dimensional Huffman coding processing. The efficiency coding apparatus is provided with a scramble means for bit-reversing at least one bit of the scan order identification signal of 1 bit or more for identifying the order of scanning the pixel block data at the time of quantization or variable length coding.

(Motion vector search range information signal) A motion vector between an image dividing means for dividing an input video signal into a plurality of pixel blocks and a prediction signal for each of the pixel blocks or each of the pixel blocks obtained by further dividing the plurality of pixel blocks. In a video high efficiency coding apparatus, the motion vector detecting means for obtaining the motion vector, the motion compensating means for performing motion compensation prediction of the prediction signal based on the obtained motion vector, and the motion vector coding means for coding the motion vector A scramble means for bit-reversing at least one bit of the fixed-length motion vector search range information signal of 1 bit or more indicating the motion vector search range is provided.

(Combination) A scramble means combining one or more of the above is provided. Also, by sharing the scramble control means to be used, the number of scramble control means that is smaller than the number of combinations of scramble means is provided.

In any of the above cases, it is also possible to provide a control means for controlling whether or not to perform bit inversion, or an area designating means for designating a frame to be scrambled or a local area in the frame.

The bit inversion may be determined by generation of a pseudo random number, and a threshold value designating means may be provided for designating a threshold value for determining presence / absence of bit inversion for the generated pseudo random number.

The decoding side has a descrambling method and means for correcting the inversion bit based on the scramble signal indicating the presence / absence of bit inversion corresponding to the above-mentioned video high efficiency encoding device.

[0029]

[Action]

(Sign bit of non-zero coefficient) The generated code length does not change by providing scrambling means for bit-reversing the code bit of the non-zero coefficient of fixed length generated in the two-dimensional Huffman coding process, and The coded bitstream syntax does not need to change either. On the receiving side, if the bit inverted based on the inversion information of the encoded bit is not corrected and is decoded as it is, the orthogonal transform coefficient cannot be correctly reproduced, and the image quality of the encoded video signal to be transmitted is not deteriorated and scrambled. Can be realized.

(Fixed-length code part of two-dimensional Huffman code) 2
The generated code length does not change by providing scrambling means for bit-reversing at least one bit of the fixed-length code part of 1 bit or more generated in the dimension Huffman coding process, and the coded bit stream -There is no need to change the syntax. On the reception side, if the bit inverted based on the inversion information of the encoded bit is not corrected and is decoded as it is, the orthogonal transform coefficient, for example, the DC component of the intra-frame direct encoding cannot be correctly reproduced, and the code to be transmitted is transmitted. Scramble can be realized without deteriorating the image quality of the encoded video signal.

(Motion Vector) The generated code length is changed by providing scrambling means for bit-reversing at least one bit of the fixed-length code part of 1 bit or more generated in the motion vector coding process. In addition, the coded bitstream syntax does not need to be changed. On the receiving side, if the bit inverted based on the inversion information of the encoded bit is not corrected and decoded as it is, the motion vector cannot be correctly reproduced, and the image quality of the encoded video signal to be transmitted is not deteriorated and scrambled. realizable.

(DCT processing identification signal) By generating scrambling means for inverting the bit of the orthogonal transformation processing identification signal indicating the result of the orthogonal transformation determination means, the generated code length does not change, and the coded bit stream is obtained. -There is no need to change the syntax. On the receiving side, if the bit inverted based on the inversion information of the encoded bit is not corrected and decoded as it is, the video signal cannot be correctly reproduced by the inverse orthogonal transform, and the image quality of the encoded video signal to be transmitted is impaired. It is possible to realize scrambling without using it.

(Quantization Information Signal) The generated code is generated by providing scrambling means for bit-reversing at least one bit of the quantization information signal having a fixed length of 1 bit or more for determining the quantization step width and encoding it. The length does not change and the coded bitstream syntax does not need to change. On the receiving side, if the bit inverted based on the inversion information of the encoded bit is not corrected and is decoded as it is, the dequantized video signal cannot be reproduced correctly, and the image quality of the encoded video signal to be transmitted is impaired. It is possible to realize scrambling without using it.

(Quantization characteristic table identification signal) A scramble means for bit-reversing at least one bit of the quantization characteristic table identification signal having a fixed length of 1 bit or more for identifying the quantization characteristic table used in quantization. By providing and encoding, the generated code length does not change, and the encoded bitstream syntax does not need to be changed. On the receiving side, if the bit that is inverted based on the inversion information of the encoded bit is not corrected and is decoded as it is, the video signal cannot be correctly reproduced during dequantization, and the image quality of the encoded video signal to be transmitted is reduced. Scramble can be realized without spoiling.

(Scan Order Identification Signal) A scramble means for bit-reversing at least one bit of the scan order identification signal of 1 bit or more for identifying the order of scanning the pixel block data at the time of quantization or variable length coding. By providing and coding, the generated code length does not change, and the coded bitstream syntax does not need to be changed. On the receiving side, if the bit inverted based on the inversion information of the encoded bit is not corrected and is decoded as it is, the result of dequantization is that the video signal cannot be correctly reproduced, and the image quality of the encoded video signal to be transmitted. The scrambling can be realized without spoiling.

(Motion vector search range information signal) By providing a scramble means for bit-reversing at least one bit of the fixed-length motion vector search range information signal of 1 bit or more indicating the motion vector search range, the coding is performed. The generated code length does not change, and the coded bitstream syntax does not need to be changed. On the receiving side, if the bit inverted based on the inversion information of the encoded bit is not corrected and decoded as it is, the motion vector cannot be correctly reproduced, and the image quality of the encoded video signal to be transmitted is not deteriorated and scrambled. realizable.

(Combination) By providing scrambling means combining one or more of the above and encoding, it is possible to control the confidentiality of the video signal by scrambling according to the number.

Further, by sharing the scramble control means to be used and providing and coding the scramble control means of a number smaller than the number of combinations of the scramble means, the concealment of the confidentiality of the video signal by the scramble can be achieved according to the number. You can control the strength.

Further, in any of the above cases, the control setting or the size of the designated area is also provided by providing a control means for controlling whether or not to perform bit inversion, or a frame designating means for designating a scrambled frame or a local area in the frame. It is also possible to control the degree of concealment of the video signal by scrambling according to this. On the decoding side as well, the bit processing of the signal to be scrambled is sufficient, and descrambling can be realized with a simple configuration.

[0040]

Embodiments of the present invention will be described below with reference to the drawings. Here, description will be given below based on the high-efficiency video coding method of MPEG2. First, FIG. 1 shows an example of this basic configuration.

First, the operation of the interframe coding process will be described. In FIG. 1, a video signal is input to the input terminal 11. This input video signal is given to the input buffer 12. The input buffer 12 divides the input video signal into a subtractor 13 and a motion vector detecting device 14 for each predetermined pixel unit (pixel block), and outputs the divided video signal. Subtractor 13
Is also given motion-compensated block data (prediction signal) of the previous frame from the motion compensation predictor 15, and obtains a difference signal (prediction error signal) from the block data of the input signal, and switches DCT via terminal b of 23
Input to the container 16. The DCT unit 16 performs a two-dimensional DCT (discrete cosine transform) process on the input block data, converts it into horizontal and vertical DCT frequency components, and outputs it to the quantizer 17. The quantizer 17 is the DCT device 1
The output of No. 6 is quantized and output to the variable length encoder 26 and the inverse quantizer 19.

The inverse quantizer 19 inversely quantizes the output of the quantizer 17 and supplies it to the inverse DCT unit 20. The inverse DCT unit 20 performs inverse DCT processing on the output of the inverse quantizer 19 and adds it to the adder 21.
Output to. The prediction error signal is decoded by these processes.

The adder 21 adds the block data (prediction signal) of the motion-compensated previous frame from the motion compensation predictor 15 via the terminal b of the switch 24 and the difference data from the inverse DCT unit 20 to add the current frame. The input block data of is reproduced and output to the frame memory 22. The frame memory 22 delays the input block data for one frame period and stores it as the previous frame data in the motion compensation predictor 15
And output to the motion vector detection device 14.

The motion vector detecting device 14 receives the block data of the current frame from the input buffer 12 and the block data of one frame before from the frame memory 22, which are used as input data and reference data, respectively. The motion vector detection device 14 obtains a motion vector between the current frame and the previous frame for the input block data, and outputs it to the motion compensation predictor 15 and the variable length encoder 26. The motion compensation predictor 15 is supplied with the block data of the previous frame from the frame memory 22, and the block data of this block data is motion-compensated by the above-described motion vector, so that the subtracter 1 as a prediction signal.
It is designed to output to 3.

The above is the operation when the motion-compensated interframe predictive coding is performed. Further, in a motion-compensated interframe predictive coding apparatus for video signals, generally, in order to avoid accumulation and propagation of errors and the like caused by transmission, cyclically forced intraframe direct processing (intra processing) is performed. In addition, the intra-frame direct encoding process is performed even when the motion compensation prediction is greatly deviated.

Then, the operation of the intra-frame direct encoding process will be described. In this case, the switch 23 of FIG.
Goes to the terminal a, and the output signal of the input buffer 12 is directly input to the DCT device 16. Then, it is converted into a DCT conversion frequency component and output to the quantizer 17. The quantizer 17 quantizes each of the above components and outputs them to the variable length encoder 26 and the inverse quantizer 19. Inverse quantizer 1
Reference numeral 9 is an inverse DCT device 20 which inversely quantizes the output of the quantizer 17.
And the inverse DCT device 20 outputs the inverse D to the output of the inverse quantizer 19.
It is subjected to CT processing and output to the adder 21. The input signal is decoded by these processes.

In this case, for the adder 21,
The motion-compensated block data (prediction signal) of the previous frame from the motion compensation predictor 15 is not input because the switch 24 is tilted to the terminal a. Therefore, the inverse DCT device 2
Only the data from 0 is passed through the adder 21 as a reproduction signal of the input block data of the current frame and the frame memory 22.
Output to.

The above is the operation when the intra-frame direct encoding processing is performed. Then, the intra / inter processing determination unit 25 compares the variances of the input signal and the prediction error signal and selects the smaller one in principle as to whether to perform the intra-frame direct coding process or the inter-frame predictive coding process. The switches 23 and 24 are controlled so as to operate.

Now, the video signal quantized in the motion compensation interframe predictive coding apparatus is the variable length encoder 26.
In, the video signal is basically two-dimensional Huffman coding,
Regarding the motion vector, the DPCM component is also variable-length coded by using Huffman coding and output to the multiplexer 27. The multiplexer 27 multiplexes the variable length data, the fixed length intra / inter processing determination signal, and the quantization information signal for determining the quantization step width, and outputs the variable length bit stream data to the output buffer 28. The coding rate controller 29 outputs the quantized information signal, determines the size of the quantization step width of the quantizer 17 and the dequantizer 19 according to the occupied amount of the output buffer 28, and outputs the quantized step width. The buffer 28 is controlled so that variable length bit stream data is output at a constant rate.

The above is a basic configuration example of the MPEG2 video high efficiency coding system. FIG. 2 shows an example of the configuration of a decoding device for the encoding device. The encoded bit stream data is output from the input terminal 31 to the demultiplexer 33 via the input buffer 32. The demultiplexer 33 separates the multiplexed encoded bitstream data into variable-length DCT coefficients before multiplexing, a motion vector and a fixed-length intra / inter processing determination signal, and a quantized information signal, respectively, and a variable-length decoder 34, Inverse quantizer 3
5, output to the switch 38. The variable length decoder 34 decodes the video signal and the motion vector and outputs them to the inverse quantizer 35 and the motion compensation predictor 39. Then, the inverse quantizer 35 quantizes the DCT based on the quantized information signal.
The coefficient data is inversely quantized, and its output is decoded into a prediction error signal or a direct signal through the inverse DCT unit 36. Then, this signal, together with the motion-compensated prediction signal from the motion-compensated predictor 39, which is input through the terminal b of the switch 38 when the inter-frame predictive coding process is performed on the basis of the intra / inter-process determination signal in the adder 37 It is added and output. If the code is directly encoded in the frame, the switch 38 falls to the terminal a and is output as it is. The input signal is decoded by these processes. The signal of the adder 37 is delayed by one frame period via the frame memory 40 and output to the motion compensation predictor 39. Then, the motion compensation predictor 39 motion-compensates the output of the frame memory 40, which is the image data of the previous frame, by the decoded motion vector from the variable-length decoder 34, and uses it as the next prediction signal.

The above is the description of the MPEG2 decoding apparatus. (Embodiment 1) As Embodiment 1, a scrambling method applied to a code bit of a non-zero coefficient, a fixed length code part of a two-dimensional Huffman code and a fixed length code part of a motion vector will be described.

The quantized DCT coefficient is variable-length coded in the variable-length coding by Huffman-coding the combination of the zero run length and the non-zero coefficient having the sign bit (two-dimensional Huffman coding). . In particular, the intra-processed DC component is separately converted into a combination of a fixed length part and a variable length part and encoded. In addition, the motion vector is also converted into a combination of the fixed length part and the variable length part after the DPCM processing, and then encoded.

For reference, FIGS. 16, 17, and 18 show a normal DCT coefficient coding table, an intra DC component coding table, and a motion vector coding table, respectively. 3 and 4 are respectively the variable length encoder of FIG.
2 shows a configuration in which the variable length decoder of 1 has a scramble circuit and a descramble circuit.

First, regarding the variable length encoder of FIG.
The quantized DCT coefficient output from the quantizer 17 of FIG. 1 is input to the input terminal 41. This signal is separated into an intra DC component and other components by referring to the intra / inter discrimination signal input from the input terminal 43 in the intra DC component separation circuit 42, and the intra DC component difference processing circuit 44 and the run length code, respectively. Output to the digitization circuit 45.

In the intra DC component difference processing circuit 44, the intra DC processed immediately before is basically processed in block units.
A difference is obtained by using the component as a predictor, and the difference signal is converted into a variable-length size signal component indicating its magnitude and a fixed-length additional difference signal component, and the encoding table reference circuit (LU
T) 46. Of these, a bit inversion process is performed on an arbitrary bit of the fixed-length additional difference signal component, for example, MSB. That is, this MSB is input to the exclusive OR gate 47, and the output of the pseudo random number generation circuit 48 which is the other input controls whether or not the bit is inverted.

Here, the pseudo random number generation circuit 48 outputs the value of 0 or 1 as a random number to the exclusive OR gate 47 as it is. A threshold value is set when a decimal value between 0 and 1 is generated, and for example, 1 is output when a value larger than the threshold value is generated, and 0 is output otherwise. . If the threshold value is set small, the frequency of bit inversion processing becomes small and the confidentiality of the video signal can be weakened. Conversely, if the threshold value is set large, the confidentiality can be strengthened.

As a result, the fixed-length code part of the bit-inverted two-dimensional Huffman code is scrambled, and this intra DC component is coded by the coding table reference circuit (LUT) 46, and in FIG. It is output to the multiplexer 27 shown. At this time, the seed for random number generation is also output from the pseudo random number generation circuit 48 to the multiplexer 27 as a scramble decoding signal (key signal).

The quantized DCT transform coefficient components other than the intra DC component input to the run length coding circuit 45 are converted into non-zero coefficients (representing levels) and preceding zero run lengths by the zero run length coding process. The converted Huffman coding table reference circuit (LUT) 49
Is output to. The exclusive OR gate 5 is applied to the 1-bit sign bit of the non-zero coefficient generated at this time.
The scrambling process similar to the case of the intra DC component is performed using 0 and the pseudo random number generation circuit 51, and output to the multiplexer 27. Then, the pseudo random number generation circuit 5
The seed of random number generation of 1 is also output to the multiplexer 27 as a scramble decryption signal (key signal).

Further, regarding the motion vector coding, the motion vector output from the motion vector detecting device 14 of FIG. 1 is input to the input terminal 52. In the motion vector difference processing circuit 53, the difference between the motion vector and the motion vector of the immediately preceding macroblock is basically taken in macroblock units, and after the modulo operation is performed, a fixed-length difference component and a variable length variable are obtained. And the residual component of. Then, the motion vector coding table reference circuit (LUT) 5
4 and encoded. Of these bits, an arbitrary bit of the fixed-length difference component, for example, LSB, is scrambled by the exclusive OR gate 55 and the pseudo random number generation circuit 56 in the same manner as in the above case, and is output to the multiplexer 27. To be done. Then, the pseudo random number generation circuit 5
The random number generation seed 6 is output to the multiplexer 27 as a scramble decryption signal (key signal).

Next, a variable length decoder having a descramble circuit for the scrambled signal will be described with reference to FIG. In the variable length decoder of FIG. 4, the variable length coded DC output from the demultiplexer 33 of FIG.
The intra DC component of the T coefficient and the other components are input to the input terminals 61 and 62, respectively.

The intra DC component is Huffman-decoded by the decoding table reference circuit 64 corresponding to the encoding table reference circuit (LUT) 46 shown in FIG. 3 to restore the variable length size signal component and the fixed length additional difference signal component. , Bits to be inverted of the fixed-length additional differential signal component (in this case, MS
The signal except for B) is output to the intra DC component addition processing circuit 67. The bit to be inverted of the fixed difference additional difference signal component is input to one of the exclusive OR gates 66. The pseudo random number generation circuit 65 receives the random number seed obtained by scrambling the signal component as a scramble decoding signal, and generates the same random number as the pseudo random number generator 48 of FIG. Then, this output is input to the other side of the exclusive OR gate 66 together with the target bit (MSB in this case) of the fixed-length additional difference signal component as a control signal for inverting the bit and inverted. Intra DC component addition processing circuit 6
Output to 7. The intra DC component addition processing circuit 67 adds the intra DC components that have been subjected to the difference processing in FIG. 3 to restore the original intra DC components, and outputs them to the intra DC component incorporation circuit 68.

Next, the components other than the intra DC are Huffman-decoded by the decoding table reference circuit 69 corresponding to the encoding table reference circuit (LUT) 49 of FIG. 3 and re-converted into the non-zero coefficient and the preceding zero run length. , The non-zero coefficient code bits are output to the run-length decoding circuit 70. The sign bit of the non-zero coefficient is input to one of the exclusive OR gates 71. Further, the pseudo random number generator 72 receives a random number seed in which the sign bit of the non-zero coefficient is scrambled as a scramble decoding signal, and generates the same random number as the pseudo random number generator 51 in FIG. Then, this output is input to the other side of the exclusive OR gate 71 together with the sign bit of the non-zero coefficient as a control signal for whether or not to invert the bit, and the inverted target bit is corrected and run-length decoded. Circuit 7
Output to 0. The run length decoding circuit 70 performs a run length decoding process on the basis of the above signal, restores the original DCT coefficient component, and outputs it to the intra DC component incorporating circuit 68.

The intra DC component incorporating circuit 6
In 8, when the intra DC component is intra processed with reference to the intra / inter processing determination signal, the DCT coefficient is completely variable length decoded by incorporating it into the original position. And it outputs to the dequantizer 35 of FIG.

As for the motion vector, the coded motion vector output from the demultiplexer 33 in FIG. 2 is input to the input terminal 63. The motion vector decoding table reference circuit 73 corresponding to the motion vector coding table reference circuit (LUT) 54 of FIG. 3 reconverts the fixed-length difference component and the variable-length residual component into the fixed-length difference component. The bits to be scrambled (LSB in this case) are removed and output to the motion vector addition processing circuit 74. The scramble target bit of the fixed length difference component is input to one of the exclusive OR gates 75. The pseudo random number generator 76 receives a random number seed obtained by scrambling the sign bit of the non-zero coefficient as a scramble decoding signal, and generates the same random number as the pseudo random number generator 56 of FIG. Then, this output is input to the other side of the exclusive OR gate 75 together with the scramble target bit of the fixed length difference component as a control signal for bit inversion, and the inverted target bit is corrected. It is output to the motion vector addition processing circuit 74. In the motion vector addition processing circuit 74, after performing the modulo operation, the addition process is performed with the motion vector of the immediately preceding macro block which is basically subjected to the difference process in macro block units, and the motion vector is decoded. Then, it is output to the motion compensation predictor 39 in FIG.

(Embodiment 2) Next, as a second embodiment, DCT
A method of scrambling the process identification signal will be described.

In MPEG2, when a video signal is an interlaced input, a method of merging two fields forming one frame to form a frame structure and performing an encoding process is often adopted. Then, at this time, as shown in FIG. 5, it is determined whether the DCT processing in frame units or the original DCT processing in field units is performed for each processing pixel block (16 × 16 pixel blocks in this case). -By executing, it is possible to reduce the coding distortion of the decoded image. However, the DCT processing is performed in 8 × 8 pixel block units, and the hatch portion is an odd field line,
The white part represents the even field lines.

FIGS. 6A and 6B show the configurations of the DCT device having the scramble circuit and the inverse DCT device having the descramble circuit in this case, respectively. Figure 6
In the DCT device of (a), the video signal from the switch 23 of FIG. 1 is input to the input terminal 81. This signal is input to the selection circuit 82 and the processing unit conversion circuit 83. Also, the frame / field processing determination circuit 8
It is also input to 4. In the processing unit conversion circuit 83,
As shown in FIG. 5B, line-based rearrangement is performed to form a field-based block, and the rearranged signal is input to the selection circuit 82. In the selection circuit 82, either one of the above two input signals is converted into a DC signal according to the determination result of the frame / field processing determination circuit 84.
The T circuit 85 is selected and supplied. Then, the DCT circuit 8
In 5, DCT processing is performed in 8 × 8 pixel block units,
The resulting DCT coefficient is supplied to the quantizer 17 of FIG. Now, the output (1 bit) of the frame / field processing determination circuit 84 is subjected to bit inversion processing immediately before being output to the multiplexer 27 of FIG. This signal is input to the exclusive OR gate 86, and the output of the pseudo random number generation circuit 87, which is the other input, controls whether or not the bit is inverted. As a result, the bit-inverted scan sequential identification signal is scrambled, and the seed for random number generation of the pseudo random number generation circuit 87 is also output to the multiplexer 27 as a scramble decoding signal (key signal).

Next, in the inverse DCT device of FIG. 6B, the video signal from the inverse quantizer 35 of FIG.
Enter in 8. In the inverse DCT circuit 89, this signal is
Inverse DCT processing is performed in units of 8 × 8 pixel blocks and output to the selection circuit 90 and the processing unit conversion circuit 91. In the processing unit conversion circuit 91, line-by-line rearrangement is performed in order to reconfigure from field unit to frame unit block, contrary to the process shown in FIG.
It is output to the selection circuit 90. The DCT process identification signal which is the inversion target bit is input from the input terminal 92 and input to one of the exclusive OR gates 93. Further, the pseudo random number generating circuit 94 receives this signal component from the scrambled random number seed input terminal 95 as a scramble decoding signal, and the pseudo random number generating circuit 87 of FIG. 6A.
Generates the same random number as. Then, this output is input to the other of the exclusive OR gates 93 as a control signal for whether to invert the bit, and the inverted DCT processing identification signal is corrected and output as the control signal of the selection circuit 90. To do. As a result, the output of the selection circuit 90 is restored to the original frame structure even for the pixel block subjected to the DCT processing in the field unit, and is output to the adder 37 of FIG.

(Third Embodiment) Next, as a third embodiment, a method of scrambling a scan order identification signal, a quantization characteristic table identification signal and a fixed length quantized information signal will be described.

In the MPEG2 video high-efficiency coding system, 8
The two-dimensional data of the × 8 pixel block is sequentially scanned from the low-frequency component to the high-frequency component of the DCT coefficient region to be one-dimensional,
Performs quantization and variable length coding. As for this scan order, as shown in FIG. 7, a zigzag scan order from MPEG1 for ensuring compatibility with MPEG1 and a new scan order corresponding to the interlaced structure are defined. To identify this, the encoder transmits a scan order identification signal (1 bit). As for the quantization characteristic table, as shown in FIG.
In addition to those having uniform quantization step widths, the tables having different quantization step width intervals are prepared, and the quantization characteristic table identification signal (1 bit) is transmitted. Further, for the quantized information signal, 31 steps can be selected for determining the quantization step width, and it is transmitted with a fixed length of 5 bits.

9 and 10 show examples of the configurations of the quantizer having the scramble circuit of FIG. 1 and the dequantizer having the descramble circuit of FIG. 2, respectively. First, for the quantizer of FIG. 9, the DCT coefficient from the DCT device 16 of FIG. 1 is input to the input terminal 101. This signal is converted into one-dimensional data in the zigzag scan order and the new scan order by the first scanning circuit 102 and the second scanning circuit 103, respectively, and input to the selection circuit 104. The selection circuit 104 selects a scan order designated in advance by the scan order identification signal and outputs it to the first quantization characteristic table reference quantization circuit 105 and the second quantization characteristic table reference quantization circuit 106. In the first quantization characteristic table reference quantization circuit 105 and the second quantization characteristic table reference quantization circuit 106, quantization is performed with reference to the quantization step width linear characteristic table and the quantization step width non-linear characteristic table, respectively. And outputs it to the selection circuit 107. For the quantization, the coding rate controller 29 of FIG.
The fixed length quantization information (5 bits) input from the input terminal 108 is used. Then, the selection circuit 107 selects and outputs one of them based on the quantization characteristic table identification signal.

The scan order identification signal is subjected to bit inversion processing immediately before being output to the multiplexer 27 of FIG. That is, the signal is input to the exclusive OR gate 111, and the output of the pseudo random number generation circuit 112, which is one of the inputs, controls whether or not the bit is inverted. As a result, the bit-inverted frame / field DCT processing identification signal is scrambled, and the seed for random number generation of the pseudo random number generation circuit 112 is also output to the multiplexer 27 as a scramble decoding signal. This is also the case with the quantization characteristic table identification signal, similarly to the exclusive OR gate 113 and the pseudo random number generation circuit 11.
4 and then scrambled and output. Furthermore, for a fixed-length quantized information signal, any bit (for example, MSB) of 5 bits can be used as an inversion target. Of course more than one is possible. When only the MSB is to be inverted, this signal is the exclusive OR gate 11
5 and the output of the pseudo random number generation circuit 116 which is the other input controls whether or not the bit is inverted. As a result, the bit-inverted quantized information signal is scrambled, and the seed for random number generation of the pseudo random number generation circuit 116 is also output to the multiplexer 27 as a scramble decoding signal.

Next, in the inverse quantizer of FIG. 10, the video signal from the variable length decoder 34 of FIG.
Through the first quantization characteristic table reference dequantization circuit 2
02 and the second quantization characteristic table reference dequantization circuit 203. The first quantization characteristic table reference dequantization circuit 202 and the second quantization characteristic table reference dequantization circuit 203 respectively include a first quantization characteristic table reference dequantization circuit 105 and a second quantization characteristic table dequantization circuit 105 of FIG. It corresponds to the quantization characteristic table reference quantization circuit 106, and outputs the output after the inverse quantization processing to the selection circuit 204. For dequantization, fixed length quantization information (5 bits) input from the demultiplexer 33 of FIG. 2 via the input terminal 205 is used. However, since this MSB is bit-inverted and scrambled, the pseudo random number generator 206 and the exclusive OR gate 207 are
Is descrambled in. That is, the scrambled random number seed is received as a scrambled decoded signal from the input terminal 208, and the pseudo random number generation circuit 11 of FIG.
Generate the same random number as 6. Then, the output of the pseudo random number generation circuit 206 is input to the other of the exclusive OR gates 207 as a control signal for determining whether or not to invert the bit, and the inverted MSB is corrected to be a quantized information signal. First quantization characteristic table reference inverse quantization circuit 2
02 and the second quantization characteristic table reference dequantization circuit 203. Further, in the selection circuit 204, the input terminal 2
The output of the selection circuit 204 is selected based on the quantization characteristic table information signal input from the demultiplexer 33 of FIG. However, also in this case, since the quantization characteristic table information signal is scrambled, the scramble decoding signal is received from the random number seed input terminal 212, and the same random number as the pseudo random number generating circuit 114 of FIG. 213.

Then, this output is input to the other of the exclusive-OR gates 214 as a control signal for bit inversion, and the inverted quantization characteristic table information signal is corrected to select circuit 204. Output as a control signal of. Further, this selection output signal is output to the first reverse scanning circuit 215 and the second reverse scanning circuit 216. First reverse scanning circuit 215 and second reverse scanning circuit 2
16 corresponds to the first scanning circuit 105 and the second scanning circuit 106 of FIG. 9, respectively, and is converted into the original data array in the zigzag scan order and the new scan order, respectively.
The output is input to the selection circuit 217. In the selection circuit 217, the scan order identification signal, which is its output control signal, is scrambled at the time of being input from the input terminal 218. Therefore, the scramble decoding signal is received from the random number seed input terminal 219, and the pseudo random number generation circuit 220 is received.
At, the same random number as that of the pseudo random number generation circuit 112 of FIG. 9 is generated. Then, this output is input to the other side of the exclusive OR gate 221 as a control signal for whether or not to invert the bit, and the inverted scan order identification signal is corrected and output as the control signal of the selection circuit 217. To do. Then, the selection circuit 217 selects and outputs one of them based on the correct identification signal.

(Embodiment 4) Next, a method of scrambling the motion vector search range information signal will be described.

The motion vector search range information is normally used as a 3-bit fixed-length signal for designating the motion vector search range. It is also used for modulo arithmetic in motion vector variable length coding. The decoding device decodes the motion vector based on this information. The configurations of the scramble circuit of the encoding device and the descramble circuit of the decoding device at this time are shown in FIGS. 11A and 11B, respectively.

First, in the encoding device, the motion vector search range information is output to the motion vector detecting device 14 and the variable length encoder 26 of FIG. And multiplexer 2
Immediately before input to 7, scramble processing is performed. Any bit of this 3-bit signal, for example MSB
Is input to one of the exclusive OR gates 301 as a bit to be scrambled. The other of the exclusive OR gates 301 has a pseudo random number generation circuit 302.
The output of is input to control whether or not to perform bit inversion. The output of the exclusive OR gate 301 is output to the multiplexer 27 as a scrambled motion vector search range information signal. Also, the pseudo random number generation circuit 3
The random number generation seed 02 is output to the multiplexer 27 as a scramble decoding signal.

Next, in the decoding device, as shown in FIG. 11B, the scrambled motion vector search range information signal is output from the demultiplexer 33 in FIG. Then, at the time of descrambling, the bit to be scrambled (MSB in this case) of this signal is input to one of the exclusive OR gates 305. The pseudo random number generation circuit 306 receives a random number seed corresponding to the pseudo random number generation circuit 302 of FIG. 11A as a scramble decoding signal from the demultiplexer 33 of FIG. 2 and generates the same random number as the pseudo random number generation circuit 302. Let Then, this output is input to the other side of the exclusive OR gate 305 together with the scramble target bit of the motion vector search range information signal as a control signal for whether or not the bit is inverted, and the inverted target bit is corrected. The motion vector search range information signal is correctly restored and the variable length decoder 3 of FIG.
Output to 4. The variable length decoder 34 decodes the motion vector based on this information.

(Embodiment 5) In Embodiments 1 to 4,
A scramble circuit and a descramble circuit that invert the target bit by a pseudo random number (see FIGS. 1 to 11).
However, the scramble circuit and the descramble circuit shown in FIG. 12 may be used in place of these.

In FIG. 12 (a), the pseudo random number generation circuit 351 and the output of the local area designating circuit 352 are logically ANDed by a logical product gate 353 to scramble the video signal to the local area in the designated frame. Call. And in this circuit, the seed of pseudo random number generation is the key signal,
The local area designation (for example, slice upper limit value, lower limit value, etc.) is output to the multiplexer as a subkey signal.
Then, in the descramble circuit of FIG. 9B, the pseudo random number generation circuit 361 receives the key signal from the demultiplexer, generates a random number of the same seed as on the scramble side, and outputs it to the AND gate 363. Further, the local area designating circuit 362 receives the subkey signal from the demultiplexer to generate the same local area designating control signal as on the scramble side, which is also output to the AND gate 363. The logical product gate 363 can perform a logical product of the above signals to perform the descrambling process of the scrambled signal on the local area in the designated frame.

FIG. 13 shows a configuration example of a local area designating circuit in a frame. In the pulse generator 442, the input end 441
Slice pulses and macroblock (hereinafter referred to as MB) pulses are generated from the video signal input to the counters 443 and 444, respectively. Slice counter 443
Then, the slice pulse is counted up, the number of slices is counted, and reset is applied for each frame. This counter output is compared with the preset upper and lower limit values of the slice in the comparator 445, and if it is within this range, 1 is output, and if it is outside this range, 0 is output to the AND gate 447. The MB counter 444 counts up the MB pulse to count the number of MB, and resets with the slice pulse. This count number is compared with a preset MB upper limit value and lower limit value in the comparator 446, and if it is within this range, 1 is output, and if it is outside this range, 0 is output to the comparator 447. Then, the AND gate 447 outputs 1 if the above comparator outputs match, and 0 otherwise. As a result, an arbitrary local area in the frame can be designated in slice units and MB units.

The advantages of each of the above-described embodiments can be summarized as follows. However, in each case, a slight increase in the information band generated due to the transmission of the key signal is excluded. (Sign bit of non-zero coefficient) The generated code length does not change by providing scrambling means for bit-reversing the code bit of the non-zero coefficient of fixed length generated in the two-dimensional Huffman coding process, and The coded bitstream syntax does not need to change either. On the receiving side, if the bit inverted based on the inversion information of the encoded bit is not corrected and is decoded as it is, the orthogonal transform coefficient cannot be correctly reproduced. As a result, scrambling can be realized without impairing the image quality of the encoded video signal to be transmitted.

(Fixed-length code part of two-dimensional Huffman code) 2
The generated code length does not change by providing scrambling means for bit-reversing at least one bit of the fixed-length code part of 1 bit or more generated in the dimension Huffman coding process, and the coded bit stream -There is no need to change the syntax. On the receiving side, if the bit inverted based on the inversion information of the encoded bit is not corrected and is decoded as it is, the orthogonal transform coefficient, for example, the DC component of the intra-frame direct encoding cannot be correctly reproduced.
As a result, scrambling can be realized without impairing the image quality of the encoded video signal to be transmitted.

(Motion Vector) The generated code length is changed by providing a scramble means for bit-reversing at least one bit in the fixed-length code part of 1 bit or more generated in the motion vector coding process. In addition, the coded bitstream syntax does not need to be changed. On the receiving side, if the bit inverted based on the inversion information of the encoded bit is not corrected and is decoded as it is, the motion vector cannot be correctly reproduced. As a result, scrambling can be realized without impairing the image quality of the encoded video signal to be transmitted.

(DCT processing identification signal) By providing scrambling means for bit-inverting the orthogonal transformation processing identification signal indicating the result of the orthogonal transformation determination means, the generated code length does not change, and the coded bit stream is obtained. -There is no need to change the syntax. On the receiving side, if the bit inverted based on the inversion information of the encoded bit is directly decoded without correction, the video signal cannot be correctly reproduced by the inverse orthogonal transform. As a result, scrambling can be realized without impairing the image quality of the encoded video signal to be transmitted.

(Quantized Information Signal) By generating a scramble means for inverting at least one bit of a fixed length quantized information signal of 1 bit or more for determining the quantization step width and encoding the generated code, the generated code is obtained. The length does not change and the coded bitstream syntax does not need to change. On the receiving side, if the bit inverted based on the inversion information of the encoded bit is not corrected and is decoded as it is, the dequantized video signal cannot be reproduced correctly.
As a result, scrambling can be realized without impairing the image quality of the encoded video signal to be transmitted.

(Quantization Characteristic Table Identification Signal) A scramble means for bit-reversing at least one bit of the quantization characteristic table identification signal having a fixed length of 1 bit or more for identifying the quantization characteristic table used at the time of quantization. By providing and encoding, the generated code length does not change, and the encoded bitstream syntax does not need to be changed. On the receiving side, if the bit inverted based on the inversion information of the encoded bit is not corrected and is decoded as it is, the video signal cannot be correctly reproduced at the time of inverse quantization. As a result, scrambling can be realized without impairing the image quality of the encoded video signal to be transmitted.

(Scan Order Identification Signal) A scramble means for bit-reversing at least one bit of the scan order identification signal of 1 bit or more for identifying the order of scanning the pixel block data at the time of quantization or variable length coding. By providing and coding, the generated code length does not change, and the coded bitstream syntax does not need to be changed. On the receiving side, if the bit inverted based on the inversion information of the coded bit is not corrected and is decoded as it is, as a result of dequantization, the video signal cannot be correctly reproduced. As a result, scrambling can be realized without impairing the image quality of the encoded video signal to be transmitted.

(Motion Vector Search Range Information Signal) By providing a scramble means for bit-reversing at least one bit of the fixed-length motion vector search range information signal of 1 bit or more indicating the motion vector search range, encoding is performed. The generated code length does not change, and the coded bitstream syntax does not need to be changed. On the receiving side, if the bit inverted based on the inversion information of the encoded bit is not corrected and is decoded as it is, the motion vector cannot be correctly reproduced. As a result, scrambling can be realized without impairing the image quality of the encoded video signal to be transmitted.

(Combination) By providing a scramble means combining one or more of the above and encoding, it is possible to control the strength of confidentiality of the video signal by scrambling according to the number.

Further, by sharing the scramble control means to be used and providing the scramble control means in a number smaller than the number of combinations of the scramble means, it is possible to secure the confidentiality of the video signal by scrambling according to the number. You can control the strength.

Further, in any of the above cases, by providing a control means for controlling whether or not to perform bit inversion, it is possible to control the confidentiality of the video signal by scrambling. Further, by providing an area designating means for designating a frame to be scrambled or a local area in the frame, the scramble area can be designated to control the confidentiality of the video signal.

[0093]

As described above, according to the present invention,
Even if scramble processing is performed, the generated code amount does not change, and it is possible to obtain a high-efficiency video coding apparatus and a scramble system thereof that can perform stable variable-length coding.

[Brief description of drawings]

FIG. 1 is a diagram showing an encoding device according to the present invention.

2 is a diagram showing a decoding device corresponding to the encoding device in FIG. 1. FIG.

FIG. 3 is a diagram showing a main part on the scramble side of the first embodiment of the present invention.

FIG. 4 is a diagram showing a main part of a descrambling side according to the first embodiment of the present invention.

FIG. 5 is an explanatory diagram showing an example of a DCT processing block.

FIG. 6 is a diagram showing a main part of a second embodiment of the present invention.

FIG. 7 is a diagram showing a scan example in the case of converting two-dimensional data into one-dimensional data.

FIG. 8 is a diagram showing an example of a quantization characteristic table.

FIG. 9 is a diagram showing a main part on a scramble side of a third embodiment of the present invention.

FIG. 10 is a diagram showing a main part of a descrambling side according to a third embodiment of the present invention.

FIG. 11 is a diagram showing a main part of a fourth embodiment of the present invention.

FIG. 12 is a diagram showing a main part of a fifth embodiment of the present invention.

13 is a diagram showing an example of a local area designating circuit in FIG.

FIG. 14 is a diagram showing a configuration of a video high efficiency encoding device having a scramble function.

15 is a diagram showing a configuration example of the scrambler of FIG.

FIG. 16 is a diagram showing a DCT coefficient coding table.

FIG. 17 is a diagram showing an intra DC component encoding table.

FIG. 18 is a diagram showing a motion vector coding table.

[Explanation of symbols]

12 ... Input buffer, 13 ... Subtractor, 14 ... Motion vector detection device, 15 ... Motion compensation predictor, 16 ... DCT device,
17 ... Quantizer, 19 ... Inverse quantizer, 20 ... Inverse DCT
21 ... Adder, 22 ... Frame memory, 23 ... Switch, 24 ... Switch, 25 ... Intra / inter decision unit, 26 ... Variable length encoder, 27 ... Multiplexer, 2
8 ... Output buffer, 29 ... Encoding rate controller, 32 ...
Input buffer, 33 ... Demultiplexer, 34 ... Variable length decoder, 35 ... Inverse quantizer, 36 ... Inverse DCT device, 37 ...
Adder, 38 ... Switch, 39 ... Motion compensation predictor, 40
... Frame memory, 42 ... Intra DC component separation circuit,
44 ... Intra DC component difference processing circuit, 45 ... Run length encoding circuit, 46, 49, 54 ... Encoding table reference circuit (LUT), 47, 50, 55 ... Exclusive OR gate, 48, 51, 56 ... Pseudo-random number generation circuit, 53 ... Motion vector difference processing circuit, 64, 69, 73 ... Decoding table reference circuit, 65, 72, 76 ... Pseudo-random number generation circuit,
66, 71, 75 ... Exclusive OR gate, 67 ... Intra DC component addition processing circuit, 68 ... Intra DC component incorporation circuit, 70 ... Run length decoding circuit, 74 ... Motion vector addition processing circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI Technical indication location H03M 7/40 8842-5J H04K 1/00 Z H04N 7/167 H04N 7/167 Z (72) Invention Tatsuya Ishikawa 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Stock company Toshiba Multimedia Technology Laboratory

Claims (29)

[Claims] 1. An input video signal is divided into a plurality of pixel blocks, and each of the orthogonal transform coefficients obtained by subjecting the pixel block or a pixel block obtained by further dividing the pixel block to an orthogonal transform process is quantized, Next, in a video high-efficiency coding system for performing run-length variable-length coding, a scramble for encrypting a video signal by bit-reversing the code bits of non-zero coefficient of fixed length generated at the time of run-length variable-length coding. method. 2. An image division means for dividing an input video signal into a plurality of pixel blocks, an orthogonal transformation means for subjecting the pixel block or a pixel block obtained by further dividing the pixel block to an orthogonal transformation process, and the orthogonal transformation means. A video high-efficiency coding apparatus having a quantizing means for quantizing each of the orthogonal transform coefficients obtained in step 1 and a variable-length coding means for variable-length coding the output of the quantizing means by a two-dimensional Huffman coding process. 2. The video high efficiency coding apparatus according to claim 1, further comprising scrambling means for bit-reversing a code bit of a non-zero coefficient having a fixed length generated in the two-dimensional Huffman coding process. 3. An input video signal is divided into a plurality of pixel blocks, and each of the orthogonal transform coefficients obtained by subjecting the pixel block or a pixel block obtained by further dividing the pixel block to an orthogonal transform process is quantized, A high-efficiency video coding method for variable-length coding, in which a video signal is encrypted by bit-reversing at least one bit of a fixed-length coding unit of 1 bit or more generated at the time of variable-length coding. . 4. An image dividing means for dividing an input video signal into a plurality of pixel blocks, an orthogonal transforming means for subjecting the pixel block or a pixel block obtained by further dividing the pixel block to an orthogonal transforming process, and the orthogonal transforming means. A video high-efficiency coding apparatus having a quantizing means for quantizing each of the orthogonal transform coefficients obtained in step 1 and a variable-length coding means for variable-length coding the output of the quantizing means by a two-dimensional Huffman coding process. 3. The video high efficiency coding apparatus according to claim 1, further comprising scrambling means for bit-reversing at least one bit of the fixed-length coding part of 1 bit or more generated in the two-dimensional Huffman coding process. 5. An input video signal is divided into a plurality of pixel blocks, a motion vector is obtained between the pixel block or a prediction signal for each pixel block obtained by dividing the pixel block into a plurality of pixel blocks, and the prediction is performed using the motion vector. In a video high efficiency coding method in which a signal is corrected to create a motion-compensated prediction signal, and a difference signal between the motion-compensated prediction signal and the input signal and the motion vector are encoded and transmitted, A scramble system in which a video signal is encrypted by bit-reversing at least one bit of a fixed-length code part of 1 bit or more that occurs at the time. 6. A motion vector detecting means for calculating a motion vector between an image dividing means for dividing an input video signal into a plurality of pixel blocks and a prediction signal for each of the pixel blocks or each of the pixel blocks obtained by further dividing the plurality of pixel blocks. And a motion compensation unit that performs motion compensation prediction of a prediction signal based on the obtained motion vector, and a motion vector encoding unit that encodes the motion vector. A high-efficiency video coding apparatus comprising scrambling means for bit-reversing at least one bit of a fixed-length coding part of 1 bit or more generated during coding processing. 7. An input video signal is divided into a plurality of pixel blocks, and it is determined whether an orthogonal transformation process of a frame structure or a field structure is applied to each of the pixel blocks or each of the pixel blocks obtained by further dividing the plurality of pixel blocks. A high-efficiency video coding method that performs orthogonal transformation and coding. A scramble method that encrypts a video signal by bit-inverting an orthogonal transformation processing identification signal indicating whether the processing of the frame structure or the field structure is applied. 8. An image dividing unit for dividing an input video signal into a plurality of pixel blocks, and converting the pixel block having a frame structure into a pixel block having a field structure for each of the pixel blocks or each of the pixel blocks obtained by further dividing the plurality of pixel blocks. Pixel block conversion means, an orthogonal transformation determination means for determining which frame structure or field structure orthogonal transformation processing is to be applied, and the pixel having either a frame structure or a field structure based on the result of the orthogonal transformation determination means. A video high-efficiency coding apparatus having pixel block selection means for selecting a block and orthogonal transformation means for performing orthogonal transformation processing, wherein scrambling means for bit-inverting an orthogonal transformation processing identification signal indicating the result of the orthogonal transformation determination means is provided. A video high-efficiency encoding device having. 9. An input video signal is divided into a plurality of pixel blocks, and each of the orthogonal transform coefficients obtained by subjecting the pixel block or a pixel block obtained by further dividing the pixel block to an orthogonal transform process is quantized, In a high-efficiency video coding method for coding, a scramble for encrypting a video signal by bit-reversing at least one bit of a quantized information signal having a fixed length of 1 bit or more that determines the step size of the quantization. method. 10. An image division means for dividing an input video signal into a plurality of pixel blocks, an orthogonal transformation means for performing an orthogonal transformation process on each of the pixel blocks or each of the pixel blocks further divided into a plurality of blocks, and the orthogonal transformation means. And a quantization means for quantizing each of the orthogonal transform coefficients obtained in 1., at least one of fixed-length quantization information signals of 1 bit or more for determining the quantization step width. A high-efficiency video coding device having scrambling means for inverting two bits. 11. An input video signal is divided into a plurality of pixel blocks, and each of the orthogonal transformation coefficients obtained by subjecting the pixel block or a pixel block obtained by further dividing the pixel block to an orthogonal transformation process is quantized, In a high-efficiency video encoding method for encoding, at least one bit of a quantization characteristic table identification signal having a fixed length of 1 bit or more for identifying a quantization characteristic table used in the quantization is bit-inverted. A scramble method that encrypts video signals. 12. An image division means for dividing an input video signal into a plurality of pixel blocks, an orthogonal transformation means for performing an orthogonal transformation process on each of the pixel blocks or a pixel block obtained by further dividing the pixel block into a plurality of pixel blocks, and the orthogonal transformation means. In a video high efficiency coding apparatus having a quantizing means for quantizing each of the orthogonal transform coefficients obtained in 1., a quantization characteristic of a fixed length of 1 bit or more for identifying a quantization characteristic table used in the quantization. A video high-efficiency coding apparatus having scrambling means for bit-reversing at least one bit of the table identification signal. 13. An input video signal is divided into a plurality of pixel blocks, and each of the orthogonal transform coefficients obtained by subjecting the pixel block or a pixel block obtained by further dividing the pixel block to an orthogonal transform process is quantized. In a video high-efficiency coding method for variable-length coding, at least one bit of at least one bit of a scan order identification signal for identifying an order of scanning the pixel block data at the time of the quantization or variable-length coding is used. A scramble method that encrypts video signals by inverting the bits. 14. An image division means for dividing an input video signal into a plurality of pixel blocks, an orthogonal transformation means for performing an orthogonal transformation process on each of the pixel blocks or a plurality of pixel blocks obtained by further dividing the pixel block, and the orthogonal transformation means. A video high-efficiency coding apparatus having a quantizing means for quantizing each of the orthogonal transform coefficients obtained in step 1 and a variable-length coding means for variable-length coding the output of the quantizing means by a two-dimensional Huffman coding process. The scrambling means for bit-reversing at least one bit of the scan order identification signal of 1 bit or more for identifying the order of scanning the pixel block data at the time of the quantization or the variable length encoding. Video high efficiency coding device. 15. An input video signal is divided into a plurality of pixel blocks, a motion vector is obtained from a prediction signal for each of the pixel blocks or each pixel block obtained by dividing the pixel block into a plurality of pixel blocks, and the prediction is performed using the motion vector. A motion-compensated prediction signal is generated by correcting a signal, and in a video high efficiency coding method for coding and transmitting a difference signal between the motion-compensated prediction signal and the input signal and the motion vector, a search range of the motion vector is set. At least one of the fixed-length motion vector search range information signals of 1 bit or more shown
A scramble method that encrypts a video signal by inverting two bits. 16. A motion vector detecting means for calculating a motion vector between an image dividing means for dividing an input video signal into a plurality of pixel blocks and a prediction signal for each of the pixel blocks or each of the pixel blocks obtained by further dividing the pixel block into a plurality of pixel blocks. When,
In a video high-efficiency coding apparatus having a motion compensation means for performing motion compensation prediction of a prediction signal based on the obtained motion vector and a motion vector coding means for coding the motion vector, a search range of the motion vector is set. A high-efficiency video coding apparatus having scrambling means for bit-reversing at least one bit of a motion vector search range information signal of a fixed length of 1 bit or more shown. 17. Subtracting means for dividing a plurality of pixel blocks into which a video signal is input in pixel block units, subtracting a prediction signal from the video signal and outputting the subtracted prediction signal, and a signal on the input side or output side of the subtracting means. Is entered,
Orthogonal transform means for subjecting this input signal to orthogonal transform processing, quantizing means for quantizing each orthogonal transform coefficient obtained by the orthogonal transform means, and inverse quantum for inverse quantizing the output of the quantizing means. An output unit, an inverse orthogonal transform unit for performing an inverse orthogonal transform on the output of the inverse quantization unit, an adding unit for adding the output of the inverse orthogonal transform unit and the prediction signal, and an output of the adding unit. Storage means, a motion vector detection means for obtaining a motion vector of the image in the pixel block unit using the output of the storage means and the input video signal of the subtraction means, and the storage means of the storage means using the motion vector. A motion-compensated prediction unit that corrects the output in units of the pixel block to create the prediction signal, and an input side of the subtraction unit with respect to the orthogonal transformation unit by an intra / inter identification signal An intra / inter control means for selectively introducing a signal of the subtraction result on the force side and turning the input of the prediction signal to the adding means off and on; an output of the quantizing means; Variable length coding means for performing variable length coding by length coding or Huffman coding processing, and multiplexing means for multiplexing coded data from the variable length coding means, quantization control information, and the intra / inter identification signal Output buffer means for sending the output of the multiplexing means to a transmission line, data in the variable length coding means, an orthogonal transform processing identification signal in the orthogonal transform means, and a quantum in the quantizer. Control signal, data scan control signal in the quantization or variable length coding means, motion vector in the motion vector detection means Video high efficiency coding apparatus characterized in that a scrambling means for scrambling to any one or more of the search range signal. 18. A compressed video signal encrypted by bit-inverting a code bit of a fixed-length non-zero coefficient generated during run-length variable-length coding, and a key signal for decrypting the code are input. A descrambling method in which the compressed video signal is variable-length decoded and the code bit is returned to an original state by using the key signal. 19. A compressed video signal scrambled by bit-inversion of a code bit of a non-zero coefficient of a fixed length generated in a two-dimensional Huffman coding process by a variable length coding means, and a code for decrypting this code. Key signal is input,
A high-efficiency video decoding apparatus comprising descrambling means for variable-length decoding the compressed video signal and returning the code bit to an original state by using the key signal. 20. A compressed video signal encrypted by bit-reversing at least one bit of a fixed-length code part of 1 bit or more generated during variable-length coding, and a key signal for decrypting this code. Is descrambled, the compressed video signal is variable length decoded, and the inverted bit is returned to the original state by using the key signal. 21. A compressed video signal encrypted by bit-reversing at least one bit of a fixed-length code part of 1 bit or more generated during variable-length coding, and a key signal for decrypting this code. And a descrambling means for variable length decoding the compressed video signal and restoring the inverted bit to the original state by using the key signal. 22. An input video signal is divided into a plurality of pixel blocks, a motion vector is obtained between the pixel block or a prediction signal for each pixel block obtained by dividing the pixel block into a plurality of pixel blocks, and the prediction is performed using the motion vector. When a motion-compensated prediction signal is created by correcting a signal, and a difference signal between the motion-compensated prediction signal and the input signal and the motion vector are coded to create a transmission signal, this occurs when the motion vector is coded. At least one bit of the fixed-length code part of 1 bit or more is bit-inverted to receive an encrypted motion vector, and the key signal for decrypting the motion vector is received. To decode the input video signal from a signal,
A descrambling method in which the encrypted motion vector is restored to the original motion vector using the key signal, and the motion compensated prediction signal is reproduced using the restored motion vector. 23. An input video signal is divided into a plurality of pixel blocks, a motion vector is obtained between the pixel block or a prediction signal for each pixel block obtained by dividing the pixel block into a plurality of pixel blocks, and the prediction is performed using the motion vector. When a motion-compensated prediction signal is created by correcting a signal and a difference signal between the motion-compensated prediction signal and the input signal and the motion vector are coded to create a transmission signal, this occurs when the motion vector is coded. At least one bit of the fixed-length code part of 1 bit or more is bit-inverted to form an encrypted motion vector, and the key signal for decrypting the motion vector is received. To decode the input video signal from a signal,
A descrambling means for restoring the encrypted motion vector to the original motion vector using the key signal, and reproducing the motion compensation prediction signal using the restored motion vector. Video efficient decoding device. 24. An input video signal is divided into a plurality of pixel blocks, and it is judged whether the orthogonal transformation process of a frame structure or a field structure is applied to each of the pixel blocks or each of the pixel blocks obtained by further dividing the pixel block. To scramble the coded signal, which has been coded by orthogonal transformation, and the scrambled orthogonal transformation processing identification signal, which is bit-inverted from the orthogonal transformation processing identification signal indicating whether the processing of the frame structure or the field structure is applied, Key signal is received, and in order to decode the coded signal, the key signal is used to descramble the scramble orthogonal transform processing identification signal, and the restored orthogonal transform processing identification signal is used to perform the coding. A descrambling method characterized by performing inverse orthogonal transform processing of a signal. 25. An input video signal is divided into a plurality of pixel blocks, and it is determined whether the orthogonal transformation process of a frame structure or a field structure is applied to each of the pixel blocks or each of the pixel blocks obtained by further dividing the pixel block. To scramble the coded signal, which has been coded by orthogonal transformation, and the scrambled orthogonal transformation processing identification signal, which is bit-inverted from the orthogonal transformation processing identification signal indicating whether the processing of the frame structure or the field structure is applied, Key signal is received, and in order to decode the coded signal, the key signal is used to descramble the scramble orthogonal transform processing identification signal, and the restored orthogonal transform processing identification signal is used to perform the coding. Video high efficiency characterized by having a descrambling means for performing inverse orthogonal transform processing of signals Decoding device. 26. An input video signal is divided into a plurality of pixel blocks, and each of the orthogonal transform coefficients obtained by subjecting the pixel block or a pixel block obtained by further dividing the pixel block to an orthogonal transform process is quantized and encoded. In order to generate a coded signal, at least one bit of the quantized information signal having a fixed length of 1 bit or more that determines the quantization step width, or at least one of the quantized characteristic table identification signals. A method for processing a quantized information signal or a signal obtained by scrambling the quantized characteristic table identification signal by inverting two bits, wherein the coded signal and the scrambled quantized information signal or the quantized characteristic table identification A signal and a key signal for descrambling, for dequantizing the coded signal The descrambling method is characterized in that the scrambled quantized information signal is restored to the original quantized information signal using the key signal and is used for the dequantization. 27. An input video signal is divided into a plurality of pixel blocks, and each of the orthogonal transform coefficients obtained by subjecting the pixel block or a pixel block obtained by further dividing the pixel block to an orthogonal transform process is quantized and encoded. In order to create a coded signal, at least one bit of the quantized information signal having a fixed length of 1 bit or more that determines the step size of the quantization, or at least one of the quantized characteristic table identification signals. An apparatus for processing a quantized information signal or a signal obtained by scrambling a quantized characteristic table identification signal by inverting bits, wherein the encoded signal and the scrambled quantized information signal or quantized characteristic table identification A signal and a key signal for descrambling, for dequantizing the coded signal A scrambled quantized information signal is restored to an original quantized information signal using the key signal and is used for the dequantization. Video high efficiency decoding device. 28. An input video signal is divided into a plurality of pixel blocks, and each of the orthogonal transform coefficients obtained by subjecting the pixel block or a pixel block obtained by further dividing the pixel block to an orthogonal transform process is quantized. Variable-length coding is performed to create a coded signal, and at the time of the quantization or variable-length coding, at least one of the scan order identification signals of 1 bit or more for identifying the scan order of the pixel block data Receives a scramble scan order identification signal that is scrambled by inverting two bits, a key signal for descrambling this scramble, and the coded signal, and dequantizes the coded signal and performs inverse orthogonal transform The key signal is used to obtain the original scan identification signal from the scramble scan identification signal. A descrambling method that restores the identification signal. 29. An input video signal is divided into a plurality of pixel blocks, and each of the orthogonal transform coefficients obtained by subjecting the pixel block or a pixel block obtained by further dividing the pixel block to an orthogonal transform process is quantized, Variable-length coding is performed to create a coded signal, and at the time of the quantization or variable-length coding, at least one of the scan order identification signals of 1 bit or more for identifying the scan order of the pixel block data A device for receiving a scramble scan order identification signal which is scrambled by inverting two bits, a key signal for descrambling this scramble, and the coded signal, wherein the coded signal is inversely quantized. In order to obtain a scan identification signal necessary for inverse orthogonal transform, the scrambling scan identification is performed using the key signal. A high-efficiency video decoding device having descrambling means for restoring another signal to the original identification signal.