JPH07274163A - Device and method for encoding/decoding hierarchy and transmission/reception system - Google Patents

Abstract

PURPOSE:To reduce the transmission rate of a high hierarchy signal and to suppress the deterioration of picture quality when an error occurs in a reception- side. CONSTITUTION:A sequential scanning video signal becomes a jumping scanning video signal in a thinning circuit 111. The jumping scanning video signal becomes the sequential scanning video signal by an interpolation processing fitted to movement, is subtracted from the original sequential scanning video signal in a subtraction circuit 122, becomes a differential sequential scanning video signal and is subjected to high hierarchy-encoding. The signal subjected to low hierarchy/high hierarchy-encoding is multiplexed in a multiplex circuit 125, is modulated in a modulation circuit and is transmitted. A transmission signal is demodulated in a demodulation circuit 140, and is separated in a multiplex circuit 141. The signals of the respective hierarcies are decoded in a high hierarchy FEC decoder 142 and a low hierarchy FEC decoder 143. For adding the signal decoded on a low hierarchy-side to the signal on a high hierarchy-side, the signal converted into the sequential scanning signal by a movement adaptation processing is added.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hierarchical coding transmission system for hierarchically transmitting and decoding a video signal when the video signal is highly efficient coded for transmission, and a transmitter / receiver thereof.

[0002]

2. Description of the Related Art A video signal which is a progressive scanning signal is hierarchized into a progressive scanning signal and an interlaced scanning signal, and the progressive scanning signal is encoded as a high hierarchical signal and the interlaced scanning signal is encoded as a low hierarchical signal for transmission. There is a coding system.

FIG. 9 shows the above-mentioned hierarchical coding transmission and decoding system. A video signal which is a sequential scanning signal is input from the terminal 501. The original signal input from the terminal 501 is a vertical low-pass filter 510 and a subtractor 515.
Entered in. The video signal input to the vertical low-pass filter 510 is band-limited, and the line thinning circuit 511.
Entered in. The line thinning circuit 511 thins out every other line to generate an interlaced scanning signal. The interlaced scanning signal output from the line thinning circuit 511 is input to the low layer encoder 512 and encoded.

Here, the internal structure of the lower layer encoder 512 will be described with reference to FIG. In FIG. 10, the terminal 10
From 01, an interlaced scanning signal which is an output signal of the line thinning circuit 511 shown in FIG. 9 is input. Terminal 100
The video signal input to No. 1 is input to the pre-processing circuit 1010, and rearrangement processing is performed in block units of 8 pixels in the horizontal direction and 8 lines in the vertical direction. The video signal rearranged in block units is input to the subtractor 1011, the motion vector detection circuit 1021, and the prediction switching circuit 1022. The video signal passed through the subtractor 1011 is the DCT circuit 1
It is input to 012. The DCT circuit 1012 takes in a signal in units of blocks as described above, and outputs a coefficient obtained by converting the pixel array from the time domain to the frequency domain. Each coefficient output from the DCT circuit 1012 is quantized by a quantization circuit 1013.
Is quantized to a finite level. The data quantized by the quantization circuit 1013 is zigzag-scanned from the low band to the high band for each unit block, and is output to the variable length coding circuit 1014 and the dequantization circuit 1016. In the variable length coding circuit 1014, variable length coding is performed, and the buffer 101
Input to 5. The buffer 1015 outputs the variable rate data input from the variable length coding circuit 1014 as fixed rate data to the terminal 1003. Further, the buffer 1015 controls the quantizing circuit 1013 so that the buffer 1015 itself does not overflow. The output signal of the terminal 1003 is input to the low layer FEC encoder 518 shown in FIG.

The other output of the quantization circuit 1013 is
The data is input to the inverse quantization circuit 1016 and subjected to inverse quantization,
It is input to the inverse DCT circuit 1017. Inverse DCT circuit 10
In 17, inverse DCT processing is performed and the video signal is returned to the block unit. The block-based video signal output from the inverse DCT circuit 1017 is input to the frame memory 1019 and the post-processing circuit 1024 via the adder 1018. In the frame memory 1019, the video signal is delayed by one frame and input to the motion compensation circuit 1020 and the motion vector detection circuit 1021. Motion vector detection circuit 102
1 compares the output signal of the pre-processing circuit 1010 with the output signal of the frame memory 1019, detects the motion between frames in block units, outputs them as motion vectors, controls the motion compensation circuit 1020, and performs motion compensation. The phase position of the signal output from the circuit 1020 is adjusted. The output of the motion compensation circuit 1020 is a prediction signal in which the video signal is delayed by one frame and motion-compensated by the motion vector. The output signal of the motion compensation circuit 1020 is supplied to the subtractor 1011 via the switch 1030, the adder 1018 via the switch 1031, and the prediction switching circuit 1022. ON / OFF of the switch 1030 and the switch 1031 is controlled by a refresh signal output from the OR circuit 1023.

[0006] As means for encoding, there are intraframe compression encoding and interframe compression encoding. When intraframe compression encoding is performed, the switch 1030 and the switch 1
Both 031 are turned off. At this time, the block-based video signal output from the preprocessing circuit 1010 is DC
It is encoded through the T circuit 1012, the quantization circuit 1013, the variable length encoding circuit 1014, and the buffer 1015, and output to the terminal 1003. On the other hand, the output signal of the quantization circuit 1013 is the inverse quantization circuit 1016 and the inverse DCT circuit 101.
It is returned to the video signal in block units via 7. The video signal in block units is delayed by one frame in the frame memory 1019 via the adder 1018. Therefore, the intraframe compression encoding is equivalent to encoding the input video signal from the terminal 1001 as it is.

When interframe compression coding is performed,
Both the switch 1030 and the switch 1031 are turned on. At this time, the video signal in block units, which is the output of the preprocessing circuit 1010, takes a difference from the prediction signal motion-compensated by the motion vector of the video signal of one frame in the subtractor 1011. Therefore, the difference signal output from the subtractor 1011 becomes a prediction error signal. Subtractor 10
The prediction error signal output from 11 is the DCT circuit 101.
2, a quantization circuit 1013, a variable length coding circuit 1014,
The data is encoded via the buffer 1015 and output to the terminal 1003. On the other hand, the output signal of the quantization circuit 1013 is returned to the prediction error signal via the inverse quantization circuit 1016 and the inverse DCT circuit 1017. This prediction error signal is added to the adder 1
In 018, the video signal of the previous frame is summed with the prediction signal motion-compensated by the motion vector, and the terminal 10
A predicted video signal obtained by predicting the video signal input to 01 is created and input to the frame memory 1019.

There are two conditions for performing the intraframe compression encoding, and one is the case where the amount of data is smaller when the original signal is encoded than when the original error signal is encoded, such as at the time of a scene change. This is because the prediction switching circuit 1022 compares the original signal and the prediction error signal from the output of the preprocessing circuit 1010 and the output of the motion compensation circuit 1020. From the comparison result, it is determined that the data amount is smaller, and when it is determined that the intra-frame compression coding has the smaller data amount,
The prediction switching circuit 1022 generates an intra-frame compression flag. Secondly, if only the prediction error signal is continuously transmitted, when an error occurs in a certain frame, the error propagates to the subsequent frames. To prevent this
Intra-frame compression encoding is forcibly performed periodically (for example, once in 10 frames). This can be done by inputting a forced refresh signal from the terminal 1002. In the OR circuit 1023, the forced refresh signal input from the terminal 1002 and the prediction switching circuit 10
The switch 1030 and the switch 1031 are controlled as a refresh signal by taking the logical sum of the in-frame compression flags output from 22. The refresh signal which is the output signal of the OR circuit 1023 is multiplexed with the encoded data of the video signal and transmitted.

The post-processing circuit 1024 rearranges the video signals in block units, arranges them in the order of scanning the screen, and decodes the original video signals. The decoded video signal is sent to the terminal 10
It is output to 04. The decoded video signal output to the terminal 1004 is input to the 0-line insertion circuit 513 shown in FIG.

Returning to FIG. 9, the video signal encoded by the low layer encoder 512 is input to the low layer FEC encoder 518, subjected to error correction encoding, and input to the multiplex circuit 519. It On the other hand, from the lower layer encoder 512, the decoded video signal obtained by restoring the once encoded signal to the original is input to the 0 line insertion circuit 513. The decoded interlaced scanning signal is input to the 0 line insertion circuit 513, and 0 data is inserted between the lines.
The video signal in which 0 data is inserted between the lines is input to the vertical low pass filter 514 and becomes a sequential scanning signal.
This progressive scanning signal is a signal whose band is limited as compared with the progressive scanning signal input from the terminal 501. The subtractor 515 takes the difference between the progressive scan signal input from the terminal 501 and the band-limited progressive scan signal output from the vertical low-pass filter 514. The differential signal output from the subtractor 515 is encoded by the higher layer encoder 516. The progressive scan signal encoded by the higher layer encoder 516 is subjected to error correction encoding by the higher layer FEC encoder 517. The error-correction-coded data is input to the multiplexing circuit 519. The multiplex circuit 519 multiplexes the low layer coded data and the high layer coded data, and outputs the multiplexed data to the modulation circuit 520. Modulation circuit 52
At 0, the modulated data is output to the terminal 502, becomes a transmission signal, and is input to the reception-side terminal 503.

On the receiving side, the data from the transmitting side is sent to the terminal 5
In 03, it is received as a received signal and demodulated by the demodulation circuit 530. The demodulated data is the demultiplexing circuit 531.
Is divided into low layer encoded data and high layer encoded data, and the low layer encoded data is divided into the low layer FEC decoder 539.
And the higher layer encoded data is input to the higher layer FEC decoder 532. The low layer FEC decoder 539 performs FEC decoding and inputs the result to the low layer decoder 540. Further, the error flag is input from the low layer FEC decoder 539 to the low layer decoder 540. The error flag is a signal indicating whether or not an error has occurred in the received signal.

Here, the internal structure of the lower layer decoder 540 will be described with reference to FIG. In FIG. 11, the terminal 110
The output signal of the low-layer FEC decoder 539 is input to 1. The signal input from the terminal 1101 is stored in the buffer 11
10, variable length decoding circuit 1111, inverse quantization circuit 111
2. Decoded via the inverse DCT circuit 1113. The decoded video signal is input to the adder 1114. In the case of intra-frame compression encoding, the switch 1130 is turned off by the refresh signal input from the terminal 1103, and the adder 1114 only receives the decoded video signal output from the inverse DCT circuit 1113. . The video signal output from the adder 1114 is input to the post-processing circuit 1118 and the frame memory 1115 via the switch 1131. In the frame memory 1115, the input video signal is delayed by one frame and input to the motion compensation circuit 1116 and the switch 1131. In the motion compensation circuit 1116, motion compensation is performed by the motion vector input from the terminal 1104, and the switch 11
It is input to 30. Further, when the inter-frame compression encoding is performed, the video signal output from the inverse DCT circuit 1113 is
It is a prediction error signal. In this case, the terminal 1103
By the refresh signal input from the switch 11,
30 is turned on. Therefore, the signals input to the adder 1114 are the prediction error signal which is the output signal of the inverse DCT circuit 1113 and the prediction video signal of one frame before input via the switch 1130. The adder 1114 adds the two signals and inputs them to the post-processing circuit 1118 and the frame memory 1115 via the switch 1131. The post-processing circuit 1118 rearranges the decoded video signals in block units composed of 8 pixels in the horizontal direction and 8 lines in the vertical direction in the order of scanning the screen, and outputs them to the terminal 1105.

The error flag input from the low layer FEC decoder 539 is input to the terminal 1102 and is directly supplied to the error compensation determination circuit 1117. On the other hand, terminal 1
The refresh signal input from 103 is also input to the error compensation determination circuit 1117. Error compensation determination circuit 11
Reference numeral 17 generates a previous frame interpolation signal when a data error exceeds a certain value, and switches 1131 to terminal 11
Connect to 07 side. By this operation, the post-processing circuit 111
The video signal of one frame before, which is output from the frame memory 1115, is input to 8.

The operation relating to error compensation will be described with reference to the time chart of FIG.
FIG. 12A shows a lower layer FEC decoder 539 shown in FIG.
It is an encoded video signal input to. FIG. 12B shows an error flag output from the lower layer FEC decoder 539. Now, an error has occurred in frame P12. This error flag is fetched from the terminal 1102 shown in FIG. 11 into the error compensation judgment circuit 1117, and the error flag is counted by the internal counter of the error compensation judgment circuit 1117. Becomes The output value of this internal counter is shown in FIG.
2 (c). The internal counter is reset every refresh period, and the reset signal is as shown in FIG.
2 (d). FIG. 12E shows a terminal 1106.
3 shows a decoded video signal input to. 12
(F) is a previous frame interpolation signal generated from the output signal of the internal counter, and is output from the error compensation determination circuit 1117. While the previous frame interpolation signal is "H", the switch 1131 is tilted toward the terminal 1107, and the video signal of the previous frame is input from the frame memory 1115 to the post-processing circuit 1118. Since the previous frame interpolation signal is "H" from the frame P12 to the frame P19, error compensation is performed during this period, and the previous frame P11 is interpolated. Therefore, the video signal after the error compensation is shown in FIG. The signal shown in FIG. 12 (g) is a refresh signal input from the terminal 1103, and the refresh signal resets the previous frame interpolation signal.

The decoded video signal output to the terminal 1105 becomes the output signal of the lower layer decoder 540, and this signal is the interlaced scanning signal. This interlaced scanning signal is input to the terminal 505 and the 0 line insertion circuit 538 of FIG. Returning to FIG. 9, the line insertion circuit 538 inserts 0 data between the lines and outputs it to the vertical low-pass filter 537. Vertical low pass filter 537
Then, for the signal with 0 data inserted between the lines,
A low-pass filter is applied to produce progressive scan signals. The progressive scan signal output from the vertical low pass filter 537 is a band-limited signal, and this signal is input to the adder 536.

On the other hand, the high layer encoded data input to the high layer FEC decoder 532 is FEC decoded and input to the high layer decoder 533. The error flag output from the higher layer FEC decoder 532 is the determination circuit 53.
4 is input. In the determination circuit 534, the designated value T
When an error flag is generated with a frequency exceeding h1, the switch 535 is turned off, and when the error flag generation frequency is lower than the designated value Th2, the switch 535 is used.
A control signal for turning ON is output. Normal Th1> Th2
Therefore, the determination circuit 534 has a hysteresis characteristic. The higher layer decoder 533 decodes the encoded video signal and inputs the decoded video signal to the adder 536 via the switch 535. In the adder 536, the high layer video signal output from the high layer decoder 533 and the vertical low pass filter 537 are added.
The original progressive scan signal is output to the terminal 504 by adding the low hierarchy video signal output from the. Here, the determination circuit 534 determines that an error has occurred, and the switch 5
When 35 is turned off, the terminal 504 is supplied with a band-limited progressive scanning signal which is an output signal of the vertical low-pass filter 537.

The above is a conventional example of a hierarchical coding system in which a hierarchical scanning system and an interlaced scanning system are layered and coded. In this conventional example, when the interlaced scanning signal which is a low hierarchy signal is interpolated to produce a progressive scanning signal on the sending side, the interlaced scanning signal is interpolated in the field to produce the progressive scanning signal. The interpolated progressive scan signal has a band-limited and deteriorated image quality and becomes a blurred image as compared with the progressive scan signal which is the original signal input from the terminal 501. Therefore, the subtractor 5
The difference value output from 15 is a large value.
If this is encoded and transmitted, the transmission rate becomes high.

On the receiving side as well, when the interlaced scanning signal which is a low hierarchy signal is interpolated to produce the progressive scanning signal, the interlaced scanning signal is interpolated in the field to produce the progressive scanning signal, so that it is interpolated. The progressive scanning signal thus generated is a blurred image as compared with the progressive scanning signal of the original signal. Therefore, when an error occurs and the switch 535 is turned off and the higher layer signal is not supplied to the adder 536, the image is displayed only by the progressive scanning signal generated by interpolating the lower layer signal. . Then, the image quality deterioration when an error occurs becomes noticeable.

[0019]

As described above, in the prior art, in the system in which the interlaced scanning signal and the progressive scanning signal are layered and encoded and transmitted, the interlaced scanning signal is interpolated at the sending side to generate the progressive scanning signal. At this time, since the interpolation is performed within the field, the interpolated progressive scanning signal is a band-limited and blurred image as compared with the original scanning signal. Therefore, when the difference between the sequential scanning signal that is the original signal and the interpolated progressive scanning signal is taken and the difference value is transmitted as a higher layer signal, the difference value becomes a large value, and the transmission rate increases. There was a drawback.

Also, on the receiving side, the interlaced scanning signal is interpolated within the field to form a progressive scanning signal, so that the interpolated progressive scanning signal is compared with the original scanning signal. , The band is limited and the image is blurred. Therefore, when an error occurs in the higher layer signal and the higher layer signal is no longer supplied, the image is displayed only by the interpolated progressive scan signal. Then, the image quality deterioration when an error occurs becomes noticeable.

Therefore, the present invention provides a hierarchical coding transmission system capable of reducing the transmission rate of high-layer signals and suppressing deterioration of image quality at the receiving side when an error occurs, and a transmitting / receiving apparatus therefor. With the goal.

[0022]

According to the present invention, when an interlaced scanning signal is interpolated to form a progressive scanning signal, a motion vector output from a low hierarchy encoder is extracted and the magnitude of this motion vector is designated. When the size of the motion vector is smaller than the specified value ThB (<ThA), when the size of the motion vector is larger than the specified value ThA, interpolation between fields using the previous field, and the size of the motion vector is When it is between ThA and ThB, an interpolating means for producing a progressive scanning signal by using the inter-field interpolation and the inter-field interpolation is used.

In addition to the above-mentioned means, when interlacing an interlaced scanning signal to produce a progressive scanning signal, motion detection is performed from a decoded video signal output from a low layer encoder, and the result of this motion detection is used. Value Th with the specified amount of movement
Interpolation in the field when larger than A, interpolation between fields using the previous field when the magnitude of the motion amount is less than the specified value ThB (<ThA), and magnitudes of the motion amounts ThA and ThB If it is between the two, an interpolating means for producing a progressive scanning signal by using the inter-field interpolation and the inter-field interpolation is used.

[0024]

By using the above means, it is possible to suppress the image quality deterioration of the progressive scanning signal generated by interpolating the interlaced scanning signal. Therefore, on the sending side, the difference value between the sequential scanning signal of the original signal which is the higher hierarchy signal and the sequential scanning signal generated by interpolation is small, and the transmission rate can be lowered. Further, when the receiving side does not supply a high-level signal when an error occurs, it is necessary to display an image with a progressive scanning signal created by interpolating an interlaced scanning signal, but to prevent a sharp deterioration in image quality at that time. be able to.

[0025]

Embodiments of the present invention will be described below with reference to the drawings. (Embodiment 1) FIG. 1 shows a hierarchical coding transmission system in which an interlaced scanning signal and a progressive scanning signal are layered, coded, and transmitted.

From the terminal 101, a video signal which is a progressive scanning signal is input as an original signal. The progressive scan signal input from the terminal 101 is supplied to the vertical low-pass filter 11
0 and is input to the subtractor 122. The video signal input to the vertical low pass filter 110 is band-limited and input to the line thinning circuit 111. Line thinning circuit 11
In No. 1, the interlaced scanning signal is created by thinning out every other line. The interlaced scanning signal output from the line thinning circuit 111 is applied to the low layer encoder 11
2 and encoded.

FIG. 2 shows the internal structure of the lower layer encoder 112. In FIG. 2, an interlaced scanning signal which is an output signal of the line thinning circuit 111 shown in FIG. 1 is input to a terminal 601. The video signal input to the terminal 601 is
The data is input to the preprocessing circuit 610, and rearrangement processing is performed in block units of 8 pixels in the horizontal direction and 8 lines in the vertical direction.
The video signal rearranged in block units is subtracted by the subtractor 61.
1 and motion vector detection circuit 621 and prediction switching circuit 6
22 is input. The video signal from the subtractor 611 is
It is input to the DCT circuit 612. The DCT circuit 612 takes in a signal in units of blocks described above, and outputs a coefficient obtained by converting the pixel array from the time domain to the frequency domain.
Each coefficient output from the DCT circuit 612 is quantized to a finite level by the quantization circuit 613. Quantization circuit 61
The data quantized in 3 is zigzag-scanned from the low band to the high band for each unit block, and the variable length coding circuit 614 is used.
Is input to the inverse quantization circuit 616. The variable length coding circuit 614 performs variable length coding, and the output thereof is input to the buffer 615. The buffer 615 outputs the variable rate data from the variable length coding circuit 614 as fixed rate data, and outputs the fixed rate data to the terminal 603. Also, the buffer 6
Reference numeral 15 controls the quantization circuit 613 to prevent the buffer 615 itself from overflowing. The output signal from the terminal 603 is the low-level FEC shown in FIG.
It is input to the encoder 113. The other output of the quantization circuit 613 is input to the inverse quantization circuit 616 and subjected to inverse quantization, and its output is input to the inverse DCT circuit 617. In the inverse DCT circuit 617, inverse DCT processing is performed,
It is returned to the video signal in block units. Inverse DCT circuit 61
The video signal in block units, which is the output of No. 7, is added by the adder 61.
8 is input to the frame memory 619 and the terminal 604. In the frame memory 619, the video signal is delayed by one frame and its output is input to the motion compensation circuit 620 and the motion vector detection circuit 621. The motion vector detection circuit 621 compares the output signal of the preprocessing circuit 610 with the output signal of the frame memory 619, and in block units,
Image motion between frames is detected to obtain a motion vector, the motion compensation circuit 620 is controlled by this motion vector, and the phase position of the signal output from the motion compensation circuit 620 is adjusted. The motion vector output from the motion detection circuit 621 is derived at the terminal 605. The output of the motion compensation circuit 620 is a prediction signal in which the video signal is delayed by one frame and motion-compensated by the motion vector. The output signal of the motion compensation circuit 620 is output to the subtractor 6 via the switch 630.
11 and is supplied to the adder 6 via the switch 631.
18, and the prediction switching circuit 622 is also provided.
Is supplied to. ON / OFF of the switch 630 and the switch 631 is controlled by a refresh signal output from the OR circuit 623. When performing the intraframe compression encoding, the switch 630 and the switch 631 are selected by the refresh signal output from the OR circuit 623.
Turns OFF, and the original signal output from the preprocessing circuit 610 is directly encoded. When performing interframe compression coding, the switch 630 and the switch 631 are turned on by the refresh signal output from the logical sum circuit 623, and the subtractor 611 causes the switch 630 and the switch 631 to turn on.
The difference between the original signal output from the pre-processing circuit 610 and the signal obtained by performing motion compensation on the video signal of one frame before output from the motion compensating circuit 620 is calculated, output as a prediction error signal, and encoded. Will be.

In the prediction switching circuit 622, the prediction error signal which is the difference between the output of the preprocessing circuit 610 and the output of the motion compensation circuit 620 and the output of the motion compensation circuit 620 and the original signal are used. Certain preprocessing circuit 610
Compare the output of. If it is determined from the comparison result that the data amount is smaller, and if the intra-frame compression coding is smaller than the data amount, the prediction switching circuit 62 is used.
2, an intra-frame compression flag is generated. Further, a forced refresh signal is input from the terminal 602 in order to periodically perform intraframe compression encoding. OR circuit 623
Then, the logical sum of the forced refresh signal input from the terminal 602 and the intra-frame compression flag output from the prediction switching circuit 622 is calculated to obtain the refresh signal as
The switches 630 and 631 are controlled. The refresh signal which is the output signal of the logical sum circuit 623 is multiplexed with the encoded data of the video signal and transmitted.

Returning to FIG. 1, the video signal encoded by the low layer encoder 112 is input to the low layer FEC encoder 113, subjected to error correction encoding, and input to the multiplex circuit 125. .

On the other hand, from the low-level encoder 112, the decoded video signal obtained by restoring the once-encoded signal is restored in block units in the field memory 115 and the vertical interpolation filter 1.
16, input to the selection circuit 120. Further, the motion vector output from the lower layer encoder 112 is the coefficient circuit 1
14 is input. The coefficient circuit 114 is a circuit that outputs a coefficient in accordance with the magnitude of the motion vector, and the relationship between the magnitude of the motion vector and the coefficient value K is shown in FIG.
The coefficient value K shown in FIG. 3 is a coefficient value input to the arithmetic circuit 118, whereas the coefficient value input to the arithmetic circuit 117 is 1−K. In FIG. 3, when the value of the motion vector is lower than the specified value A, the coefficient value is K = 0, and when the value is between the specified values A and B (> A), the coefficient The value is 0 <k <1, and the specified value B
If it is greater than, the coefficient value is K = 1.

The block-based video signal input to the field memory 115 is delayed by one field and input to the arithmetic circuit 117. The arithmetic circuit 117 multiplies the coefficient output from the coefficient circuit 114 and the output signal of the field memory 115, and outputs the product to the adder 119. On the other hand, the block-based video signal input to the vertical interpolation filter 116 is subjected to vertical interpolation filter processing within the field and output to the arithmetic circuit 118. Arithmetic circuit 11
8, the coefficient output from the coefficient circuit 114 is multiplied by the output signal of the vertical interpolation filter 116, and the adder 119 is added.
Output to. The adder 119 takes the sum of the output signal of the arithmetic circuit 117 and the output signal of the arithmetic circuit 118, and outputs the sum as an interpolated video signal to the selection circuit 120.

The interpolated video signal output from the selection circuit 120 is 3 according to the coefficient value output from the coefficient circuit 114.
There are two interpolation methods. The first method is the arithmetic circuit 117.
When the coefficient output to 1 is 0 and the coefficient output to the arithmetic circuit 118 is 0. This is the lower layer encoder 112.
A value that specifies the magnitude of the motion vector output from
Is smaller than. The relationship between the motion vector and the value of the coefficient has been described above. At this time, the field memory 11
The signal of one field before output from 5 becomes an interpolation signal. This state is shown in FIG. In FIG. 4, the horizontal direction indicates the time axis direction, and the vertical direction indicates the vertical direction of the screen. When interpolation is performed as shown in FIG. 4A-1, the interpolated video signal output from the selection circuit 120 is as shown in FIG. 4A-2.

In the second method, the coefficient output to the arithmetic circuit 117 is 0 and the coefficient output to the arithmetic circuit 118 is 1.
It is time for This is a value B (> A) in which the magnitude of the motion vector output from the lower layer encoder 112 is designated.
When it is greater than. At this time, the signal output from the vertical interpolation filter 116 becomes the interpolation signal. This state is shown in FIG. 4 (c-1). When interpolation is performed as shown in FIG. 4C-1, the interpolated video signal output from the selection circuit 120 is as shown in FIG. 4C-2.

The third method is when the coefficient output to the arithmetic circuit 118 is K (0 <K <1) and the coefficient output to the arithmetic circuit 117 is 1-K. This is when the magnitude of the motion vector output from the lower layer encoder 112 is between the designated values A and B. At this time, the signal obtained by adding the signal obtained by multiplying the signal output from the vertical interpolation filter 116 by K and the signal obtained by outputting 1 field before the field output from the field memory 115 by 1−K is the interpolation signal. Become. This state is shown in FIG. 4 (b-1). When interpolation is performed as shown in FIG. 4B-1, the selection circuit 1
The interpolated video signal output from 20 is as shown in FIG. The above three interpolation methods are
It is determined by the magnitude of the motion vector output from the lower layer encoder 112.

In the selection circuit 120, the lower layer encoder 11
The block raster conversion circuit 1 selects the block-based video signal, which is the output signal of No. 2, and the interpolated video signal, which is the output signal of the adder 119, for each line alternately.
It is output to 21. The signal input to the block raster conversion circuit 121 is a sequential scanning signal created by interpolating in block units. Block raster conversion circuit 1
In 21, the video signals are rearranged in block units and output to the subtractor 122 in the order of scanning the screen.

In the subtractor 122, the interpolated progressive scan signal output from the block raster conversion circuit 121 and the sequential scan signal which is the original signal input from the terminal 101 are input and a difference value is output. . The difference signal output from the subtractor 122 is encoded by the higher layer encoder 123. The progressive scan signal encoded by the higher layer encoder 123 is subjected to error correction encoding by the higher layer FEC encoder 124. The error-correction-coded data is input to the multiplexing circuit 125. The multiplex circuit 125 multiplexes the low layer encoded data and the high layer encoded data and outputs the multiplexed data to the modulation circuit 126. Modulation circuit 12
The data modulated in 6 is output to the terminal 102, becomes a transmission signal, and is input to the terminal 103 on the receiving side.

On the receiving side, the data from the transmitting side is sent to the terminal 1
At 03, it is received as a received signal and demodulated by the demodulation circuit 140. The demodulated data is sent to the demultiplexing circuit 141.
Is divided into low layer encoded data and high layer encoded data, and the low layer encoded data is divided into the low layer FEC decoder 147.
And the higher layer encoded data is input to the higher layer FEC decoder 142. The low layer FEC decoder 147 performs FEC decoding, and the output is the low layer decoder 14
8 is input. Further, the error flag is input from the low layer FEC decoder 147 to the low layer decoder 148.
The error flag is a signal indicating whether or not an error has occurred in the received signal.

FIG. 5 shows the internal structure of the lower layer decoder 148. In FIG. 5, a terminal 701 has a low-level FEC.
The output signal of the decoder 147 is input. The signal input from the terminal 701 receives the buffer 710 and the variable length decoding circuit 7
11, the inverse quantization circuit 712, and the inverse DCT circuit 713. The decoded video signal is input to the adder 714. In the case of intraframe compression encoding, the terminal 70
Switch 7 by the refresh signal input from 3
30 is turned off, and the adder 714 only inputs the decoded video signal from the inverse DCT circuit 713. The video signal output from the adder 714 is transmitted via the switch 731 to the post-processing circuit 715 and the frame memory 71.
6 and the terminal 706. The output signal from the terminal 706 is input to the field memory 150, the vertical low pass filter 151, and the selection circuit 155 in FIG.
In the frame memory 716, the input video signal is delayed by one frame, and the motion compensation circuit 717 and the switch 73 are delayed.
Enter 1. In the motion compensation circuit 717, motion compensation is performed by the motion vector input from the terminal 704,
The output video signal is input to the switch 730. The motion vector input from the terminal 704 is also supplied to the terminal 707, and the output of the terminal 707 is input to the coefficient circuit 149 in FIG. Further, when the inter-frame compression encoding is performed, the video signal output from the inverse DCT circuit 713 is
It is a prediction error signal. At this time, the switch 730 is activated by the refresh signal input from the terminal 703.
Turns on. Therefore, the signals input to the adder 714 are the prediction error signal which is the output signal of the inverse DCT circuit 713 and the predicted video signal of one frame before input through the switch 730. The adder 714 adds the two signals and inputs them to the post-processing circuit 715 and the frame memory 716 via the switch 731. The post-processing circuit 715 rearranges the decoded video signals in block units composed of 8 pixels in the horizontal direction and 8 lines in the vertical direction in the order of scanning the screen, and outputs them to the terminal 705.

The error flag input from the low layer FEC decoder 147 is input to the terminal 702 and is directly supplied to the error compensation determination circuit 718. On the other hand, the refresh signal input from the terminal 703 is also input to the error compensation determination circuit 718. Error compensation determination circuit 718
Generates a previous frame interpolation signal when a data error exceeds a certain value, and connects the switch 731 to the terminal 709 side. By this operation, the video signal of one frame before output from the frame memory 716 is input to the post-processing circuit 715.

The decoded video signal derived to the terminal 705 is
It is an output signal of the lower layer decoder 148, and this signal is an interlaced scanning signal. This interlaced scanning signal is output to the terminal 105. The decoded video signal in block units output from the terminal 706 is the lower layer decoder 14
8 becomes the output signal and is input to the field memory 150, the vertical interpolation filter 151, and the selection circuit 155. Further, the motion vector output from the terminal 707 becomes an output signal of the lower layer decoder 148 and is input to the coefficient circuit 149.

Returning to FIG. 1, the coefficient circuit 149 detects the magnitude of the motion vector, outputs the coefficient K to the arithmetic circuit 153 according to the characteristic shown in FIG. 3, and outputs the coefficient 1-K to the arithmetic circuit 152. To be done. The arithmetic circuit 153 multiplies the output of the vertical interpolation filter 151 and the coefficient K output from the coefficient circuit 149 and outputs the product to the adder 154. Also,
In the arithmetic circuit 152, the video signal output from the field memory 150 and delayed by one field and the coefficient circuit 14
Multiply the coefficient 1-K output from 9 and adder 15
Output to 4. The adder 154 takes the sum of the output signals of the arithmetic circuit 152 and the arithmetic circuit 153 and inputs the sum to the selection circuit 155. In the selection circuit 155, the video signal in block units, which is the output signal of the lower layer decoder 148, and the adder 15
The block raster conversion circuit 156 selects the interpolated video signal in block units, which is the output signal of No. 4, alternately for each line.
Is output to. The signal input to the block raster conversion circuit 156 is a sequential scanning signal created by interpolating in block units. Block raster conversion circuit 156
In this case, the video signals in block units are rearranged and output to the adder 146 in the order of scanning the screen.

On the other hand, the high layer encoded data input to the high layer FEC decoder 142 is FEC decoded and then input to the high layer decoder 143. The error flag output from the higher layer FEC decoder 142 is the determination circuit 14
4 is input. In the judgment circuit 144, the designated value T
When an error flag is generated with a frequency exceeding h1, the switch 145 is turned off, and when the error flag generation frequency is less than the specified value Th2, the switch 145 is used.
A control signal for turning ON is output. Normal Th1> Th2
As a result, the determination circuit 144 has a hysteresis characteristic. The higher layer decoder 143 decodes the encoded video signal and inputs the decoded video signal to the adder 146 via the switch 145. In the adder 146, the high layer video signal output from the high layer decoder 143 and the block raster conversion circuit 15
The original progressive scan signal is output to the terminal 104 by adding the interpolated video signal output from the terminal 6. Here, when the determination circuit 144 determines that an error has occurred and the switch 145 is turned off, the terminal 104 is supplied with the interpolated progressive scan signal which is the output signal of the block raster conversion circuit 156. Will be.

(Effect of the first embodiment) By using the apparatus described in the first embodiment, it is possible to suppress the deterioration of the image quality of the progressive scanning signal generated by interpolating the interlaced scanning signal, and therefore, the forwarding On the side, the difference value between the progressive scan signal of the original signal and the progressive scan signal generated by interpolation is small, and the transmission rate can be lowered. Further, when the receiving side cannot supply the higher hierarchical signal when an error occurs and the original progressive scanning signal cannot be restored, it is necessary to display an image with the progressive scanning signal generated by interpolating the interlaced scanning signal. It is possible to prevent a sharp deterioration in image quality at that time.

(Second Embodiment) In FIG. 6, a video signal which is a progressive scanning signal is hierarchized into a progressive scanning signal and an interlaced scanning signal. The 2nd Example in the hierarchical coding system which encodes and transmits as a signal is shown.

A video signal which is a progressive scanning signal is input from the terminal 201. The video signal input from the terminal 201 receives the vertical low-pass filter 210 and the subtractor 21.
6 is input. The video signal input to the vertical low-pass filter 210 is band-limited, and the line thinning circuit 21
Input to 1. The line thinning circuit 211 thins out every other line to generate an interlaced scanning signal. The interlaced scanning signal output from the line thinning circuit 211 is input to the lower layer encoder 212,
Is encoded. The signal input from the layer encoder 212 to the lower layer FEC encoder 213 is an encoded signal. The low-layer FEC encoder 213 is subjected to error correction coding, and its output is the multiplexing circuit 21.
9 is supplied.

On the other hand, from the low layer encoder 212 to the 0 line insertion circuit 214, a decoded video signal obtained by returning the once encoded signal to the original is input. The decoded interlace scanning signal is input to the 0 line insertion circuit 214, and 0 data is inserted between the lines. The video signal in which 0 data is inserted between the lines is input to the vertical low pass filter 215 and becomes a sequential scanning signal. This progressive scanning signal is a signal whose band is limited as compared with the progressive scanning signal input from the terminal 201. Subtractor 2
16, the sequential scanning signal input from the terminal 201,
The difference from the band-limited progressive scanning signal output from the vertical low-pass filter 215 is calculated. The differential signal output from the subtractor 216 is encoded by the higher layer encoder 217. The progressive scan signal encoded by the higher layer encoder 217 is subjected to error correction encoding by the higher layer FEC encoder 218. The data that has been subjected to error correction coding is input to the multiplexing circuit 219. Multiplex circuit 2
In 19, the low layer coded data and the high layer coded data are multiplexed and output to the modulation circuit 220. Modulation circuit 220
Then, the modulated data is output to the terminal 202, becomes a transmission signal, and is input to the reception-side terminal 203.

On the receiving side, the data from the transmitting side is sent to the terminal 2
The signal is received as a received signal at 03 and demodulated at the demodulation circuit 240. The demodulated data is sent to the demultiplexing circuit 241.
Is divided into low layer encoded data and high layer encoded data, and the low layer encoded data is divided into the low layer FEC decoder 246.
Is input to the high layer FEC decoder 242. The low layer FEC decoder 246 performs FEC decoding, and the output thereof is input to the low layer decoder 247. In addition, from the low layer FEC decoder 246,
The error flag is input to the lower layer decoder 247.

The signal input from the lower layer decoder 247 to the terminal 205 and 0 line insertion circuit 248 is a decoded video signal, which is an interlaced scanning signal. The signal input from the lower layer decoder 247 to the field memory 251, the vertical interpolation filter 252, and the selection circuit 256 is a decoded video signal in block units. Further, the motion vector is input from the low layer decoder 247 to the coefficient circuit 250. The coefficient circuit 250 detects the magnitude of the image motion vector, applies the coefficient K to the arithmetic circuit 254 according to the characteristics shown in FIG. 3, and supplies the arithmetic circuit 253 with the coefficient 1-K. The arithmetic circuit 254 multiplies the output of the vertical interpolation filter 252 and the coefficient K output from the coefficient circuit 250 and outputs the result to the adder 255. The arithmetic circuit 253 multiplies the video signal delayed by one field output from the field memory 251 and the coefficient 1−K output from the coefficient circuit 250, and outputs the product to the adder 255. The adder 255 takes the sum of the output signals of the arithmetic circuit 253 and the arithmetic circuit 254 and inputs the sum to the selection circuit 256. In the selection circuit 256, the block-based video signal output from the lower layer decoder 247 and the block-based interpolated video signal output from the adder 255 are alternately selected line by line, and the block raster conversion circuit is selected. It is output to 257.
The signal input to the block raster conversion circuit 257 is a sequential scanning signal created by interpolating in block units. The block raster conversion circuit 257 rearranges the video signals in block units and outputs them to the selection circuit 258 in the order of scanning the screen.

The interlaced scanning signal input from the lower layer decoder 247 to the 0 line insertion circuit 248 is 0 between lines.
The data is inserted and input to the vertical low-pass filter 249 to become a sequential scanning signal. The progressive scan signal generated by this interpolation is input to the adder 244.

On the other hand, the high layer encoded data input to the high layer FEC decoder 242 is FEC decoded and input to the high layer decoder 243. The error flag output from the higher layer FEC decoder 242 is the determination circuit 24.
Input to 5. The determination circuit 245 uses the specified value Th.
When an error flag occurs with a frequency of more than 1, the switch 259 is turned off, and the selection circuit 258 outputs a control signal so that the output signal of the block raster conversion circuit 257 is selected. At this time, at the terminal 204,
The interpolated progressive scan signal which is the output signal of the block raster conversion circuit 257 is output. When the occurrence frequency of the error flag falls below the designated value Th2, the switch 259 is turned on, and the selection circuit 258 outputs a control signal for selecting the output signal of the adder 244. At this time, the decoded higher layer signal output from the higher layer decoder 243 is added to the adder 2 via the switch 259.
44 is input. In the adder 244, the higher layer decoder 2
The original progressive scan signal is output to the selection circuit 258 by adding the high hierarchy video signal output from 43 and the interpolated video signal output from the vertical low pass filter 249. The selection circuit 258 selects the output of the adder 244 and outputs the original sequential scanning signal to the terminal 204.
Normally, Th1> Th2, and the determination circuit 245 has a hysteresis characteristic.

(Effect of Second Embodiment) By using the device described in the second embodiment, the receiving side
When the high-level signal is not supplied when an error occurs and the original progressive scan signal cannot be restored, the video must be displayed with the progressive scan signal created by interpolating the interlaced scan signal, but at that time, the motion vector Since the progressive scanning signal generated by adaptively switching between the inter-field interpolation and the inter-field interpolation according to the size of is displayed, rapid image quality deterioration can be prevented.

(Third Embodiment) FIG. 7 shows that a video signal which is a progressive scanning signal is hierarchized into a progressive scanning signal and an interlaced scanning signal, and the interlaced scanning signal is a high hierarchical signal and the interlaced scanning signal is a low hierarchical signal. The 3rd Example in the hierarchical coding system which encodes and transmits as a signal is shown.

A video signal, which is a progressive scanning signal, is input from the terminal 301. The video signal input from the terminal 301 receives the vertical low pass filter 310 and the subtractor 31.
6 is input. The video signal input to the vertical low-pass filter 310 is band-limited, and the line thinning circuit 31
Input to 1. The line thinning circuit 311 thins out every other line to generate an interlaced scanning signal. The interlaced scanning signal output from the line thinning circuit 311 is input to the low layer encoder 312,
Is encoded. The signal input from the hierarchical encoder 312 to the low hierarchical FEC encoder 313 is an encoded signal. The low-layer FEC encoder 313 performs error correction coding, and its output is the multiplex circuit 31.
9 is input. On the other hand, a decoded video signal obtained by restoring the once-encoded signal to the original is input from the lower layer encoder 312 to the 0-line insertion circuit 314. The decoded interlaced scanning signal is input to the 0 line insertion circuit 314, and 0 data is inserted between the lines.
The video signal in which 0 data is inserted between the lines is input to the vertical low pass filter 315 and becomes a sequential scanning signal.
This progressive scanning signal is a signal whose band is limited as compared with the progressive scanning signal input from the terminal 301. The subtractor 316 takes the difference between the progressive scan signal input from the terminal 301 and the band-limited progressive scan signal output from the vertical low-pass filter 315. The differential signal output from the subtractor 316 is encoded by the higher layer encoder 317. The progressive scan signal encoded by the higher layer encoder 317 is subjected to error correction encoding by the higher layer FEC encoder 318. The data that has been subjected to error correction coding is input to the multiplexing circuit 319. The multiplex circuit 319 multiplexes the low layer encoded data and the high layer encoded data and outputs the multiplexed data to the modulation circuit 320. Modulation circuit 32
At 0, the modulated data is output to the terminal 302, becomes a transmission signal, and is input to the reception-side terminal 303.

On the receiving side, the data from the transmitting side is sent to the terminal 3
In 03, it is received as a received signal and demodulated by the demodulation circuit 340. The demodulated data is the demultiplexing circuit 341.
Is divided into low layer encoded data and high layer encoded data, and the low layer encoded data is divided into the low layer FEC decoder 346.
To the higher layer FEC decoder 342. The low layer FEC decoder 346 performs FEC decoding and inputs the result to the low layer decoder 347. Further, the error flag is input from the low layer FEC decoder 346 to the low layer decoder 347. The lower layer decoder 347 decodes the encoded lower layer signal, and the decoded signal is an interlaced scanning signal.

The interlaced scanning signal output from the lower layer decoder 347 is the terminal 305, the 0 line insertion circuit 348,
It is input to the motion detection circuit 350, the field memory 352, the vertical interpolation filter 353, and the selection circuit 357. The motion detection circuit 350 uses the decoded interlaced scanning signal,
The amount of movement between fields is detected for each pixel. The amount of motion detected by the motion detection circuit 350 is input to the coefficient circuit 351, and the coefficient K is output to the arithmetic circuit 355 according to the characteristics of the amount of motion and the coefficient K (0 ≦ K ≦ 1) shown in FIG. A coefficient 1-K is output to the circuit 354. Arithmetic circuit 3
55, the output of the vertical interpolation filter 353 and the coefficient circuit 3
The coefficient K output from 51 is multiplied and the adder 356 is added.
Output to. The arithmetic circuit 354 multiplies the video signal delayed by one field output from the field memory 352 by the coefficient 1-K output from the coefficient circuit 351, and outputs the product to the adder 356. In the adder 356,
The sum of the output signals of the arithmetic circuit 354 and the arithmetic circuit 355 is calculated and input to the selection circuit 357. In the selection circuit 357,
The interlaced scanning signal that is the output signal of the lower layer decoder 347 and the interpolated video signal that is the output signal of the adder 356 are alternately selected for each line and output to the selection circuit 358. The signal input to the selection circuit 358 is a sequential scanning signal created by interpolation.

The interlaced scanning signal input from the lower layer decoder 347 to the 0 line insertion circuit 348 is 0 between lines.
Data is inserted and input to the vertical low-pass filter 349, and becomes a sequential scanning signal. The progressive scan signal generated by this interpolation is input to the adder 344.

On the other hand, the high layer encoded data input to the high layer FEC decoder 342 is FEC decoded and then input to the high layer decoder 343. The error flag output from the higher layer FEC decoder 342 is the determination circuit 34.
Input to 5. The determination circuit 345 uses the designated value Th.
When an error flag occurs with a frequency exceeding 1, the switch 359 is turned off, and the selection circuit 358 outputs a control signal for selecting the output signal of the selection circuit 357. At this time, the interpolated progressive scan signal which is the output signal of the selection circuit 357 is output to the terminal 304.
When the occurrence frequency of the error flag falls below the designated value Th2, the switch 359 is turned on, and the selection circuit 358 outputs a control signal for selecting the output signal of the adder 344. At this time, the higher layer decoder 34
The decoded higher layer signal output from the switch 3 is the switch 35.
9 is input to the adder 344. The adder 344 adds the high-layer video signal output from the high-layer decoder 343 and the interpolated video signal output from the vertical low-pass filter 349 to select the original progressive scan signal from the selection circuit 3
It outputs to 58. In the selection circuit 358, the adder 34
4 is selected and the original progressive scanning signal is output to the terminal 304. Normally, Th1> Th2, and the determination circuit 3
45 has a hysteresis characteristic. (Effect of the third embodiment) When the apparatus described in the third embodiment is used, when the receiving side cannot supply the higher hierarchical signal when an error occurs and the original progressive scanning signal cannot be restored. , It is necessary to display an image with a progressive scan signal created by interpolating an interlaced scan signal, but at that time, a sequence created by adaptively switching between intra-field interpolation and inter-field interpolation according to the amount of motion. Since the scanning signal is displayed, it is possible to prevent rapid image quality deterioration.

(Embodiment 4) In FIG. 8, a video signal which is a progressive scanning signal is hierarchized into a progressive scanning signal and an interlaced scanning signal, the progressive scanning signal is a high hierarchical signal, and the interlaced scanning signal is a low hierarchical signal. 4 shows a fourth embodiment in a hierarchical coding system for coding and transmitting.

A video signal, which is a progressive scanning signal, is input from the terminal 401. The video signal input from the terminal 401 receives the vertical low-pass filter 410 and the subtractor 42.
Entered in 2. The video signal input to the vertical low-pass filter 410 is band-limited, and the line thinning circuit 41
Input to 1. The line thinning circuit 411 thins out every other line to generate an interlaced scanning signal. The interlaced scanning signal output from the line thinning circuit 411 is input to the low layer encoder 412,
Is encoded. The signal input from the layer encoder 412 to the low layer FEC encoder 413 is an encoded signal. The low-layer FEC encoder 413 performs error correction coding, and inputs it to the multiplexing circuit 425. On the other hand, from the lower layer encoder 412 to the motion detection circuit 4
14, field memory 416, vertical interpolation filter 41
7. To the selection circuit 421, the decoded video signal obtained by restoring the once encoded signal to the original is input.

The motion detection circuit 414 detects the amount of motion between fields for each pixel from the decoded interlaced scanning signal. The motion amount detected by the motion detection circuit 414 is
The motion amount and coefficient K shown in FIG. 3 are input to the coefficient circuit 415.
The coefficient K is calculated according to the characteristic of (0 ≦ K ≦ 1).
9 and outputs the coefficient 1-K to the arithmetic circuit 418. The arithmetic circuit 419 multiplies the output of the vertical interpolation filter 417 and the coefficient K output from the coefficient circuit 415 and outputs the result to the adder 420. The arithmetic circuit 418 multiplies the video signal delayed by one field output from the field memory 416 and the coefficient 1-K output from the coefficient circuit 415, and outputs the product to the adder 420. The adder 420 takes the sum of the output signals of the arithmetic circuits 418 and 419 and inputs the sum to the selection circuit 421. The selection circuit 421 alternately selects the interlaced scanning signal, which is the output signal of the lower layer decoder 412, and the interpolated video signal, which is the output signal of the adder 420, line by line, and outputs it to the subtractor 422. The signal input to the subtractor 422 is a sequential scanning signal created by interpolation.

The subtractor 422 calculates the difference between the progressive scan signal input from the terminal 401 and the interpolated progressive scan signal output from the selection circuit 421. Subtractor 4
The differential signal output from the high-level encoder 423
Is encoded with. The progressive scan signal encoded by the higher layer encoder 423 is subjected to error correction encoding by the higher layer FEC encoder 424. The data that has been subjected to error correction coding is input to the multiplexing circuit 425. The multiplex circuit 425 multiplexes the low layer coded data and the high layer coded data and outputs the multiplexed data to the modulation circuit 426. The data modulated by the modulation circuit 426 is output to the terminal 402, becomes a transmission signal, and is input to the terminal 403 on the receiving side.

On the receiving side, the data from the transmitting side is sent to the terminal 4
In 03, it is received as a received signal and demodulated by the demodulation circuit 440. The demodulated data is the demultiplexing circuit 441.
Is divided into low layer encoded data and high layer encoded data, and the low layer encoded data is divided into the low layer FEC decoder 446.
Is input to the higher layer FEC decoder 442. The low layer FEC decoder 446 performs FEC decoding and inputs the result to the low layer decoder 447. Further, the error flag is input from the low layer FEC decoder 446 to the low layer decoder 447. The low layer decoder 447 decodes the encoded low layer signal, and the decoded signal is an interlaced scanning signal.

The interlaced scanning signal output from the lower layer decoder 447 is input to the terminal 405, the motion detection circuit 448, the field memory 450, the vertical interpolation filter 451, and the selection circuit 455. The motion detection circuit 448 detects the amount of motion between fields for each pixel from the decoded interlaced scanning signal. The motion amount detected by the motion detection circuit 448 is input to the coefficient circuit 449, and the coefficient K is output to the arithmetic circuit 453 according to the characteristics of the motion amount and the coefficient K (0 ≦ K ≦ 1) shown in FIG. The circuit 452 has a coefficient of 1-K
Is being output. The arithmetic circuit 453 outputs the output of the vertical interpolation filter 451 and the coefficient K output from the coefficient circuit 449.
And outputs to the adder 454. The arithmetic circuit 452 multiplies the video signal delayed by one field output from the field memory 450 and the coefficient 1-K output from the coefficient circuit 452, and outputs the product to the adder 454. The adder 454 sums the output signals of the arithmetic circuit 452 and the arithmetic circuit 453, and inputs the sum to the selection circuit 455. The selection circuit 455 alternately selects the interlaced scanning signal, which is the output signal of the lower layer decoder 447, and the interpolated video signal, which is the output signal of the adder 454, for each line, and outputs it to the adder 444. The signal input to the adder 444 is a sequential scanning signal created by interpolation.

On the other hand, the high layer encoded data input to the high layer FEC decoder 442 is FEC decoded and input to the high layer decoder 443. The error flag output from the higher layer FEC decoder 442 is the determination circuit 44.
Input to 5. In the judgment circuit 445, the designated value T
When the error flag is generated with a frequency exceeding h1, the switch 456 is turned off, and when the error flag generation frequency is lower than the designated value Th2, the switch 456 is used.
A control signal for turning ON is output. Normal Th1> Th2
Therefore, the determination circuit 445 has a hysteresis characteristic. The higher layer decoder 443 decodes the encoded video signal, and inputs the decoded video signal to the adder 444 via the switch 456. The adder 444 outputs the original progressive scan signal to the terminal 404 by adding the high layer video signal output from the high layer decoder 443 and the interpolated video signal output from the selection circuit 455. Here, when the determination circuit 445 determines that an error has occurred and the switch 456 is turned off, the interpolated progressive scan signal which is the output signal of the selection circuit 455 is supplied to the terminal 404. Become.

As described above, according to the embodiment of the present invention, the following advantages are obtained. (Claims 1 and 2) Interpolation is performed by interpolating inter-field interpolation and inter-field interpolation in accordance with the motion in block units (for example, 8 pixels × 8 lines) using a motion vector, so that interpolation is performed. It is possible to suppress the image quality deterioration of the generated progressive scanning signal. Therefore, the difference value between the progressive scanning signal which is the original signal and the interpolated progressive scanning signal becomes small, and the transmission rate can be lowered.

(Claims 3 and 4) Since the inter-field interpolation and the inter-field interpolation are switched in accordance with the movement on a pixel-by-pixel basis to generate an interpolated progressive scan signal, the hierarchical coding apparatus according to any one of claims 1 and 2. Although the circuit scale is larger than
Image quality deterioration of the interpolated progressive scan signal can be further suppressed. Therefore, the difference value between the progressive scanning signal which is the original signal and the interpolated progressive scanning signal becomes small, and the transmission rate can be lowered.

(Claims 5, 6, 7, and 8) When the error of the transmitted high layer signal exceeds the reference value, the high layer signal is not supplied, and the progressive scanning signal which is the original signal cannot be displayed, and the low level signal is low. A progressive scanning signal generated by interpolating the interlaced scanning signal which is a hierarchical signal is displayed. At this time,
Since the inter-field interpolation and the inter-field interpolation are switched according to the movement on a block-by-block basis to generate the interpolated progressive scanning signal, it is possible to suppress the image quality deterioration of the interpolated progressive scanning signal. Therefore, it is possible to prevent a sharp deterioration in image quality when the error of the higher layer signal exceeds the reference value and the display of the progressive scanning signal which is the original signal is switched to the display of the interpolated progressive scanning signal.

(Claims 9, 10, 11 and 12) When the error of the transmitted higher layer signal exceeds the reference value, the higher layer signal is not supplied and the progressive scanning signal which is the original signal cannot be displayed, and the low level signal cannot be displayed. A progressive scanning signal generated by interpolating the interlaced scanning signal which is a hierarchical signal is displayed. At this time, the inter-field interpolation and the inter-field interpolation are switched in accordance with the movement on a pixel-by-pixel basis to create an interpolated progressive scanning signal. Therefore, compared to the hierarchical decoding device according to claim 5, 6, 7, or 8. Although the scale becomes large, it is possible to further suppress the image quality deterioration of the interpolated progressive scanning signal. Therefore, it is possible to prevent a sharp deterioration in image quality when the error of the higher layer signal exceeds the reference value and the display of the progressive scanning signal which is the original signal is switched to the display of the interpolated progressive scanning signal.

(Claims 13 and 14) On the feed side,
Since the inter-field interpolation and the inter-field interpolation are switched in block units according to the motion using the motion vector to generate the interpolated progressive scan signal, it is possible to suppress the image quality deterioration of the interpolated progressive scan signal. Therefore, the difference value between the progressive scanning signal which is the original signal and the interpolated progressive scanning signal becomes small, and the transmission rate can be lowered.
Further, the receiving side also uses the motion vector similarly to the sending side, and the inter-field interpolation and the inter-field interpolation are switched according to the movement in block units to generate the interpolated progressive scanning signal. It is possible to suppress the image quality deterioration of the signal, so that when the error of the higher hierarchy signal exceeds the reference value and the display of the original scanning signal is switched to the interpolated scanning signal display, It is possible to prevent deterioration of image quality.

(Claims 15 and 16) On the feed side,
Since the inter-field interpolation and the inter-field interpolation are switched in accordance with the movement on a pixel-by-pixel basis to generate the interpolated progressive scan signal, the deterioration of the image quality of the interpolated progressive scan signal is further increased as compared with the methods of claims 13 and 14. Can be suppressed. Therefore, the difference value between the progressive scanning signal which is the original signal and the interpolated progressive scanning signal becomes small, and the transmission rate can be lowered. Further, in the receiving side as well as in the sending side, the inter-field interpolation and the inter-field interpolation are switched according to the movement on a pixel-by-pixel basis to produce an interpolated progressive scanning signal, so that compared to the method of claims 13 and 14. It is possible to suppress the image quality deterioration of the interpolated progressive scan signal. Therefore, the error of the higher hierarchy signal exceeds the reference value, and the display of the original progressive scan signal is switched to the display of the interpolated progressive scan signal. It is possible to prevent a sudden deterioration in image quality when the image is replaced.

[0071]

As described above, according to the present invention,
It is possible to obtain a hierarchical coding transmission system and a transmission / reception device thereof that can reduce the transmission rate of a high layer signal and can suppress deterioration of image quality when an error occurs on the receiving side.

[Brief description of drawings]

FIG. 1 is a structural explanatory view showing a first embodiment of the present invention.

FIG. 2 is a diagram showing an internal configuration of a low layer encoder in the first embodiment.

FIG. 3 is a diagram showing a relationship between an image motion vector (image motion amount) and a coefficient K.

FIG. 4 is a diagram showing a process of interpolating an interlaced scanning signal to generate a sequential scanning signal.

FIG. 5 is a diagram showing an internal configuration of a lower layer decoder in the first embodiment.

FIG. 6 is a structural explanatory view showing a second embodiment of the present invention.

FIG. 7 is a structural explanatory view showing a third embodiment of the present invention.

FIG. 8 is a structural explanatory view showing a fourth embodiment of the present invention.

FIG. 9 is a diagram showing a conventional hierarchical encoding / decoding system.

FIG. 10 is a diagram showing an internal configuration of a conventional low layer encoder.

FIG. 11 is a diagram showing an internal configuration of a conventional low layer decoder.

FIG. 12 is a time chart for explaining error correction.

[Explanation of symbols]

110, 210 ... Vertical low-pass filter, 111, 21
1 ... Line thinning circuit, 112, 212 ... Low layer encoder, 113, 213 ... Low layer FEC encoder, 114,
214 ... Coefficient circuit, 115, 215 ... Field memory, 116, 216 ... Vertical interpolation filter, 117, 11
8 ... Arithmetic circuit, 119 ... Adder, 120 ... Selection circuit, 1
21 ... Block tester conversion circuit, 122 ... Subtractor, 12
3, 218 ... High-layer encoder, 124, 217 ... High-layer FEC encoder, 125, 219 ... Multiplex circuit, 126, 220 ... Modulation circuit, 140, 240 ... Demodulation circuit, 141, 241 ... Demultiplex Circuit, 14
2, 242 ... High layer FEC decoder, 143, 243 ... High layer decoder, 144, 245 ... Judgment circuit, 145, 25
9 ... Switch, 146, 244 ... Adder, 147, 24
6 ... Low layer FEC decoder, 148, 247 ... Low layer decoder, 149, 250 ... Coefficient circuit, 150, 251 ... Field memory, 151, 252 ... Vertical interpolation filter, 1
53, 154, 253, 254 ... Arithmetic circuit, 154, 2
55 ... Adder, 155, 256 ... Selection circuit, 156, 2
57 ... Block raster conversion circuit.

Claims (14)

[Claims] 1. An original progressive scan signal is layered by a progressive scan signal for transmission and an interlaced scan signal for transmission, and the progressive scan signal for transmission is encoded by a high layer encoding means and transmitted as a high layer signal, and the transmission is performed. A hierarchical coding apparatus for coding a special interlaced scanning signal by a low hierarchical coding means and transmitting it as a low hierarchical signal, wherein means for subtracting a low frequency sequential scanning signal from the original sequential scanning signal to obtain the transmission sequential scanning signal In the case of interpolating the decoded interlaced scanning signal output from the lower layer encoding means, an interpolation signal created by adaptively switching intra-field interpolation and inter-field interpolation according to image motion information is used. And a means for generating the low-frequency sequential scanning signal. 2. The image motion information is information on a motion vector used in the lower layer encoding means or information on an image motion amount of an interlaced scanning signal decoded and output from the lower layer encoding means. The hierarchical encoding device according to claim 1, wherein 3. An original progressive scanning signal is layered by a progressive scanning signal for transmission and an interlaced scanning signal for transmission, and the progressive scanning signal for transmission is encoded by a high layer encoding means to be transmitted as a high layer signal, and the transmission. In a hierarchical coding apparatus for coding a special interlaced scanning signal by a low hierarchical coding means and transmitting it as a low hierarchical signal, a field for producing a first interpolation signal from the interlaced scanning signal in the low hierarchical coding means by intra-field interpolation. An inner interpolating means, an inter-field interpolating means for producing a second interpolated signal by inter-field interpolation from the interlaced scanning signal in the lower layer encoding means, a magnitude of a motion vector output from the lower layer encoding means, Alternatively, the coefficient K (0 ≦ K ≦ 1) is determined from the image motion amount detected using the decoded interlaced scanning signal output from the low layer encoding means. Means, means for multiplying the first interpolation signal output from the intra-field interpolation means by K, means for multiplying the second interpolation signal output from the inter-field interpolation means by 1-K, Means for producing a low-frequency sequential scanning signal using a third interpolation signal obtained by the sum of the K-multiplied signal and the 1-K-multiplied signal; and the low-frequency sequential scanning signal from the original sequential scanning signal. Means for subtracting to produce the progressive scanning signal for transmission. 4. An original progressive scanning signal is layered by a transmission progressive scanning signal and a transmission interlaced scanning signal, and the transmission progressive scanning signal is encoded by a high layer encoding means and transmitted as a high layer signal. In the hierarchical decoding system, the interlaced scanning signal for transmission is encoded by a low hierarchical encoding unit to decode a transmission signal transmitted as a low hierarchical signal, wherein the low hierarchical signal is decoded and the interlaced transmission is performed. Low-layer decoding means for restoring a scanning signal, high-layer decoding means for decoding the high-layer signal to restore the transmission sequential scanning signal, and the restored transmission interlaced scanning signal output from the low-layer decoding means When interpolating, depending on the image motion information,
Means for creating a restored low-frequency sequential scanning signal using an interpolation signal created by adaptively switching between intra-field interpolation and inter-field interpolation, and adding the restored low-frequency sequential scanning signal to the reconstruction transmission sequential scanning signal. And a means for reconstructing the original progressive scanning signal, and the higher layer decoding means, when it is detected that an error of a reference value or more has occurred in the transmitted higher layer signal, the reconstructed transmission progressive scanning signal is And a means for turning off and outputting the restored low frequency band progressive scanning signal. 5. The image motion information is information on a motion vector used in the lower layer decoding means or information on an image motion amount of an interlaced scanning signal decoded and output from the lower layer decoding means. The hierarchical decoding device according to claim 4. 6. The original progressive scan signal is layered by a progressive scan signal for transmission and an interlace scan signal for transmission, and the progressive scan signal for transmission is encoded by a high layer encoding means and transmitted as a high layer signal. In the layer decoding device that decodes the signal that is transmitted as the lower layer signal by being encoded by the lower layer encoding means, the interlaced scanning signal for transmission, the interlaced scanning for transmission is performed by decoding the lower layer signal. A low layer decoding means for restoring a signal, a high layer decoding means for decoding the high layer signal to restore the transmission progressive scanning signal, and an intra-field from the restored transmission interlaced scanning signal from the low layer decoding means In-field interpolating means for producing a first interpolating signal by interpolation, and second interpolating signal by inter-field interpolating from the interlaced scanning signal for restoration transmission from the lower layer decoding means. Inter-field interpolating means for generating a signal, the magnitude of the motion vector output from the lower layer decoding means, or the image motion amount detected using the decoded interlaced scanning signal output from the lower layer decoding means. Means for determining a coefficient K (0 ≦ K ≦ 1), means for multiplying the first interpolation signal output from the intra-field interpolation means by K, and the second output from the inter-field interpolation means. Means for multiplying the interpolated signal by 1-K, means for producing a restored low-frequency sequential scanning signal using a third interpolated signal obtained by the sum of the K-multiplied signal and the 1-K-multiplied signal, A unit that adds the restored low-band progressive scan signal to the restored progressive scan signal to restore the original progressive scan signal; and the high-layer decoding unit that has an error of a reference value or more in the transmitted high-layer signal. Detected that something happened The time, hierarchical decoding apparatus characterized by comprising a means for outputting the restored low frequency sequential scanning signal to turn off the progressive scanning signal for the restored transmission. 7. A transmission / reception system in which a progressive scanning signal is layered by a progressive scanning signal and an interlaced scanning signal, the progressive scanning signal is transmitted as a high hierarchical signal, and the interlaced scanning signal is transmitted as a low hierarchical signal, and the transmission side receives a low level signal. Intra-field interpolation and inter-field interpolation depending on the magnitude of the motion vector output from the hierarchical encoder, or the image motion amount detected using the decoded interlaced scanning signal output from the low hierarchical encoding means. Adaptively switch to create a progressive scan signal from the interlaced scan signal, take the difference between this progressive scan signal and the original progressive scan signal, and transmit this difference as a higher layer signal. Depending on the magnitude of the output motion vector or the image motion amount detected using the decoded interlaced scanning signal output from the lower layer decoder, Inter-field interpolation and inter-field interpolation are adaptively switched to interpolate a progressive scanning signal from a decoded interlaced scanning signal, and the sum of the interpolated progressive scanning signal and the decoded signal of the higher hierarchy signal. A transmission / reception system of a hierarchical signal, characterized in that the original sequential scanning signal is decoded by taking 8. A transmission / reception method in which a progressive scanning signal is layered by a progressive scanning signal and an interlaced scanning signal, the progressive scanning signal is transmitted as a high hierarchical signal, and the interlaced scanning signal is transmitted as a low hierarchical signal, and the reception side is low at the sending side. The coefficient K is determined from the magnitude of the motion vector output from the hierarchical encoder or the image motion amount detected by using the decoded interlaced scanning signal output from the low hierarchical encoding means, and the low hierarchical code is determined. The decoded interlaced scanning signal output from the encoder is multiplied by K (0 ≦ K ≦ 1) times the interpolated signal, and the interlaced interpolation of the decoded interlaced scanning signal output from the lower layer encoder. The interpolated progressive scan signal and the original progressive scan signal are created by multiplying the obtained signal by 1-K and taking the sum of the K-multiplied signal and the 1-K multiplied signal. The difference value with the signal is transmitted as a higher layer signal, and the receiving side uses the magnitude of the motion vector output from the lower layer decoder or the decoded interlaced scanning signal output from the lower layer decoder. The coefficient K is determined from the detected image motion amount, and the decoded interlaced scanning signal output from the low layer decoder is interpolated by K (0≤K≤1) times to obtain the low layer decoder. The interlaced interpolated signal of the decoded interlaced scanning signal output by 1 is multiplied by 1-K, and the interpolated progressive scanning signal is created by taking the sum of the K multiplied signal and the 1-K multiplied signal. A method of transmitting / receiving a hierarchical signal, wherein the original progressive scanning signal is decoded by summing a signal obtained by decoding the higher hierarchical signal and the interpolated progressive scanning signal. 9. An original progressive scanning signal is layered by a progressive scanning signal for transmission and an interlaced scanning signal for transmission, and the progressive scanning signal for transmission is encoded by a high hierarchical encoding means to be transmitted as a high hierarchical signal, and the transmission. In the hierarchical coding method of coding the interlaced scanning signal for low-level coding means and transmitting it as a low-level signal, a low-frequency sequential scanning signal is subtracted from the original sequential scanning signal to obtain the transmission sequential scanning signal, In the case of interpolating the decoded interlaced scanning signal output from the lower layer encoding means, the interpolation signal generated by adaptively switching the intra-field interpolation and the inter-field interpolation according to the image motion information is used. A hierarchical encoding method characterized in that an area sequential scanning signal is created. 10. The image motion information is information on a motion vector used in the low layer encoding means or image motion amount information of an interlaced scanning signal decoded and output from the low layer encoding means. 10. The hierarchical encoding method according to claim 9, wherein: 11. An original progressive scanning signal is layered by a progressive scanning signal for transmission and an interlaced scanning signal for transmission, and the progressive scanning signal for transmission is encoded by a high layer encoding means to be transmitted as a high layer signal, and the transmission. In a layered encoding method for encoding an interlaced scanning signal for use in a lower layered encoding means and transmitting it as a lower layered signal, a first interpolated signal is created by inter-field interpolation from the interlaced scanning signal in the lower layered encoding means, A second interpolation signal is generated by inter-field interpolation from the interlaced scanning signal in the low layer encoding means, and the magnitude of the motion vector output from the low layer encoding means or the output from the low layer encoding means. Before determining the coefficient K (0 ≦ K ≦ 1) from the image motion amount detected using the decoded interlaced scanning signal Note that the first interpolation signal is multiplied by K, the second interpolation signal output from the inter-field interpolation unit is multiplied by 1−K, and the sum of the K multiplied signal and the 1−K multiplied signal is calculated. A hierarchical code, wherein a low-frequency sequential scanning signal is generated using the obtained third interpolation signal, and the low-frequency sequential scanning signal is subtracted from the original sequential scanning signal to generate the transmission sequential scanning signal. Method. 12. An original progressive scanning signal is layered by a transmission progressive scanning signal and a transmission interlaced scanning signal, and the transmission progressive scanning signal is encoded by a high layer encoding means and transmitted as a high layer signal. In the layer decoding method, the interlaced scanning signal for transmission is encoded by a low layer encoding means to decode a signal transmitted as a low layer signal, wherein the interlaced scanning for transmission is performed by decoding the low layer signal. When the signal is restored, the higher layer signal is decoded to restore the transmission progressive scanning signal, and the restored interlaced transmission scanning signal output from the lower layer decoding means is interpolated, depending on the image motion information, Then, a restored low band progressive scan signal is created using an interpolation signal created by adaptively switching between intra-field interpolation and inter-field interpolation, and the restored low band progressive scan signal is used as the restored transmission progressive scan signal. When the progressive scanning signal is added to restore the original progressive scanning signal, and when the high hierarchical decoding means performs the high hierarchical decoding, it is detected that an error of the transmitted high hierarchical signal or more exceeds a reference value. In this case, the decompression transmission progressive scan signal is turned off, and the decompression low band progressive scan signal is output. 13. The image motion information is information on a motion vector used in the lower layer decoding means or information on an image motion amount of an interlaced scanning signal decoded and output from the lower layer decoding means. The hierarchical coding method according to claim 12. 14. An original progressive scan signal is layered by a progressive scan signal for transmission and an interlace scan signal for transmission, and the progressive scan signal for transmission is encoded by a high layer encoding means and transmitted as a high layer signal. In the layer decoding method, the interlaced scanning signal for transmission is encoded by a low layer encoding means to decode a signal transmitted as a low layer signal, wherein the interlaced scanning for transmission is performed by decoding the low layer signal. A signal is restored, the higher layer signal is decoded to restore the transmission progressive scan signal, and a first interpolated signal is created by inter-field interpolation from the restored interlaced scan signal from the lower layer decoding means, A second interpolated signal is created by inter-field interpolation from the interlaced scanning signal for restoration transmission from the low layer decoding means, and a large motion vector output from the low layer decoding means is generated. Alternatively, the coefficient K (0 ≦ K ≦ 1) is determined from the image motion amount detected using the decoded interlaced scanning signal output from the lower layer decoding means, and is output from the intra-field interpolation means. The first interpolation signal is multiplied by K, the second interpolation signal output from the inter-field interpolation means is multiplied by 1−K, and the sum of the K multiplied signal and the 1−K multiplied signal is calculated. A restored low-frequency sequential scanning signal is created using the obtained third interpolation signal, and the restored low-frequency sequential scanning signal is added to the restoration scanning progressive scanning signal to restore the original sequential scanning signal. When it is detected by the decoding means that an error equal to or more than a reference value has occurred in the transmitted higher layer signal when performing the higher layer decoding, the restoration transmission progressive scan signal is turned off to restore the restoration low level signal. It is characterized by outputting a region sequential scanning signal Layer decoding how.