JPH07273287A - Semiconductor resistance device and amplifier circuit using it - Google Patents

Semiconductor resistance device and amplifier circuit using it

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Publication number
JPH07273287A
JPH07273287A JP5642394A JP5642394A JPH07273287A JP H07273287 A JPH07273287 A JP H07273287A JP 5642394 A JP5642394 A JP 5642394A JP 5642394 A JP5642394 A JP 5642394A JP H07273287 A JPH07273287 A JP H07273287A
Authority
JP
Japan
Prior art keywords
resistance
voltage
semiconductor
region
amplifier circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5642394A
Other languages
Japanese (ja)
Inventor
Yutaka Sada
裕 佐田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Engineering Ltd
Original Assignee
NEC Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Engineering Ltd filed Critical NEC Engineering Ltd
Priority to JP5642394A priority Critical patent/JPH07273287A/en
Publication of JPH07273287A publication Critical patent/JPH07273287A/en
Pending legal-status Critical Current

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  • Control Of Amplification And Gain Control (AREA)

Abstract

PURPOSE:To obtain a semiconductor resistance without voltage dependence in a simple constitution by eliminating a change in a resistance value by changing a depletion layer so as to depend on an applied voltage. CONSTITUTION:N-wells 12, 14 are formed independently on a P-type semiconductor substrate 11, and P-type resistance regions 13, 15 are formed respectively inside the individual wells. The N-wells 12, 14 are used to be floating. Since the wells 12, 14 are floating, potentials of the wells are decided by voltages of the resistance regions, and the voltage of a P-N junction part becomes a very small forward bias. Consequently, even when the voltages of the individual resistance regions 13, 15 are changed, the voltage of the P-N junction part is not changed but is always definite, and a depletion layer is not generated.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体抵抗装置及びそれ
を用いた増幅回路に関し、特に拡散抵抗の電圧依存性を
低減した半導体抵抗装置及びそれを用いた増幅回路に関
するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor resistance device and an amplifier circuit using the same, and more particularly to a semiconductor resistance device in which the voltage dependence of diffusion resistance is reduced and an amplification circuit using the same.

【0002】[0002]

【従来の技術】一般に、オペアンプ(演算増幅器)を用
いた増幅回路の一例である反転増幅回路の構成は図2に
示すようになっている。図2において、信号源1の入力
信号VINは入力抵抗2を介してオペアンプ7の反転入力
5へ印加されており、その非反転入力6は抵抗3を介し
て接地電位が付与されている。そして、このオペアンプ
7の出力8は帰還抵抗4を介して反転入力5へ帰還され
て負帰還が施されている。
2. Description of the Related Art Generally, the configuration of an inverting amplifier circuit, which is an example of an amplifier circuit using an operational amplifier (operational amplifier), is as shown in FIG. In FIG. 2, the input signal VIN of the signal source 1 is applied to the inverting input 5 of the operational amplifier 7 via the input resistor 2, and the non-inverting input 6 thereof is given the ground potential via the resistor 3. The output 8 of the operational amplifier 7 is fed back to the inverting input 5 via the feedback resistor 4 and negatively fed back.

【0003】この様な反転増幅回路は半導体集積回路構
成とされるが、入力抵抗2と帰還抵抗4との集積回路構
造を図3に示している。図3において、P型半導体基板
11の一主表面上に、N型の不純物拡散領域(Nウェ
ル)12が形成されており、このNウェル12内にP型
の抵抗領域13,15が不純物拡散やイオン注入等によ
り形成される。
Such an inverting amplifier circuit has a semiconductor integrated circuit structure, and the integrated circuit structure of the input resistor 2 and the feedback resistor 4 is shown in FIG. In FIG. 3, an N type impurity diffusion region (N well) 12 is formed on one main surface of a P type semiconductor substrate 11, and P type resistance regions 13 and 15 are diffused in the N well 12. And ion implantation.

【0004】これ等P型領域13,15が抵抗領域とし
て用いられるもので、P型領域13が図2の入力抵抗2
として、またP型領域15が図2の帰還抵抗4として夫
々使用される。
These P-type regions 13 and 15 are used as resistance regions, and the P-type region 13 is the input resistor 2 of FIG.
, And the P-type region 15 is used as the feedback resistor 4 in FIG.

【0005】かかる構成において、半導体基板11には
回路の最低電位(本例ではアース電位)が印加され、N
ウェル12には電源16により回路の最高電位VCCが印
加される。こうすることによって、基板11とNウェル
12とのPN接合面及びNウェル12とP型抵抗領域1
3,15との各PN接合面は、共に逆バイアスとなるの
で、互いの抵抗領域13,15は絶縁分離されることに
なり、よってこれ等P型領域13,15が抵抗素子とし
て使用可能となるのである。
In such a structure, the lowest potential of the circuit (earth potential in this example) is applied to the semiconductor substrate 11, and N
The power source 16 applies the highest potential Vcc of the circuit to the well 12. By doing so, the PN junction surface between the substrate 11 and the N well 12 and the N well 12 and the P type resistance region 1 are formed.
Since the respective PN junction surfaces with 3 and 15 are reverse biased, the resistance regions 13 and 15 are isolated from each other, so that these P-type regions 13 and 15 can be used as resistance elements. It will be.

【0006】[0006]

【発明が解決しようとする課題】図3の構造において
は、Nウェル12と抵抗領域13,15との間のPN接
合部の逆バイアス電圧が変化すると、空乏層の幅がそれ
に伴って変化するので、抵抗領域13,15の各抵抗値
も変化することになる。
In the structure of FIG. 3, when the reverse bias voltage of the PN junction between the N well 12 and the resistance regions 13 and 15 changes, the width of the depletion layer changes accordingly. Therefore, the resistance values of the resistance regions 13 and 15 also change.

【0007】この様な空乏層の変化に起因する抵抗値の
変化が、図2の反転増幅回路の特性に影響を及ぼす問題
点を、抵抗2,4の各値が共に等しくR2=R4の場合
につき説明する。
The problem that the change in the resistance value due to such a change in the depletion layer affects the characteristics of the inverting amplifier circuit of FIG. 2 is that when the values of the resistors 2 and 4 are equal, R2 = R4. Will be explained.

【0008】オペアンプ7の反転入力5は仮想接地であ
るのでその電位は0Vとみなせる。よって、入力電圧V
INが負の場合、−VIN/R2なる電流が出力8から抵抗
4及び2を介して信号源1へ流れる。従って、出力8の
電圧VOUT は、−VIN×R4/R2となる。
Since the inverting input 5 of the operational amplifier 7 is a virtual ground, its potential can be regarded as 0V. Therefore, the input voltage V
When IN is negative, a current of −VIN / R2 flows from the output 8 through the resistors 4 and 2 to the signal source 1. Therefore, the voltage VOUT of the output 8 becomes -VIN * R4 / R2.

【0009】Nウェル12は最高電位はバイアスされて
いるので、抵抗2は抵抗4より大きな逆バイアス電圧が
印加される。
Since the N well 12 is biased at the highest potential, a reverse bias voltage larger than that of the resistor 4 is applied to the resistor 2.

【0010】図4は抵抗の電圧依存性を示すグラフであ
り、抵抗2と4の逆バイアス電圧を夫々V2,V4とす
ると、V2>V4であるから、R2>R4となる。従っ
て、VOUT <−1×VINとなる。入力電圧VINが正の場
合も同様にして、VOUT <−1×VINとなる。
FIG. 4 is a graph showing the voltage dependence of the resistance. When the reverse bias voltages of the resistors 2 and 4 are V2 and V4, respectively, V2> V4, and thus R2> R4. Therefore, VOUT <-1 * VIN. Similarly, when the input voltage VIN is positive, VOUT <−1 × VIN.

【0011】理想的な反転増幅回路の入出力特性を図5
に破線52で示すと、従来例では、実線51で示すよう
に入出力直線性が悪いという問題点がある。抵抗の電圧
依存性が不純物濃度により変化するので一概にはいえな
いが、代表的な例として、VIN=3Vとすると、VOUT
=−3.06Vとなり、理想的な反転増幅回路より2%
低い出力電圧となる。
FIG. 5 shows the input / output characteristics of an ideal inverting amplifier circuit.
In the conventional example, there is a problem that the input / output linearity is poor, as indicated by the solid line 51. Since the voltage dependence of resistance changes depending on the impurity concentration, it cannot be said unequivocally, but as a typical example, if VIN = 3V, VOUT
= -3.06V, 2% better than the ideal inverting amplifier circuit
Low output voltage.

【0012】この様な抵抗の電圧依存性を補償する技術
としては、特開平4−29706号公報に記載のものが
ある。これを、図6に従って説明すると、共通のP型基
板21にN型の拡散領域22及び24を形成し、更に拡
散領域22及び24の中にP型領域の抵抗23及び25
を夫々形成する。
As a technique for compensating for such voltage dependence of resistance, there is a technique described in Japanese Patent Laid-Open No. 4-29706. This will be described with reference to FIG. 6. N-type diffusion regions 22 and 24 are formed on a common P-type substrate 21, and the resistances 23 and 25 of the P-type region are formed in the diffusion regions 22 and 24.
Are formed respectively.

【0013】抵抗23の一端Aを、基板21,電圧VD
の固定バイアス電源27の陰極,及び電圧Vn の可変バ
イアス電源28の陰極に接続し、抵抗23の他端Bを抵
抗25の一端Cに接続し、可変バイアス電源28の陽極
を抵抗25の他端Dと拡散領域22に接続し、固定バイ
アス電源27の陽極を拡散領域24に接続する。
One end A of the resistor 23 is connected to the substrate 21 and the voltage VD.
Of the fixed bias power source 27 and the cathode of the variable bias power source 28 of the voltage Vn, the other end B of the resistor 23 is connected to one end C of the resistor 25, and the anode of the variable bias power source 28 is connected to the other end of the resistor 25. D is connected to the diffusion region 22, and the anode of the fixed bias power supply 27 is connected to the diffusion region 24.

【0014】抵抗23及び25の接続部B及びCにおけ
る電圧をV1とおくと、抵抗23のA,B、抵抗25の
C,Dにおける逆バイアス電圧は夫々、Vn ,Vn −V
1,VD −V1,VD −Vn となる。可変バイアス電源
28の電圧Vn が増加すると、抵抗23の逆バイアス電
圧は増加し、抵抗25の逆バイアス電圧は減少する。従
って、抵抗23は増加し、抵抗25は減少するので、抵
抗23と25の直列抵抗はあまり変化しない。Vn が減
少するときも同じである。
When the voltage at the connection points B and C of the resistors 23 and 25 is V1, the reverse bias voltages at A and B of the resistor 23 and C and D of the resistor 25 are Vn and Vn-V, respectively.
1, VD-V1, VD-Vn. When the voltage Vn of the variable bias power source 28 increases, the reverse bias voltage of the resistor 23 increases and the reverse bias voltage of the resistor 25 decreases. Therefore, since the resistance 23 increases and the resistance 25 decreases, the series resistance of the resistances 23 and 25 does not change much. The same is true when Vn decreases.

【0015】しかし、この技術では、図6の構成では効
果があるが、以下に示すように図2の回路では使用でき
ない。図6においてVn を逆極性にすると、拡散領域2
2と抵抗23とが順方向になってしまうので逆極性にで
きないため、図2の回路では使用できない。また電圧依
存性のない抵抗一つ実現するために二つの拡散領域(ウ
ェル)が必要なので集積回路化するのには不利となる。
However, although this technique is effective in the configuration of FIG. 6, it cannot be used in the circuit of FIG. 2 as described below. In FIG. 6, when Vn has a reverse polarity, the diffusion region 2
2 cannot be used in the circuit of FIG. 2 because the resistor 2 and the resistor 23 are in the forward direction and cannot have the opposite polarities. In addition, two diffusion regions (wells) are necessary to realize one resistance having no voltage dependence, which is disadvantageous in forming an integrated circuit.

【0016】また、この他に、薄膜抵抗やポリシリコン
抵抗を用いれば電圧依存性はないので入出力直線性が良
好な反転増幅回路を実現できるが、余分の製造工程が必
要になるという欠点がある。
In addition to this, if a thin film resistor or a polysilicon resistor is used, there is no voltage dependence so that an inverting amplifier circuit having good input / output linearity can be realized, but there is a drawback that an extra manufacturing process is required. is there.

【0017】本発明の目的は、一つのウェルを形成する
のみで拡散抵抗の電圧依存性をなくした半導体抵抗装置
を提供することである。
An object of the present invention is to provide a semiconductor resistance device in which the voltage dependence of diffusion resistance is eliminated by forming only one well.

【0018】本発明の他の目的は、製造工程を増加する
ことなく極めて簡単な構成で拡散抵抗の電圧依存性をな
くした半導体抵抗装置を提供することである。
Another object of the present invention is to provide a semiconductor resistance device which eliminates the voltage dependence of the diffusion resistance with an extremely simple structure without increasing the number of manufacturing steps.

【0019】本発明の更に他の目的は、入出力特性の直
線性を良好にした増幅回路を提供することである。
Still another object of the present invention is to provide an amplifier circuit having good linearity of input / output characteristics.

【0020】[0020]

【課題を解決するための手段】本発明による半導体抵抗
装置は、第1導電型の半導体基板と、この半導体基板の
一主表面上に形成された第2導電型の不純物領域と、こ
の不純物領域内に形成された第1導電型の抵抗領域とを
含み、前記不純物領域は電位的に解放の状態にて使用す
ることを特徴とする。
A semiconductor resistance device according to the present invention is a semiconductor substrate of a first conductivity type, a second conductivity type impurity region formed on one main surface of the semiconductor substrate, and the impurity region. And a resistance region of the first conductivity type formed therein, the impurity region being used in a state of being electrically released.

【0021】本発明による他の半導体装置は、前記不純
物領域に第1及び第2の不純物領域を設け、これ等第1
及び第2の不純物領域の各々に前記抵抗領域である第1
及び第2の抵抗領域を夫々形成して、前記第1及び第2
の不純物領域を電位的に解放の状態にて使用することを
特徴とする。
In another semiconductor device according to the present invention, first and second impurity regions are provided in the impurity region.
And the first impurity region which is the resistance region in each of the second impurity regions.
And a second resistance region, respectively, to form the first and second resistance regions.
It is characterized in that the impurity region of is used in a released state in terms of potential.

【0022】本発明による増幅回路は、前記第1の抵抗
領域をオペアンプの入力抵抗とし、第2の抵抗領域をオ
ペアンプの帰還抵抗としたことを特徴としている。
The amplifier circuit according to the present invention is characterized in that the first resistance region serves as an input resistance of the operational amplifier and the second resistance region serves as a feedback resistance of the operational amplifier.

【0023】[0023]

【作用】半導体基板上に形成されたウェル内に抵抗領域
を形成した場合、ウェルを電位的に解放状態のフローテ
ィングとして使用することにより、抵抗領域とウェルと
の間のPN接合部は通常低い順バイアス状態に維持され
る。よって、抵抗領域にいかなる電圧が印加されても、
ウェルの電位も当該抵抗領域の電圧に従って変化して低
い順バイアス状態に維持され、逆バイアスになることは
く、空乏層が生じない。
When the resistance region is formed in the well formed on the semiconductor substrate, the well is used as a floating state in which the potential is released so that the PN junction between the resistance region and the well is normally in the lower order. Bias is maintained. Therefore, no matter what voltage is applied to the resistance region,
The potential of the well also changes in accordance with the voltage of the resistance region and is maintained in a low forward bias state, is not reverse biased, and a depletion layer does not occur.

【0024】その結果、抵抗の電圧依存性がなくなり、
増幅回路に適用した場合、入出力特性が非直線性となる
ことはない。
As a result, the voltage dependence of the resistance disappears,
When applied to an amplifier circuit, the input / output characteristics will not be non-linear.

【0025】[0025]

【実施例】以下に図面を用いて本発明の実施例について
説明する。
Embodiments of the present invention will be described below with reference to the drawings.

【0026】図1は本発明の実施例の構成を示す図であ
る。図3と同等部分は同一符号により示されている。図
1において、P型半導体基板11の一主表面上には、2
つのNウェル12及び14が形成されており、これ等N
ウェル12,14の各々にはP型抵抗領域13,15が
不純物拡散法やイオン注入法等により形成されている。
FIG. 1 is a diagram showing the configuration of an embodiment of the present invention. The same parts as in FIG. 3 are designated by the same reference numerals. In FIG. 1, 2 is formed on one main surface of the P-type semiconductor substrate 11.
N wells 12 and 14 are formed.
P-type resistance regions 13 and 15 are formed in each of the wells 12 and 14 by an impurity diffusion method, an ion implantation method, or the like.

【0027】そして、P型基板11には回路の最低電位
であるアース電位が供給されており、Nウェル12,1
4は本例ではフローティング(電位的に開放)状態とさ
れている。
The P-type substrate 11 is supplied with the ground potential which is the lowest potential of the circuit, and the N wells 12 and 1
In this example, 4 is in a floating (potentially open) state.

【0028】ここで、抵抗13とNウェル12,Nウェ
ル12と基板11の各PN接合部の飽和電流を夫々IS
1,Is2とし、ボルツマン定数をk,電子の電荷をq,
絶対温度をTとし、VT =kT/qとおいて、抵抗13
に基板11に対して正の電圧を印加したとすると、抵抗
13とNウェル12との間のPN接合部の電圧V1は、 V1=VT ln{(IS1+IS2)/IS1} と表わされる。
Here, the saturation currents of the resistor 13 and the N well 12, and the saturation currents of the N well 12 and the PN junctions of the substrate 11 are respectively determined by Is.
1, Is2, Boltzmann constant k, electron charge q,
If the absolute temperature is T and VT = kT / q, the resistance 13
If a positive voltage is applied to the substrate 11, the voltage V1 at the PN junction between the resistor 13 and the N well 12 is expressed as V1 = VT ln {(IS1 + IS2) / IS1}.

【0029】ここで、IS1=IS2とし、VT =30mV
とすると、V1は21mVとなり、上記PN接合部は順
バイアス状態(PN接合のオン電流が流れる閾値電圧よ
りも小さい順バイアス状態)となる。よって、抵抗13
には空乏層は発生せず、その結果抵抗の電圧依存性もな
くなるのである。
Here, it is assumed that IS1 = IS2 and VT = 30 mV
Then, V1 becomes 21 mV, and the PN junction becomes a forward bias state (a forward bias state smaller than the threshold voltage at which the ON current of the PN junction flows). Therefore, the resistance 13
There is no depletion layer in the gate, and as a result, the voltage dependence of the resistance disappears.

【0030】Nウェル14と抵抗15との間のPN接合
部においても全く同様に空乏層は生じないので、これま
た、抵抗の電圧依存性がなくなる。
At the PN junction between the N well 14 and the resistor 15, a depletion layer does not occur at all, so that the voltage dependency of the resistor also disappears.

【0031】従って、図2に示した反転増幅回路の入力
抵抗2と帰還抵抗4とに図1の構造の抵抗13,15を
夫々使用すれば、この反転増幅回路の入出力特性は図5
の破線52で示すようなほぼ理想的な直線性を呈するこ
とになるのである。
Therefore, if the resistors 13 and 15 having the structure shown in FIG. 1 are used for the input resistor 2 and the feedback resistor 4 of the inverting amplifier circuit shown in FIG. 2, the input / output characteristics of this inverting amplifier circuit will be as shown in FIG.
Thus, it exhibits almost ideal linearity as indicated by the broken line 52 in FIG.

【0032】尚、上記実施例では、図2に示す反転増幅
回路につき説明したが、一般には増幅回路の増幅度を決
定する抵抗に図1の構成の半導体抵抗を用いれば、増幅
度は印加電圧に依存することなく一定に維持でき、直線
性の良い増幅回路が得られるものである。
In the above embodiment, the inverting amplifier circuit shown in FIG. 2 has been described, but generally, if the semiconductor resistor having the structure of FIG. 1 is used as the resistor for determining the amplification degree of the amplifier circuit, the amplification degree is the applied voltage. It is possible to obtain an amplifier circuit having good linearity, which can be maintained constant without depending on.

【0033】また、図1の構造では、2つの抵抗素子を
形成した場合について示しているが、3つ以上の抵抗素
子の場合にも、各ウェルを夫々形成して各ウェル内に抵
抗領域を形成して得られる構造とし、各ウェルはフロー
ティングとして使用される。また、当然に1つの抵抗素
子にも同様に適用できることは明らかである。
In the structure of FIG. 1, two resistance elements are formed, but in the case of three or more resistance elements, each well is formed and a resistance region is formed in each well. Each well is used as a floating structure. Also, it goes without saying that the same can be applied to one resistance element.

【0034】更に、半導体装置の各部導電型は上記実施
例とは逆のものを用いても良いことは明らかである。
Further, it is obvious that the conductivity type of each part of the semiconductor device may be opposite to that of the above embodiment.

【0035】[0035]

【発明の効果】以上述べた如く、本発明によれば、不純
物拡散抵抗を電位的にフローティング状態とすることに
より空乏層をなくすことができるので、抵抗値の電圧依
存性がなくなるという効果がある。
As described above, according to the present invention, it is possible to eliminate the depletion layer by setting the impurity diffused resistance to a floating state in terms of potential, so that there is an effect that the voltage dependency of the resistance value is eliminated. .

【0036】また、この電圧依存性のない半導体抵抗を
増幅回路の増幅度を決定する抵抗素子に適用すれば、増
幅度が電圧依存性を有さなくなるので、直線性の良い増
幅回路が得られるものである。
If this semiconductor resistor having no voltage dependency is applied to the resistance element that determines the amplification factor of the amplifier circuit, the amplification factor has no voltage dependency, so that the amplifier circuit having good linearity can be obtained. It is a thing.

【0037】更に、半導体装置の各部導電型は上記実施
例とは逆のものを用いても良いことは明らかである。
Further, it is obvious that the conductivity type of each part of the semiconductor device may be opposite to that of the above-mentioned embodiment.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例の半導体抵抗装置の断面図であ
る。
FIG. 1 is a sectional view of a semiconductor resistance device according to an embodiment of the present invention.

【図2】本発明の半導体抵抗装置が適用される反転増幅
回路の例を示す図である。
FIG. 2 is a diagram showing an example of an inverting amplifier circuit to which the semiconductor resistance device of the present invention is applied.

【図3】従来の半導体抵抗装置の断面図である。FIG. 3 is a cross-sectional view of a conventional semiconductor resistance device.

【図4】図3の抵抗装置の電圧依存性を有する図であ
る。
FIG. 4 is a diagram with voltage dependence of the resistance device of FIG.

【図5】図2の反転増幅回路の入出力特性を、従来例と
本発明とにより比較して示したものである。
5 shows the input / output characteristics of the inverting amplifier circuit of FIG. 2 in comparison with a conventional example and the present invention.

【図6】従来の他の半導体抵抗装置の断面図である。FIG. 6 is a cross-sectional view of another conventional semiconductor resistance device.

【符号の説明】[Explanation of symbols]

1 信号源 2 入力抵抗 4 帰還抵抗 7 オペアンプ 11 半導体基板 12,14 不純物領域(ウェル) 13,15 抵抗領域 1 signal source 2 input resistance 4 feedback resistance 7 operational amplifier 11 semiconductor substrate 12 and 14 impurity region (well) 13 and 15 resistance region

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 第1導電型の半導体基板と、この半導体
基板の一主表面上に形成された第2導電型の不純物領域
と、この不純物領域内に形成された第1導電型の抵抗領
域とを含み、前記不純物領域は電位的に解放の状態にて
使用することを特徴とする半導体抵抗装置。
1. A semiconductor substrate of a first conductivity type, an impurity region of a second conductivity type formed on one main surface of the semiconductor substrate, and a resistance region of a first conductivity type formed in the impurity region. And a semiconductor resistance device, wherein the impurity region is used in a state of being electrically released.
【請求項2】 前記第1導電型はP型であり、前記第2
の導電型はN型であり、前記半導体基板には回路の最低
電位が付与されていることを特徴とする請求項1記載の
半導体抵抗装置。
2. The first conductivity type is P-type, and the second conductivity type is P-type.
2. The semiconductor resistance device according to claim 1, wherein the conductivity type is N type, and the lowest potential of the circuit is applied to the semiconductor substrate.
【請求項3】 前記不純物領域は第1及び第2の不純物
領域を有し、これ等第1及び第2の不純物領域の各々に
前記抵抗領域である第1及び第2の抵抗領域が夫々形成
されており、前記第1及び第2の不純物領域は電位的に
解放の状態にて使用することを特徴とする請求項1また
は2記載の半導体抵抗装置。
3. The impurity region has first and second impurity regions, and first and second resistance regions, which are the resistance regions, are formed in each of the first and second impurity regions. 3. The semiconductor resistance device according to claim 1, wherein the first and second impurity regions are used in a state of being electrically released.
【請求項4】 請求項1記載の半導体抵抗装置を増幅度
を決定する抵抗素子に使用したことを特徴とする増幅回
路。
4. An amplifier circuit, wherein the semiconductor resistance device according to claim 1 is used as a resistance element for determining an amplification degree.
【請求項5】 請求項3記載の前記第1の抵抗領域を演
算増幅器の入力抵抗に使用し、前記第2の抵抗領域を前
記演算増幅器の帰還抵抗に使用することを特徴とする増
幅回路。
5. An amplifier circuit, wherein the first resistance region according to claim 3 is used as an input resistance of an operational amplifier, and the second resistance region is used as a feedback resistance of the operational amplifier.
JP5642394A 1994-03-28 1994-03-28 Semiconductor resistance device and amplifier circuit using it Pending JPH07273287A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5642394A JPH07273287A (en) 1994-03-28 1994-03-28 Semiconductor resistance device and amplifier circuit using it

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5642394A JPH07273287A (en) 1994-03-28 1994-03-28 Semiconductor resistance device and amplifier circuit using it

Publications (1)

Publication Number Publication Date
JPH07273287A true JPH07273287A (en) 1995-10-20

Family

ID=13026698

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5642394A Pending JPH07273287A (en) 1994-03-28 1994-03-28 Semiconductor resistance device and amplifier circuit using it

Country Status (1)

Country Link
JP (1) JPH07273287A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6229379B1 (en) 1997-11-17 2001-05-08 Nec Corporation Generation of negative voltage using reference voltage

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6229379B1 (en) 1997-11-17 2001-05-08 Nec Corporation Generation of negative voltage using reference voltage

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