JPH07273286A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To provide a semiconductor integrated circuit which is operated at a low voltage without lowering a power supply voltage supplied from the outside and whose power consumption is lowered. CONSTITUTION:Two circuit blocks 11, 12 which constitute an integrated circuit are constituted so as to be operatable at a power supply voltage which is lower than a power-supply voltage VDD supplied from the outside, and they are stacked longitudinally between a VDD line 14 and a GND line 15. The first circuit block 1 is operated within a voltage range of (1/2) VDD to VDD, and the second circuit block 12 is operated within a voltage range of 0 to (1/2) VDD. In order to match the circuit blocks 11, 12 with an external circuit within a signal voltage range of 0 to VDD, an input/output circuit block 12 which is operated at the power supply voltage VDD and which has a level conversion function is installed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit whose power consumption is reduced by low voltage operation.

[0002]

2. Description of the Related Art Miniaturization of elements of semiconductor integrated circuits in recent years,
High integration is remarkable. If the element is downsized, it is necessary to lower the operating voltage and the operating current of the element in terms of breakdown voltage and reliability. If the operable voltage and the operable current of the element are reduced, the power supply voltage used can be lowered and the power consumption of the integrated circuit can be reduced.

[0003]

However, even if the operable voltage of a certain integrated circuit is lowered, the power supply voltage used in the system in which it is used is usually fixed, and the signal level with other circuit elements is low. Because it is necessary to match
The power supply voltage of the integrated circuit cannot be lowered by itself. An object of the present invention is to provide a semiconductor integrated circuit capable of low power consumption by performing low voltage operation without lowering the power supply voltage supplied from the outside.

[0004]

A semiconductor integrated circuit according to the present invention includes at least first and second integrated circuits.
Power supply voltage V supplied from the outside to the two circuit blocks
It is configured to be operable at a power supply voltage lower than DD and is vertically stacked between a power supply line and a ground line, and an internal power supply voltage obtained by dividing the power supply voltage VDD at a predetermined ratio is supplied to these first and second circuit blocks. It is characterized by doing so. The present invention is also a semiconductor integrated circuit to which a power supply voltage VDD is supplied from the outside, wherein the integrated circuit has m <N and m
-A first circuit block that operates at a power supply voltage of VDD / N and a second circuit block that operates at a power supply voltage of (Nm) -VDD / N are included, and the power supply voltage VDD is m-VDD / N. It is characterized in that it is divided into (N−m) · VDD / N and supplied to the first and second circuit blocks respectively. In the present invention, preferably, an output terminal is connected to a connection node of the first and second circuit blocks, and a current buffer is provided for supplying or discharging a current in a direction of suppressing a potential fluctuation of the connection node.

[0005]

According to the present invention, the integrated circuit is divided into several circuit blocks and stacked vertically within the range of the power supply voltage, so that the power supply voltage supplied from the outside is not lowered and each circuit block is substantially The operating voltage of can be lowered.
As a result, the power consumption of the integrated circuit can be reduced. Further, by providing the current buffer so as to suppress the potential fluctuation of the connection node of the circuit block, it is possible to stabilize the voltage shared by each circuit block, and thus the operation of each circuit block.

[0006]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a block configuration of a semiconductor integrated circuit according to an embodiment of the present invention. The internal circuit is divided into a plurality of circuit blocks, and a first circuit block 11 and a second circuit block 11 are provided between a power supply (VDD) line 14 and a ground (GND) line 15 to which a power supply voltage VDD from the outside is supplied. Circuit block 1
2 are stacked vertically in series. First circuit block 11
Since all the currents flowing through the second circuit block 12 flow in the second circuit block 12, assuming that the equivalent impedances of these circuit blocks 11 and 12 are substantially equal in the steady operation state, the connection node 16 between these circuit blocks 11 and 12 is Almost (1
/ 2) It is kept at VDD.

Therefore, the first circuit block 11 operates in the voltage range (1/2) VDD to VDD, and the second circuit block 12 operates in the voltage range 0 to (1/2) VDD. Since the two circuit blocks 11 and 12 operate in different voltage ranges in this way, it is necessary to match them with an external circuit. Therefore, the input / output circuit block 13 that operates at the power supply voltage VDD is provided. I / O circuit block 13
Has a level conversion function for converting the above-mentioned signal voltage levels of the first and second circuit blocks 11 and 12 into signal voltage levels of 0 to VDD.

The effect of reducing the power consumption of the integrated circuit according to this embodiment will be described with reference to FIGS. Figure 2
It is assumed that (a) is a normal integrated circuit configuration and has a circuit area S, which is divided into two circuit blocks each having a circuit area S / 2 as shown in FIG. 2 (b). Since this integrated circuit is a logic circuit that operates at the clock frequency F and the circuit impedance seen from the power supply unit is inversely proportional to the circuit area, the power consumption W1 of the circuit in the state of FIG.
Is expressed by the following equation 1 using a proportional constant k.

[0009]

[Equation 1] W1 = kFVDD ² S

On the other hand, in the state of FIG. 2 (b), the power consumption W2 of all circuits is expressed by the following equation 2.

[0011]

[Expression 2] W2 = 2 × kF (VDD / 2) ² (S / 2) = k
FVDD ² S / 4

By dividing the circuit into two blocks and stacking them vertically in the power supply voltage range as described above, the power consumption can be reduced to 1/4 as compared with the usual integrated circuit configuration.

In the above embodiment, the circuit block is divided into two circuit blocks, but it may be divided into three or more circuit blocks. Generally, if the circuit block is divided into n so that the power supply voltage is equally divided into n, the power consumption becomes 1 / n ² . This will be specifically described with reference to FIGS. 3A and 3B as follows. FIG. 3A shows a normal integrated circuit configuration, and the average current consumption is I. When the circuit blocks are divided into n circuit blocks and vertically stacked as shown in FIG. 3B, the area of each circuit block becomes 1 / n and these are in series. Therefore, the impedance viewed from the VDD terminal is shown in FIG. 1 / n ^{2 in} the case of a), and thus the average current consumption is I / n ² .
Then, the total power consumption in the state of FIG.

[0014]

[Expression 3] W = n × (VDD / n) · (I / n ² ) = VDD · I / n ²

In the present invention, it is not always necessary that the power supply voltage is equally divided by the vertically stacked circuit blocks. For example, in the embodiment of FIG. 1, even if all the currents flowing through the first circuit block 11 flow through the second circuit block 12, if the average circuit impedances thereof are different, the voltage of the connection node 16 as the dividing point is (1/2) The value deviates from VDD. Further, the division ratio of this voltage may not be an integer ratio. Generally, for m <N,
A first circuit block that operates at a power supply voltage of m · VDD / N and a second circuit block that operates at a power supply voltage of (N−m) · VDD / N are divided and vertically stacked. The power supply voltage VDD may be divided into mVDD / N and (N−m) VDD / N to be supplied.

Maintaining a stable voltage division ratio is important for stabilizing circuit operation. FIG. 4 shows an embodiment in which such means for stabilizing the voltage division ratio is added. As shown in FIG. 4A, a voltage divider circuit including resistors R1 and R2 and a current buffer 17 are provided.
The output terminal 7 is connected to the connection node 16 of the first and second circuit blocks 11 and 12. Current buffer 17
When the connection node 16 changes in potential, current is supplied or discharged so as to suppress the change in potential. FIG. 4B shows a more specific embodiment, in which the resistance R1,
A series circuit of NPN transistor Q1 and PNP transistor Q2 in which a diode D1 and D2 are interposed between R2 and a base-emitter voltage is defined by these diodes D1 and D2 is provided between VDD and GND.

The operation of stabilizing the voltage division ratio according to this embodiment will be described below with reference to FIG. 4 (b). Conditions are set in the transistors Q1 and Q2 so that equal currents flow when the potential of the connection node 16 is a prescribed potential, for example, (1/2) VDD. At this time, regardless of the currents on the transistors Q1 and Q2 side, all the currents flowing through the circuit block 11 flow into the circuit block 12, and the currents in these circuit blocks 11 and 12 are kept equal. When the potential of the connection node 16 decreases, the NPN transistor Q1 is biased in a deeper ON direction and the PNP transistor Q2 is biased in an OFF direction. As a result, the current of the transistor Q1 is partially supplied to the circuit block 12 and the potential drop of the connection node 16 is suppressed.
When the potential of the connection node 16 rises above the steady state,
The bias relationship between the transistors Q1 and Q2 is opposite to the above, and the first transistor is turned on via the transistor Q2 whose ON is deeper.
Part of the current of the circuit block 11 is discharged. As a result, the potential rise of the connection node 16 is suppressed.

In addition to the current buffer 17 for stabilizing the voltage division ratio, when the consumption currents required by the first circuit block 11 and the second circuit block 12 are different,
It is also effective to have a bypass path for supplying or discharging the difference. First and second circuit blocks 11, 1
If the two are stacked vertically and there is no other current supply or discharge path, the same current necessarily flows through them as described above. On the other hand, when the current required by the second circuit block 12 is larger than that of the first circuit block 11, a current bypass is provided on the first circuit block 11 side. Conversely, when the current required by the first circuit block 11 is large, a current bypass is provided on the second circuit block 12 side. As described above, the current of the vertically stacked circuit blocks can be made different.

FIG. 5 shows a plurality of circuit areas A in one chip.
In B, C and D, there are shown embodiments in which circuit blocks are vertically stacked with different voltage division ratios. Figure 6
5 is an example of a layout in the chip of the circuit areas A, B, C and D of FIG.

In the above-described embodiments, the description has been made on the assumption that signals are not exchanged between the vertically stacked circuit blocks. However, normally, when an integrated circuit is divided into a plurality of circuit blocks, it is necessary to exchange signals between them. In the present invention, a plurality of circuit blocks operate in different voltage ranges, so that level adjustment within the integrated circuit is necessary for these circuit blocks to exchange signals.

FIG. 7 shows an embodiment in consideration of such signal level matching. The main part of the internal circuit is divided into a first circuit block 21 and a second circuit block 22,
As in the previous embodiment, these are vertically stacked in the range of the power supply voltage VDD. The signal supplied to the input terminal IN is assumed to have a logical amplitude of 0 to VDD, for example, and the input circuit 24 operating at the power supply voltage VDD supplies (1 /
2) Converted to a signal having a logical amplitude of VDD to VDD and supplied to the first circuit block 21. First circuit block 21
Output signal of 0 to (1 /
2) Converted to a VDD logical amplitude signal and supplied to the second circuit block 22. The output of the second circuit block 22 is converted into a signal having a logical amplitude of 0 to VDD in the output circuit 25 operating at the power supply voltage VDD, and the output terminal OU
It is output from T. As a result, when the internal circuit is divided into circuit blocks that operate in different voltage regions, matching in the internal circuit and matching with the external circuit can be achieved.

[0022]

As described above, according to the present invention, the internal circuit of the integrated circuit is divided into a plurality of blocks and stacked vertically within the power supply voltage range, so that the external circuit can be operated without lowering the external power supply voltage. It is possible to effectively reduce the power consumption of the integrated circuit while maintaining the consistency with.

[Brief description of drawings]

FIG. 1 shows a configuration of an integrated circuit according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining an effect of the same embodiment.

FIG. 3 is a diagram for explaining an effect when dividing into n.

FIG. 4 shows a configuration of an embodiment in which a division ratio stabilizing means is added.

FIG. 5 shows a configuration of an embodiment in which a plurality of circuit blocks having different division ratios are mixed.

FIG. 6 shows a chip layout example of the embodiment of FIG.

FIG. 7 shows a configuration of an embodiment considering internal level matching.

[Explanation of symbols]

11 ... 1st circuit block, 12 ... 2nd circuit block, 13 ... I / O circuit block, 14 ... Power supply (VDD)
Line, 15 ... Ground (GND) line, 16 ... Connection node.

Claims (3)

[Claims] 1. At least a first of the integrated circuits,
The second two circuit blocks are configured to be operable at a power supply voltage lower than the power supply voltage VDD supplied from the outside and vertically stacked between the power supply line and the ground line. A semiconductor integrated circuit characterized in that an internal power supply voltage obtained by dividing the power supply voltage VDD at a predetermined ratio is supplied. 2. A semiconductor integrated circuit to which a power supply voltage VDD is supplied from the outside, wherein the integrated circuit has a first circuit block operating at a power supply voltage of m · VDD / N, where m <N. (N−m) · VDD / N including the second circuit block operating at the power supply voltage, the power supply voltage VDD is m · VDD / N
And (N−m) · VDD / N divided into the first,
A semiconductor integrated circuit characterized by being supplied to a second circuit block. 3. An output terminal is connected to a connection node of the first and second circuit blocks, and the current buffer has a current buffer for supplying or discharging a current in a direction of suppressing a potential variation of the connection node. Item 3. The semiconductor integrated circuit according to item 1 or 2.