JPH07272488A - Memory circuit with backup function - Google Patents

Abstract

PURPOSE:To obtain a compact, light-weight, thin and low-cost memory circuit with a backup function without, using a microcomputer or the like. CONSTITUTION:While a power source is turned ON, a capacitance C3 is charged in accordance with a signal of a data line. When the power is not supplied, a charge-controlling part 1 maintains a control impedance to the C3 high. During the supply of power, the signal is fed back to the data line so that the charge- controlling part 1 supplies a charging current when a charge in the C3 is not smaller than a predetermined value. When the power is not supplied, a charge- detecting part 2 holds a connection impedance to tame C3 high. Therefore, even waxen a data is destroyed as the power source is turned ON again after being interrupted although a data indication signal is impressed to the data line, if a predetermined or more amount of charges are present in the C3, the charge-detecting part 2 sends a signal to the data line to charge the C3 again, so that the stored data is backed up. This constitution makes it possible to back up a memory without using a microcomputer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory circuit having a backup function. More specifically, the present invention is
The present invention relates to a memory circuit with a backup function for storing information according to the amount of charges charged in a capacitor even when power is not supplied.

The present invention is particularly applicable to a memory circuit with a backup function, which is used to store the set state of the anti-theft function in a device installed in a vehicle for the anti-theft function, but only to that. Not limited.

[0003]

2. Description of the Related Art In recent years, in vehicles, in order to prevent vehicle theft, a set state of an antitheft function is stored in a memory circuit during the period from the time the driver gets off the vehicle to the next time the driver gets on the vehicle. During the period in which the above-mentioned set state is stored, a device for operating various anti-theft functions has been implemented.

In such a memory circuit, in order to retain the memory of the set state even if the battery is temporarily removed by malicious intent to cancel the antitheft function improperly, a period during which power is not supplied is provided. It is required to have a backup function that retains memory.

FIG. 5 (a) is a block diagram showing a conventional example of such a memory circuit with a backup function.
An explanation will be given based on the flowchart shown in (b).

When the driver gets off the vehicle, the CPU 202
The output potential of port 206 to low and the output of port 205.
The force potential is set to High. By this control,
Dista TR₂₁₃Conducts and current is drawn from battery 200
Transistor TR₂₁₃, Resistance R ₂₂₂, Diode D₂₂₃To
Through capacitor C₂₁₀Flow to the capacitor C₂₁₀Is
Be charged.

When the driver gets on the vehicle, the output potential of the port 206 is set to High by the CPU 202.
The 205 output potential is set to Low. By the control, the transistor TR ₂₁₁ and the transistor TR ₂₁₂ are turned on, and a current _flows from the capacitor C ₂₁₀ to the transistor T _212.
It flows to the ground through R ₂₁₂ , and the capacitor C ₂₁₀
The charged charge of is discharged.

In the CPU 202, the potential of the capacitor C ₂₁₀ is read via the port 207. The anti-theft function is executed during the period when the potential is High. In the CPU 202, the control is
The operation is continued while the battery 200 is connected and power is supplied.

If the battery 200 is removed while the capacitor C ₂₁₀ is being charged with electric charges as described above, the CPU 202 cannot execute such control. Then, when the battery 200 is reconnected, in the CPU 202, the reset circuit 2
The reset signal output from 01 executes the control shown in FIG.

In step H270, the port 20
The potential of the capacitor C ₂₁₀ is read via 7.
If the potential is High, the process proceeds to step H271 to re-execute the theft prevention function.

[0011]

In such a conventional memory circuit with a backup function, an information code is assigned to the charge charge amount of the capacitor and the charge / discharge of the capacitor is controlled under the control of the microcomputer to provide the backup function. Although it is realized, the configuration uses a microcomputer, which is a large component, and therefore, it is not easy to reduce the size, weight, and thickness, and the cost increases. .

The technical problem of the present invention is to pay attention to such a problem, and to propose a memory circuit with a backup function, which can be easily reduced in size, weight and thickness and can be reduced in cost. Especially.

[0013]

FIG. 1 is a block diagram for explaining the basic principle of the present invention. The memory circuit with backup function of the present invention is for storing information by the amount of charge charged in the capacitor C ₃ even during the period when power is not supplied, and is applied to the data line during the period when power is supplied. A charging control unit 1 that supplies a charging current to the capacitor C ₃ in accordance with a signal that maintains the connection impedance with the capacitor C ₃ in a high impedance state during a period in which power is not supplied.
While the power is being supplied, the capacitor C
_When the charging charge amount of ₃ is a predetermined amount or more, the charging control unit 1 feeds back a signal to the data line so as to supply the charging current, and when the power is not supplied, the capacitor C ₃ and And a charge detection unit 2 for keeping the connection impedance of the device in a high impedance state.

It should be noted that maintaining the connection impedance of the capacitor C ₃ in a high impedance state means that in the line connecting the capacitor C ₃ and the component,
It means that the semiconductor is cut off to eliminate the conduction, and the line is disconnected by a relay contact to eliminate the conduction.

Further, in order to discharge the charge charged in the capacitor C ₃ , the charge control unit 1 and the capacitor C ₃ are discharged.
It is desirable that the line connecting to and be connected to the reset circuit.

[0016]

If there is information to be stored even if the power is cut off during a certain period of time, a signal instructing the information is connected to the data line, and the signal is applied to the data line in the charging control unit 1. If the charging current is supplied when the charging is performed, the information is stored by the charging charge of the capacitor C ₃ .

The information stored in this way is stored in the capacitor by keeping the connection impedance of the charge controller 1, the charge detector 2 and the capacitor C ₃ in a high impedance state even when the power supply is cut off. The amount of discharged electric charge of C ₃ is suppressed, and it is held within a period in which there is no inconvenience in practical use.

[0018] Then, even when the signal is lost by the signal indicating the information to the data line is turned on again been cut power to have been applied, the capacitor C ₃ When the charge amount of a predetermined amount or more is charged, the charge detection unit 2 applies a signal to the data line to charge the capacitor C ₃ again.

Thus, the information is the capacitor C
If stored by a charge of ₃ , the signal on the data line will automatically recover to point to the information and the storage of the information will be backed up.

In the memory circuit with backup function of the present invention, the memory is backed up without using a microcomputer in this way, so that the number of large parts can be reduced and the device can be easily made small, lightweight and thin. To Also, the cost is reduced when the number of large parts is reduced.

[0021]

EXAMPLES Next, examples of how the memory circuit with backup function according to the present invention is actually embodied will be described.

[Outline of Vehicle Theft Prevention Device]
First, based on the block diagram shown in FIG. 2, an outline of a vehicle theft prevention device mounted on a vehicle will be described. The immobilizer ECU 15 that controls the traveling stop function that is a kind of vehicle theft prevention function is connected to the security ECU 12 that controls an alarm output that is also a kind of the vehicle theft prevention function.

In the security ECU 12, the radio signal transmitted from the transmitter 14 is received by the antenna 13, and the owner is identified by the received signal. When the owner is confirmed in this way, a control code instructing to set the traveling stop function to the reset state is serially transferred from the security ECU 12 to the immobilizer ECU 15.

The security ECU 12 also detects whether or not the door is open, whether or not the window glass is damaged, etc., and these detection results may be stolen. When it is present, the alarm output, display on the indicator 15 and the like are performed.

In the immobilizer ECU 15, the control code sent from the security ECU 12 is received and decoded by the serial communication unit 26. When the decoding result indicates that the traveling stop function is to be reset, the serial communication unit 26 applies High to the base of the transistor TR ₂₈ .

At this time, the transistor TR ₂₈ is turned on and a low level is applied to the reset line 37, and the output connected to the data line 38 in the key detection section 22 becomes open. In the storage unit 30, as will be described later, the charge stored in the built-in capacitor is discharged and the data line
38 becomes Open. The memory circuit with a backup function of the present invention is applied to the storage unit 30.

In this way, the data line 38 is
When open, transistor TR ₂₉ shuts off and relay R
L ₂₀ , relay RL ₂₁ , relay RL ₃₁ are not excited. In this state, when the key 10 is set to ST, the relay RL ₃₂ is excited by the battery 11 through the b contact (break contact) of the relay RL ₃₁ . Then, the starter motor M ₃₄ is driven by the battery 11 through the b contact of the relay RL ₃₁ and the a contact (make contact) of the relay RL ₃₂ .

Further, the excitation state of the relay RL ₃₃ is made through the b contact of the relay RL ₂₀ and the relay RL ₂₁ to indicate that the EFI-ECU.
When the key 10 is set to IG, the fuel pump motor M ₃₅ is driven by the battery 11 through the a contact of the relay RL ₃₃ according to the control.

On the other hand, when the key 10 is turned off and pulled out, the key detector 22 detects the operation and applies High to the output connected to the data line 38. When a high voltage is applied to the data line 38, the storage unit
At 30, as will be described later, a charging current flows through a built-in capacitor, and the charge is stored in the capacitor.

Further, the transistor TR ₂₉ becomes conductive, and the relay RL ₂₀ , the relay RL ₂₁ , and the relay RL ₃₁ are excited by the battery 11. Therefore, the starter motor M ₃₄ and the fuel pump motor M
_The relay ₃₅ is disconnected from the battery 11 by opening the contact b of the relay RL ₃₁ , and the vehicle cannot run.

When the battery 11 is disconnected and reconnected in such a state, the detection result is reset in the key detection section 22, and the output connected to the data line 38 becomes open. However, in the storage unit 30 to which the present invention is applied, as will be described later, it is detected that the charge stored in the built-in capacitor remains, and High is applied to the data line 38. .

Therefore, even if the battery 11 is removed and reconnected in this way, the above-described traveling stop function is continued.

[First Embodiment of the Present Invention] Next, the configuration of the first embodiment of the present invention applied to the storage unit 30 will be described with reference to the circuit diagram shown in FIG. .

The other end of the resistor R ₅₅ , one end of which serves as a data line, is connected to the base of the transistor TR ₅₁ . The emitter of the transistor TR ₅₁ is grounded. One end of the resistor R ₅₆ is connected to the base of the transistor TR ₅₁ ,
The other end is grounded. The resistor R ₅₇ has one end connected to the collector of the transistor TR ₅₁ and the other end connected to the base of the transistor TR ₅₂ .

Resistance R₅₈, One end has a power supply V_BContact
And the other end is the transistor TR ₅₂Connected to the base of
Be done. The transistor TR₅₂The emitter of is the power source V_B
Connected to. The transistor TR₅₂The collector of the die
Aether D₆₀Is connected to the high potential side forming the forward direction.
The diode D₆₀The low potential side that forms the forward direction of
₅₉Connected to one end of. The resistance R₅₉The other end is grounded at one end
Capacitor C₅₀Is connected to the other end of.

One end of the power source V_BResistor R connected to₆₄
The other end of is a transistor TR₅₄Connected to the base of. The
Langista TR₅₄The emitter of is grounded. Resistance R₆₃To
However, one end is the transistor TR₅₄Connected to the base of
And the other end is grounded. Resistance R ₆₂In one end is
Transistor TR₅₄Connected to the collector of the
Dista TR₅₃Connected to the base of.

The resistor R ₆₁ has one end connected to the base of the transistor TR ₅₃ and the other end connected to the transistor TR _53.
Connected to ₅₃ emitters. The emitter of the transistor TR ₅₃ is also connected to the line connecting the diode D ₆₀ and the resistor R ₅₉ . The collector of the transistor TR ₅₃ is connected to the data line.

The transistor TR ₅₁ is an NPN type,
The transistor TR ₅₂ is a PNP type transistor, and the transistor TR is
₅₃ is a PNP type, and the transistor TR ₅₄ is an NPN type. The line connected to the emitter of the transistor TR ₅₃ is used as a reset line.

Next, based on the time chart shown in FIG.
Next, the operation of the configuration will be described. Now
The capacitor C₅₀When there is no charge on the
Tick t ₇₀High is applied to the data line at
And the transistor TR₅₁, The transistor TR₅₂Led by
Through, the transistor TR₅₂, The diode D₆₀,Previous
Resistance R₅₉Through the power source V_BFrom the capacitor
C₅₀Is supplied with charging current. And the capacitor
C₅₀Is charged.

When the reset line is grounded at time t ₇₁ when the capacitor C ₅₀ is charged, the capacitor C ₅₀ is connected through the resistor R _59.
The charge of ₅₀ is discharged.

Next, the operation in this configuration will be described based on the time chart shown in FIG. Now
In the state where the capacitor C ₅₀ is not charged,
Wherein at time t ₇₂ supply V _B is disconnected, and the power source V _B are reconnected at time t _73. At this time,
If the data line is open, the transistor
TR ₅₃ is cut off, and the transistor TR ₅₁ and the transistor TR ₅₂ are also cut off. Therefore,
The capacitor C ₅₀ is not charged.

That is, even if the power source V _B is disconnected and reconnected while the capacitor C ₅₀ is not storing information,
The capacitor C ₅₀ is not charged, and a signal (Open) indicating that there is no stored information is output to the data line.

Next, based on the time chart shown in FIG.
Next, the operation of the configuration will be described. Now
The capacitor C₅₀When the electric charge is
Tick t ₇₄At the power source V_BIs disconnected at time t₇₅To
The power source V_BAre reconnected. At this time,
Time t₇₄From the time t₇₅In the period up to
Transistor TR₅₂, The transistor TR₅₃Is cut off
Therefore, the capacitor C₅₀The discharge amount of
It

Then, at the time t ₇₅ , the transistor TR _{53 is} charged by the charge of the capacitor C _50.
Conducts. At this time, since the collector of the transistor TR ₅₃ is connected to the data line, the transistors TR ₅₁ and TR ₅₂ also become conductive. Therefore, the charging current flows into the capacitor C _50, the capacitor C ₅₀ is recharged. In addition, since the transistor TR ₅₃ becomes conductive as described above, High is applied to the data line.

[0045] Thus, when reconnecting cutting the power supply V _B in a state in which stored information in the capacitor C _50, the capacitor C ₅₀ is recharged, to the data line, has been stored A signal (High) indicating information is output.

[Second Embodiment of the Present Invention] Next, the configuration of the second embodiment of the present invention will be described with reference to the circuit diagram shown in FIG.

The other end of the resistor R ₈₉ , one end of which serves as a data line, is connected to the base of the transistor TR ₈₂ . The emitter of the transistor TR ₈₂ is connected to the power source V _B. The resistor R ₈₈ has one end connected to the base of the transistor TR ₈₂ and the other end connected to the power supply V _B.

The collector of the transistor TR ₈₂ is connected to the high potential side forming the forward direction of the diode D ₉₀ . The low potential side forming the forward direction of the diode D ₉₀ has a resistor R _91.
Connected to one end of. The other end of the resistor R ₉₁ is connected to the other end of a capacitor C ₈₀ whose one end is grounded.

A resistor R _{95 having} one end connected to the power source V _B
The other end of is connected to the base of transistor TR ₈₄ . The resistor R ₉₄ has one end connected to the base of the transistor TR ₈₄ and the other end grounded. One end is the transistor
The other end of the resistor R ₉₃ connected to the collector of TR ₈₄ is connected to the base of the transistor TR ₈₃ .

The emitter of the transistor TR ₈₃ is connected to the line connecting the diode D ₉₀ and the resistor R ₉₁ . One end of the resistor R ₉₂ is the transistor
It is connected to the base of TR ₈₃ and the other end is the transistor TR _83.
Connected to the emitter of. The collector of the transistor TR ₈₃ is connected to one end of the resistor R ₉₇ .

The other end of the resistor R ₉₇ is connected to the base of the transistor TR ₈₅ . The collector of the transistor TR ₈₅ is connected to the data line. The emitter of the transistor TR ₈₅ is grounded. The resistor R ₉₆ has one end connected to the base of the transistor TR ₈₅ and the other end grounded.

The other end of the resistor R ₈₆ , one end of which serves as a reset line, is connected to the base of the transistor TR ₈₁ . The emitter of the transistor TR ₈₁ is grounded. The transistor TR
The base of ₈₁ is also connected to the other end of the resistor R ₈₇ whose one end is grounded. The collector of the transistor TR ₈₁ is connected to the line connecting the diode D ₉₀ and the resistor R ₉₁ .

The transistor TR ₈₁ is an NPN type,
The transistor TR ₈₂ is of PNP type, and the transistor TR is
₈₃ is a PNP type, the transistor TR ₈₄ is an NPN type, and the transistor TR ₈₅ is an NPN type.

Next, based on the time chart shown in FIG.
Next, the operation of the configuration will be described. Now
The capacitor C₈₀When there is no charge on the
Tick t ₇₀Low is applied to the data line at
And the transistor TR₈₂Conducts the transistor
TR₈₂, The diode D₉₀, The resistance R₉₁Through
Power supply V_BFrom the capacitor C₈₀Is supplied with charging current
Be done. And the capacitor C₈₀Is charged.

When a high level is applied to the reset line at time t ₇₁ while the capacitor C ₈₀ is being charged, the transistor TR ₈₁ becomes conductive and the resistor R ₉₁ and the transistor TR are turned on. Through ₈₁ , the charge of the capacitor C ₅₀ is discharged.

Next, the operation in this configuration will be described based on the time chart shown in FIG. 3 (c). Now
In the state that the capacitor C ₈₀ is not charged,
Wherein at time t ₇₂ supply V _B is disconnected, and the power source V _B are reconnected at time t _73. At this time,
If the data line is open, the transistor
TR ₈₂ is cut off, and the transistor TR ₈₃ and the transistor TR ₈₅ are also cut off. Therefore, the capacitor C ₈₀ is not charged.

[0057] Thus, even when reconnecting cutting the power supply V _B when no stored information in the capacitor C _80, rather than that the capacitor C ₈₀ from being charged, the data line Outputs a signal (Open) indicating that there is no stored information.

Next, based on the time chart shown in FIG.
Next, the operation of the configuration will be described. Now
The capacitor C₈₀When the electric charge is
Tick t ₇₄At the power source V_BIs disconnected at time t₇₅To
The power source V_BAre reconnected. At this time,
Time t₇₄From the time t₇₅Up to
Transistor TR₈₁, The transistor TR₈₂, Said tran
Dista TR₈₃Is cut off, the capacitor C₈₀Release of
The amount of electricity can be suppressed to a minute.

Then, at the time t ₇₅ , the transistor T is charged by the charge of the capacitor C _80.
R ₈₃ and the transistor TR ₈₅ become conductive. At this time, since the collector of the transistor TR ₈₅ is connected to the data line, the transistor TR ₈₂ also becomes conductive.

[0060] Therefore, the charging current flows into the capacitor C _80, the capacitor C ₈₀ is recharged. Also,
Since the transistor TR ₈₅ is conductive as described above, a low voltage is applied to the data line.

[0061] Thus, when the disconnecting and re-connecting the power supply V _B in a state where the capacitor C ₈₀ stores information, the capacitor C ₈₀ is recharged, to the data line, has been stored A signal (Low) indicating information is output.

[0062]

As described above, the memory circuit with the backup function of the present invention is configured without using a large component such as a microcomputer, so that it is easier to make the device smaller, lighter and thinner than conventional devices. become.

Further, since large parts are not used as described above, the cost is reduced. Therefore, the present invention can be applied to a vehicle theft prevention device, the device can be provided at a low price, and more vehicles can be protected from theft.

[Brief description of drawings]

FIG. 1 is a block diagram showing the basic principle of the present invention.

FIG. 2 is a block diagram illustrating an outline of a vehicle theft prevention device.

FIG. 3 is a circuit diagram showing the configuration of the first embodiment of the present invention and a time chart explaining the operation of the embodiment.

FIG. 4 is a circuit diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 5 is a block diagram around a memory circuit with a backup function used in a conventional immobilizer ECU.

[Explanation of symbols]

1 Charge control unit 2 Charge detection unit C ₃ Capacitor 12 Security ECU 15 Immobilizer ECU 30 Storage unit

Claims (1)

[Claims] 1. A memory circuit with a backup function for storing information according to the amount of charge stored in the capacitor (C ₃ ) even when power is not supplied, and is applied to the data line during power supply. A charging control unit (1) that supplies a charging current to the capacitor (C ₃ ) according to a signal that is maintained and maintains the connection impedance with the capacitor (C ₃ ) in a high impedance state during the period when power is not supplied. And the capacitor (C
₃ ) the charge control unit (1) feeds back a signal to the data line so that the charging current is supplied when the charge amount is equal to or more than a predetermined amount, and the capacitor is supplied in a period in which power is not supplied. A memory circuit with a backup function, comprising: a charge detection unit (2) for maintaining a connection impedance with (C ₃ ) in a high impedance state.