JPH07264608A - Convergence adjusting circuit - Google Patents

Abstract

PURPOSE:To provide the convergence adjusting circuit which is low in power consumption and highly stable. CONSTITUTION:Representative points of an image from a pattern generating circuit 9 are outputted and displayed, the movement quantities of the respective representative points are inputted with adjustment input keys 7 and stored in a ROM 2, and an address conversion arithmetic processor 1 operates and sends the movement quantities of the respective points of the image to an LUT 4. The LUT 4 inputs the output address of an address counter 6 and outputs a converted address. An RGB primary color video signal, on the other hand, is A/D-converted, temporarily stored in a frame memory 3, and D/A-converted and inputted to a CRT 14, where an image is displayed. At this time, when the signal is stored with the converted address and outputted with the output address of the address counter 6, the video signal is modulated on a time base and converted in position on a screen 15, so that the convergence is adjusted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CRT display convergence adjustment circuit, and more particularly to a low power consumption and high stability convergence adjustment circuit suitable for a projection type CRT display.

[0002]

2. Description of the Related Art Generally, in a projection display,
Since CRT images of three colors of RGB are projected on the screen to compose one image, a color shift occurs due to geometrical distortion due to a difference in the position of each color CRT. In addition, pincushion distortion also occurs due to the aberration of the projection lens.

To solve these problems, a sub-coil (hereinafter referred to as a convergence coil) has been conventionally used in a deflection yoke.
2 is attached, a correction signal is input, horizontal and vertical geometric distortions are corrected, and convergence is adjusted. To further improve the correction accuracy, Japanese Patent Laid-Open No.
As described in Japanese Patent No. 250787, a method of creating a correction signal using digital signal processing has been proposed. The structure is shown in FIG.

The convergence correction circuit shown in FIG.
As components, a CRT 40, a vertical convergence coil 38, a horizontal convergence coil 39, a current amplifier 37, a D / A conversion circuit 36, a RAM 33, a CPU 34,
ROM 35, PLL 30, H address counter 32, V
It comprises an address counter 31.

In the operation of the convergence correction circuit shown in FIG. 2, the CPU 34 reads the convergence data of the representative points in the image stored in the ROM 35, calculates the convergence data of the other parts, and sends them to the RAM 33.
The output of the H and V address counters 32 and 31 reads the convergence data in real time according to the scanning of the image, the D / A conversion circuit 36 performs the D / A conversion, and the current amplifier 37 performs the current amplification. A correction current is input to the horizontal convergence coils 38 and 39 to correct the geometric distortion of the CRT 40.

[0006]

However, the method using the vertical and horizontal convergence coils 38 and 39 as described above has the following problems. One is that as the scale of the display increases, the correction current flowing through the convergence coils 38 and 39 increases, and the power consumption increases. This is particularly remarkable in the projection type, which requires a relatively large amount of correction relative to the direct-view type. The other is the change with time of the performance of the convergence coils 38, 39.
The stability of the convergence over time is poor due to factors such as changes in the performance of the current amplifier 37.

An object of the present invention is to provide a convergence adjusting circuit with low power consumption and high stability, in consideration of the above conventional problems.

[0008]

To achieve the above object, the present invention adjusts the convergence of a CRT display by modulating each pixel of a video signal on the time axis.
Specifically, an A / D conversion unit for RGB primary color video signals and 1
An image storage means for storing more than one field, a D / A conversion means, an address generation means for generating an address value of the image storage means, a signal generation means for displaying a representative point of the image, and a movement amount of the representative point of the image. Position input means for setting
Position storage means for storing the movement amount of the representative point, coordinate conversion calculation means for calculating the movement amount of each image point from the movement amount of the representative point, and the address value according to the movement amount of each image point A convergence adjusting circuit is configured by the coordinate converting means for converting.

The signal generating means can change the position of the representative point by inputting position information from the outside. The coordinate conversion means is a high speed table conversion circuit using a RAM.

[0010]

In the above structure, the representative points of the image are output from the signal generating means and displayed, the movement amount of each representative point is sequentially inputted by the position input means and stored in the position storing means, and the image is calculated by the coordinate conversion calculating means. The amount of movement of each point is calculated and sent to the coordinate conversion means. The output address of the address generating means is input to the coordinate converting means and the converted address is output. On the other hand, RGB
The primary color video signal is A / D converted by the A / D conversion means, temporarily stored in the image storage means, D / A converted by the D / A conversion means and input to the CRT to display an image. When the image signal is stored in the conversion address when it is stored in the storage means, and when it is output from the image storage means by the output address of the address generation means, the video signal is coordinate-converted and output. If the coordinate conversion means is a high-speed table conversion circuit using RAM, real-time coordinate conversion processing becomes possible.

[0011]

An embodiment of the present invention will be described with reference to the drawings.
FIG. 1 shows the configuration of a convergence adjusting circuit according to an embodiment of the present invention. As shown in FIG. 1, the convergence adjustment circuit includes an address conversion processor 1, a ROM 2, a frame memory 3, an LUT (lookup table) 4, a multiplexer 5, an address counter 6, an adjustment input key 7, and a PL.
L circuit 8, pattern generation circuit 9, A / D conversion circuit 10,
The multiplexer 11, the D / A conversion circuit 12, the video amplifier 13, the CRT 14, and the like are configured.

Next, the operation of the embodiment will be described. The circuit of the embodiment is roughly divided into two parts. One is RGB
The primary color video signal processing part and the other part are video signal coordinate conversion processing parts. First, the former will be described.
RGB primary color video signals (R.IN, G.IN, B.IN)
Is A / D converted by the A / D conversion circuit 10, once written in the frame memory 3 through the multiplexer 11, and then read out, D / A converted by the D / A conversion circuit 12, and amplified by the video amplifier 13. After that, it is input to the CRT 14 and becomes an RGB three-color image, which is projected on the screen 15 by the projection lens 16. The projected image was initially
Pincushion distortion due to the aberration of the projection lens 16 (see FIG.
a) and the geometric distortion due to the difference in the positions of the RGB CRTs 14.

Next, a portion for performing the coordinate conversion processing of the video signal will be described. This portion outputs the read address 17 of the frame memory 3 and outputs the write address 18 of the frame memory 3 for the purpose of coordinate conversion of the video signal. A detailed description of each part will be given below. The horizontal synchronizing signal (HD) is input to the PLL circuit 8 and the divided clock (CK) of the horizontal synchronizing signal is output. Divided clock,
The horizontal synchronizing signal and the vertical synchronizing signal (VD) are input to the address counter 6, and the address signal synchronized with the timing of the video signal is output. The address signal is input to the LUT 4 via the frame memory 3 and the multiplexer 5. The former is used as a read address of the frame memory 3, and the latter is input to the frame memory 3 after being converted by the conversion table of the LUT 4 and used as a write address. The LUT 4 uses a RAM for high-speed access in order to output the write address in real time. The address conversion processor 1 has a function of performing coordinate conversion calculation of a video signal and sending a coordinate conversion table to the LUT 4, and a function of controlling the entire coordinate conversion process. From the adjustment input key 7, the designation data of the adjustment location and the image movement amount data at the time of adjustment are input to the address conversion processor 1 and stored in the ROM 2. The pattern generation circuit 9 receives the divided clock, the horizontal synchronizing signal, and the vertical synchronizing signal, and outputs the dot pattern video data for adjustment. The position of the dot pattern can be freely set by the address bus of the address conversion processor 1.

Next, a procedure for actually performing convergence adjustment using the above circuit will be described. First adjust G
From the image, the R and B images are sequentially adjusted. First, control signal 1 from address translation processor 1
9 to the multiplexer 11 to output the pattern generation circuit 9
The G dot pattern output by the above is displayed on the screen 15. The G projection image initially has distortion as shown in FIG. 3a. Next, the dot to be adjusted is selected by the adjustment input key 7. The selected position data is sent from the address conversion processor 1 to the pattern generation circuit 9 and displayed on the screen with a cursor or the like. Next, the movement amount data for the convergence correction of the selected dot is input by the adjustment input key 7.
The address conversion processor 1 changes the value of the address bus 20 sent to the pattern generation circuit 9 according to the input movement amount data, and changes the position of the selected dot. When the movement amount data is determined in this way, the initial value and the changed value of the address bus 20 at that time are stored in the ROM 2. The same operation is performed for each of the other dots.

Next, a calculation process for obtaining the address shift amount of another portion from the address shift amount of each dot obtained by the above method will be described with reference to FIG. (X1, y2), (x2, y2), (x1, y1) on the address coordinates,
Each point of (x2, y1) is (Δx1, Δy1), (Δx2, Δy
2) When moving addresses by (Δx3, Δy3), (Δx4, Δy4), the moving amount of any point (x, y) inside the rectangle surrounded by 4 points is calculated by using the linear approximation. It is represented by 2.

[0016]

[Equation 1]

[0017]

[Equation 2] The above calculation is performed for each point on the screen to obtain the address movement amount. By the above calculation, the conversion address for the current address of each point of the image is obtained. Further, the address conversion processor 1 outputs to the LUT 4 the current address via the multiplexer 5 and the converted address via the data bus to store the coordinate conversion table.
The geometric distortion of the G image is eliminated (Fig. 3b).

Convergence adjustment is completed by performing similar processing for R and B images.

[0019]

As is apparent from the description of the embodiments, the following effects can be achieved by the present invention. (1) The geometric distortion can be eliminated and the convergence can be adjusted with a smaller electric power than the method using the sub-yoke of the deflection yoke. (2) Since the sub-yoke of the deflection yoke and the current amplifier in the preceding stage are not used, changes in the performance of the sub-yoke with time,
The adjustment result is stabilized without being affected by the performance change of the current amplifier.

[Brief description of drawings]

FIG. 1 is a block diagram of a convergence adjustment circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional convergence correction circuit.

FIG. 3 is a conceptual diagram of video signal coordinate conversion of the present invention.

FIG. 4 is an explanatory diagram of coordinate conversion calculation.

[Explanation of symbols]

 1 Address Conversion Processor 2 ROM 3 Frame Memory 4 LUT (Look Up Table) 6 Address Counter 7 Adjustment Input Key 8 PLL Circuit 9 Pattern Generation Circuit 10 A / D Conversion Circuit 12 D / A Conversion Circuit 13 Video Amplifier 14 CRT

Claims (4)

[Claims] 1. An A / D conversion means for RGB primary color video signals, an image storage means for storing one or more fields, and a D / A.
Conversion means, address generation means for generating an address value of the image storage means, signal generation means for displaying a representative point of the image, position input means for setting the movement amount of the representative point of the image, and the representative point Position storage means for storing the movement amount, coordinate conversion calculation means for calculating the movement amount of each image point from the movement amount of the representative point, and coordinate conversion means for converting the address value according to the movement amount of each image point. And a convergence adjustment circuit for performing convergence adjustment of a CRT display by modulating each pixel of a video signal on a time axis. 2. The convergence adjusting circuit according to claim 1, wherein the signal generating means can change the position of the representative point by inputting position information from the outside. 3. The convergence adjusting circuit according to claim 1, wherein the coordinate converting means is a high speed table converting circuit using a RAM. 4. The convergence adjustment circuit according to claim 1, wherein the CRT display is a projection type display which projects an RGB image to obtain an image by combining three colors.