JPH07263505A - Circuit operation mode detecting apparatus - Google Patents

Abstract

PURPOSE:To obtain more information with a smaller space by selecting a circuit operation mode from a plurality of the circuit operation modes and by detecting a circuit operation out of a plurality of circuit operation modes from the number of pads smaller than the number of circuit modes based on the results of selection. CONSTITUTION:One circuit operation mode is selected out of a plurality of operation mode switching pads A, B and C. At this time, pads A, B and C are held to an ordinary grounding potential by transistors TA1 to TA3, and the gates of transistors TA4 to TA10 are set to VSS. In this state, a circuit operation selected out of a plurality of circuit operation modes can be detected based on the selection results from a current flowing to a pad P because a potential higher than the ordinary operation voltage is applied to the detecting pad P.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit operation mode detecting device having a bonding pad or a fuse having a function of switching a plurality of circuit operation modes.

[0002]

2. Description of the Related Art A current semiconductor integrated circuit (hereinafter, also referred to as an IC) is capable of producing a plurality of products with one chip by using an operation switching circuit or the like. This means that a wide variety of products are mixed on one wafer, and as a means for selecting them, there is a bonding pad or fuse for switching a plurality of circuit operation modes.

In this way, when the means for selecting the circuit operation mode are independent of each other, there is a possibility that the product will not be the actual intended product due to a bonding error. There is also.

FIG. 22 shows the configuration of a conventional operation switching and detection circuit using a bonding pad.

In this circuit, the pads Pi (i = 1 to 6; P
1, P2 and P3 are bonding pads for switching the circuit operation mode. P4, P5 and P6 are pads connected to external pins of the package), P-channel transistor T
1, T2, T3, N-channel transistor Ti (i = 4
˜15; T4 to T6 are provided with high resistance transistors) and an inverter Ii (i = 1 to 6).

In such a circuit, when a lead frame having a power supply potential VCC is bonded to the pad P1,
Since the transistor T4 has a high resistance, N1 is the power supply potential V
Lifted to CC. In addition, the current flowing from the node N1 to the ground potential VSS is also very small. This node N
The potential of 1 is transmitted to the node N2 via the inverters I1 and I2 (the potential of N2 is VCC), and this circuit operation mode is selected (in this case, operation mode 1).

At this time, VC is applied to the gate of the transistor T1.
When C is applied and a voltage higher than the normal operating voltage is applied to the pad P4, VCC + | Vthp1 | (Vthp1 is T
T1 starts to turn on at the threshold voltage of 1), and VCC + V
At th7 + Vth8 + Vth9 (Vth7, Vth8, and Vth9 are threshold voltages of T7, T8, and T9, respectively), current starts flowing from P4 to VCC. Where VCC + | Vthp
1 | <(VCC + Vth7 + Vth8 + Vth9). Thereby, the current flowing through the pad P can be monitored.

On the other hand, if the pad P1 is not bonded, 0V is applied to the gate of the transistor T1 while P1 remains at the ground potential VSS. When P4 becomes a potential higher than | Vthp1 |, T1 turns on, but no current flows from P4 to VCC due to T7 to T9 in the normal operating voltage range. The potential of P4 is (VCC + Vth7 + Vth8 + Vth
9) above, current begins to flow from P4 to VCC. Here, the gate level of T1 changes depending on the presence / absence of bonding of P1, and P4 becomes (VCC + Vth7 + Vth8 + V
When th9) or more is applied, the current value changes due to the difference in the ON resistance of T1, and the current value is different, and it is possible to determine whether P1 is bonded or not. The same applies to P2, P5 and P3, P6.

Further, in the circuit shown in FIG. 22, a similar circuit can be formed by the fuse by replacing the bonding pad for switching the circuit operation with the fuse.

[0010]

As described above,
In the conventional circuit shown in FIG. 22, one current detection circuit is required for one operation switching circuit. Therefore, when the circuit operation modes are diverse, the current detection circuits for the minimum number of modes are required, and if a current detection circuit is provided for each pin, it is necessary to route the wiring and the like into the chip, which hinders the reduction of the chip size. It was.

Although it is possible to check the bonding for the same type of chips, it cannot be checked whether the bonding corresponding to each of the plurality of types of chips is correct. In other words, a plurality of types of information is given to the chips on the wafer (using fuses or the like), and after dicing, it is impossible to check whether each chip is correctly bonded based on the information.

Therefore, the present invention has been made in view of the above, and an object thereof is to detect a plurality of information such as a circuit operation mode by one pad and obtain a large amount of information in a small space. Another object of the present invention is to provide a circuit operation mode detecting device capable of performing the above.

Another object of the present invention is to provide a circuit operation mode detecting device capable of preventing the erroneous recognition of the product type by checking the coincidence between the information on the wafer and the information after assembly by bonding. It is in.

[0014]

In order to achieve the above object, the invention according to claim 1 detects a circuit operation mode selected from a plurality of circuit operation modes in accordance with a value of a current flowing through a pad. The number of detection pads less than the number of circuit operation modes, the plurality of operation mode switching pads provided corresponding to the set circuit operation modes, and the potentials of the corresponding operation mode switching pads A plurality of conduction control circuits that output a conduction control signal according to the bonding state of the switching pad, and a common connection to the detection pad, and conduction control is performed according to the conduction control signals of the corresponding conduction control circuits, and different conduction currents respectively. Are provided to the detection pad.

According to a second aspect of the present invention, in the circuit operation mode detection device according to the first aspect, a plurality of detection units each including the conduction control circuit according to the first aspect, the operation mode switching pad, and the current supply circuit, and a detection unit are provided. It is composed of a connection control circuit for switching and controlling the pad for detection and the respective detection units, and a control pad for giving a switching control signal to the connection control circuit.

According to a third aspect of the present invention, the number of detection pads is smaller than the number of circuit operation modes for detecting a circuit operation mode selected from a plurality of circuit operation modes according to the value of current flowing through the pad. A plurality of operation mode switching pads provided respectively corresponding to the circuit operation mode,
A selection circuit that receives the potentials of the corresponding operation mode switching pads and selectively selects an operation mode from a plurality of operation modes according to the bonding state of the operation mode switching pads and a preset priority. , A conduction control circuit that outputs a conduction control signal according to the selected operation mode in response to the operation mode selected by the selection circuit, and a current value that flows through each detection pad according to the conduction control signal of the conduction control circuit And a current supply circuit for determining and controlling.

According to a fourth aspect of the present invention, the number of detection pads is smaller than the number of circuit operation modes for detecting a circuit operation mode selected from a plurality of circuit operation modes according to the value of the current flowing through the pad. A plurality of operation mode switching pads provided respectively corresponding to the circuit operation mode,
A plurality of conduction control circuits that receive the potentials of the corresponding operation mode switching pads and output a conduction control signal according to the bonding state of the operation mode switching pads, and the detection pads are connected in common and are connected to each other. A plurality of current supply circuits, each of which is supplied with a specific potential via the conduction control circuit, supplies a conduction current to the detection pad based on the value of the conduction control signal of the corresponding conduction control circuit.

According to a fifth aspect of the invention, the number of detection pads is smaller than the number of circuit operation modes for detecting a circuit operation mode selected from a plurality of circuit operation modes according to the value of the current flowing through the pad. A plurality of operation mode switching fuses respectively provided corresponding to the circuit operation modes, and a plurality of conduction control circuits that output a conduction control signal according to the connection / disconnection state in the corresponding operation mode switching fuses, A plurality of current supply circuits that are commonly connected to the detection pad and are supplied with a specific potential via the detection pad to give a conduction current to the detection pad based on the value of the conduction control signal of the corresponding conduction control circuit. Composed of and.

According to a sixth aspect of the present invention, in the circuit operation mode detecting device according to the fourth aspect, the plurality of operation mode switching fuses and the conduction control circuit according to the fifth aspect are provided.

According to a seventh aspect of the present invention, there are provided a plurality of detection pads for detecting a circuit operation mode selected from a plurality of circuit operation modes according to a current value flowing through the pad, and a set circuit operation mode. A plurality of operation mode switching fuses that are connected or disconnected before chip packaging, and a plurality of conduction control signals that are output according to the connection / disconnection states of the corresponding operation mode switching fuses. It is composed of a conduction control circuit and a plurality of current supply circuits that apply a conduction current to the detection pad according to the conduction control signals of the corresponding conduction control circuits.

[0021]

In the above structure, according to the present invention, at least one circuit operation mode is selected from the plurality of circuit operation modes, and which circuit operation is selected from the plurality of circuit operation modes based on the selection result. Is detected with a smaller number of pads than the number of circuit modes.

At least one circuit operation mode is selected from a plurality of circuit operation modes before packaging the chip, and at least one circuit operation mode is selected from a plurality of circuit operation modes during the packaging of the chip. After chip packaging, it is detected whether or not the selected mode is correct.

[0023]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing the configuration of a circuit operation mode detecting device according to an embodiment of the invention described in claim 1. In FIG.

In this embodiment, the circuit operation mode detecting pads P4 to P6 are combined into one in the conventional structure shown in FIG.

In FIG. 1, this detection device includes a number of operation detection pads P less than the number of circuit operation modes, bonding pads A, B, and C for switching IC operations, inverters IA1 to IA6 serving as a conduction control circuit, and a high level. N channel transistors TA1 to TA3 of resistors and N serving as a current supply circuit
It includes a channel transistor TA0 and P-channel transistors TA4 to TA10.

In each of the following embodiments of the invention, the number of operation detecting pads is set to be smaller than the number of circuit operation modes.

Pads A, B and C are connected to nodes NA1 to NA3.
Connected to inverters IA1, IA3, IA5, and the outputs thereof are inverters IA2, IA4, IA6.
Connected to. The outputs of the inverters IA2, IA4, IA6 are connected to the gates of the P-channel transistors TA4 to TA10. The sources of the transistors TA4 to TA10 are nodes NA0 and the drains thereof are nodes NA8 to NA1.
0, and the back gates are transistors TA4 to TA1.
Connected to 0 source. Transistors TA4 to T
The drain of A10 is connected to the transistor TA0 via the nodes NA8 to NA10, and the power supply potential VCC is applied to the final stage.

High resistance N channel transistors TA1 to T
A3 has a drain connected to the nodes NA1 to NA3, a source connected to the ground potential VSS, and a gate applied with the power supply potential VCC. Therefore, the pads A, B, and C are normally held at the ground potential by the transistors TA1 to TA3, and the gates of the transistors TA4 to TA10 are at VSS.

In such a structure, the detection pad P
By applying a potential higher than the normal operating voltage to the pad, the current flowing through the pad P can be detected.

A constant potential VP (VP> VCC + Vthn; Vthn is TA higher than the normal operating voltage is applied to the pad P of FIG.
n threshold voltage) is applied. If the pads A, B, and C are not bonded to VCC, TA
The ground potential VSS is applied to all the gates of 4 to TA10, and currents IA1, IA2, IA3 flow.

Here, the P-channel transistors TA4.about.
If the threshold voltage of TA10, the channel width Wp, and the channel length Lp are all the same and IA1 = IT, then I
A2 = 21T, IA3 = 41T, and pads P to V
The current IP flowing through CC is IP = 7IT.

Next, consider the case where only the pad A is VCC-bonded.

When the pad A is VCC-bonded, since the transistor TA1 has a high resistance, the node NA is
1 is raised to VCC and inverters IA1, IA2
The gate of the transistor TA4 is set to VCC via.
As a result, even if the potential VP is applied to the pad P, the current IA1
Flows slightly, and IP = IA2 + IA3 = 6IT.

In this way, the operation switching pads A,
FIG. 2 shows the relationship between the bonding state of B and C and the current IP. As shown in FIG. 2, the current IP changes stepwise according to the bonding state. By measuring the current value by utilizing this, the state of the bonding pad can be known and the operation mode can be detected.

FIG. 3 is a diagram showing a configuration of a circuit operation mode detecting device according to an embodiment of the invention described in claim 2.

The circuit of the embodiment shown in FIG. 3 is a circuit in which a control pad is prepared in addition to the detection pad, and the detection circuit is switched by the pad to detect a circuit operation mode twice as high as that in the above embodiment. .

This detection circuit includes a number of operation detection pads P smaller than the number of circuit operation modes, operation switching bonding pads A to F, a control pad α, P channel transistors TC1 and TC2, inverters IC2 and IC3. And the unit X used in the above embodiment and the AD conversion circuit IC1
It has and.

As the pad α, a pad used in normal operation is used. The pad α is connected to the gate of TC1 via the AD conversion circuit IC1 and the inverter IC2. Also, I
The output of C2 is connected to the inverter through IC3 and to the gate of TC2. Sources of TC1 and TC2 are node NC
The pad P and the drain are connected to the unit X via 0 respectively.
It is connected to (1) and (2). Operation switching pad A
-C and DF are connected to the units X (1) and (2), respectively.

In such a structure, the pad P has a constant potential VP (VP> VCC + V) higher than the normal operating voltage.
thn; Vthn is a threshold voltage of TAn). Here, when the pad α is applied with the VCC potential,
The gate potential of TC1 is VCC and the gate potential of TC2 is V
It becomes SS and unit X from pad P through TC2
A current flows to the (2) side. As a result, the pads P, D, E, and F of the unit X (2) are formed in the same manner as in the above embodiment.
The state of can be detected.

When a VSS potential is applied to the pad α,
The gate potential of TC1 is VSS and the gate potential of TC2 is V
CC, unit X from pad P through TC1
A current flows to the (1) side. As a result, the state of the pads A, B, C of the unit X (2) can be detected by the pad P.
The relationship between the state of these pads and the current IP is shown in FIG.
As shown in.

FIG. 5 is a diagram showing a configuration of a circuit operation mode detecting device according to an embodiment of the invention described in claim 3.

In the embodiment shown in FIG. 5, priority is given to four operation modes to prohibit selection of a plurality of operation modes, and the operation is performed by detecting a current with two operation detection pads smaller than the number of circuit operation modes. It detects the mode.

This detection circuit assigns an operation mode priority to a circuit C1 which serves as a selection circuit, and a circuit C2 which serves as a conduction control circuit by converting its output so that it can be detected by two pads.
A circuit C3 which detects it and becomes a current supply circuit, detection pads PX and PY, and operation switching pads B, C and D
And high-resistance N-channel transistors TE6 to TE9.

The circuit C1 for prioritizing the operation modes is
Inverters IE3 to IE7 and NOR gate NOR
3 to NOR5. The operation mode A of the circuit C1 is selected in the initial state.

Here, when VCC bonding is performed on the pad B, since NE5 is at the LOW level, IE3, IE
NE1 becomes LOW level through 7, and operation mode D
Is deselected. Similarly, since NE2 is at the LOW level, the output of NOR3 is at the LOW level and the operation mode C is in the non-selected state. Since the output of NOR3 and the output of NOR3 and all of NE1 and NE4 are LOW level, the output of NOR4 becomes HIGH level, and the operation mode B becomes the selected state. It is understood that the output of NOR5 receives the output of NOR4 and becomes LOW level, the operation mode A is not selected, and only the operation mode B is selected.

Next, when VCC bonding is performed on the pad C, NE1 becomes LOW level, so that the operation mode D becomes non-selected. Similarly, since NE2 is at the LOW level, the output of NOR3 is at the HIGH level and the operation mode C is in the selected state. NOR by receiving the output of NOR3
4, the output of NOR5 becomes LOW level, the operation modes B and A are in the non-selected state, and it is understood that only the operation mode C is selected. Similarly, when the pad D is VCC-bonded, the operation modes A, B, and C are in the non-selected state, and only the operation mode D is in the selected state.

That is, all the operation modes having a lower priority in the order of the operation modes A, B, C, D and lower than the selected operation mode are unselected. This prevents a plurality of operation modes from being selected.

The output of the circuit C1 is input to the circuit C2 and converted as shown by X and Y in FIG. 6 to control the transistors TE2 and TE4 of the circuit C3. Here, the pads PX,
VCC + | Vthp | <VP <VCC + 2 | Vthp for PY
By applying the potential VP of |, Vthn <| Vthp |, the currents IX and IY flow to VCC, and by detecting this, IX and IY as shown in FIG. 6 (where IX = I
The operation mode can be detected by the difference (Y = Ic).

FIG. 7 is a diagram showing a configuration of a circuit operation mode detecting device according to an embodiment of the invention described in claim 4.

In this embodiment, by utilizing the difference in the voltage at which a current starts to flow from the pad to VCC by changing the potential applied to the detection pad, any one of a plurality of operation modes can be selected even after packaging. The squid is electrically detected with one pin.

The detection circuit shown in FIG. 7 has a number of operation detection pads P30 smaller than the number of circuit operation modes, IC operation switching bonding pads P3i (i = 1 to 3), and inverters I3ia and I3ib (i = 1). 3) and N-channel transistors TN131b, TN31c, TN31
d, TN32b, TN32c, TN33b, P-channel transistor TP3i (i = 1 to 3), and high resistance N
It includes a channel transistor TN3ia (i = 1 to 3).

The pad P3i is a node 3ia (i = 1 to 1).
3) via an inverter I3ia, the output of which is connected to the inverter I3ib. The output of the inverter I3ib is connected to the gate of the P-channel transistor TP3i. The source of the transistor TP3i is the node N30a, and the drain is the node N3ic (i =
1 to 3), and transistors TN31b, TN31c, TN31d via a node N3ic,
It is connected to TN32b, TN32c and TN33b, and power supply potential VCC is applied to the final stage of each.

Here, the transistors TN31b and TN3
1c, TN31d, TN32b, TN32c, TN33
All of the transistors b have the same characteristics. The high resistance N-channel transistor T3ia (i = 1 to 3) has a drain connected to the node N3ia and a source connected to the ground potential V.
It is connected to SS and the power supply potential VCC is applied to its gate. Therefore, the transistor P3i is connected to the pad P3i.
It is normally held at the ground potential by a, and the gate of the transistor TP3i is VSS. Therefore, the current flowing through the pad P30 can be detected by applying a higher potential to the detection pad P30 with a normal operating voltage.

In addition, a CMOS device is usually an Nwell
The ground voltage VSS is applied to the power supply potentials VCC and Pwell, thereby reverse biasing the source and drain of the transistor to prevent leakage current. In the conventional case, the power supply potential VCC + VtPN (V
tPN is P between the source of the transistor T1 and Nwell
When a potential equal to or higher than the potential difference at which the forward current starts to flow to the N-junction) is applied, the current indicated by a in FIG. 8 is generated and malfunction occurs.

In the circuit shown in FIG. 7, by connecting the back gate and the source of the P-channel transistor TP3i as shown in FIG. 9, the source of the TP31 and the Nw are connected.
There is no potential difference between the cells, the PN junction does not turn on, the current indicated by a does not occur, and malfunctions can be prevented.

In the embodiment shown in FIG. 7, first, consider a state in which the pads P31, P32 and P33 are not bonded.

The potentials of the nodes N31a, N32a, N33a are the ground potential VSS, respectively, and the inverter I31
a, I31b, I32a, I32b, I33a, I33
The gate potentials of TP31, TP32, and TP33 are set to the ground potential VSS through b. When a voltage higher than the normal operating voltage is applied to the pad P30, the VP30 becomes VC
When the voltage exceeds C + Vthn33b (Vthn33b is the threshold voltage of TN33b) or more, the current I33 flows to VCC through TP33 and TN33b. At this time, TN32
b, TN32c, TN31b, TN31c, TN31d
Is in the off state, the current flowing from the pad P30 to VCC is I30 = I33.

Next, VP30 is set to (VCC + Vthn32b
+ Vthn32c) or more (Vthn32b, Vthn32c are threshold voltages of TN32b, TN32c), T
A current I32 flows to VCC through P32, TP32b, and TN32c. At this time, TN31b, TN31c, T
Although N31d is still in the off state, the current I33 that has started to flow earlier causes VP30 to be (VCC + Vthn32b + Vth32
Since the current I33 is flowing even when the value is set to c) or more, the current I30 flowing from the bad P30 to VCC is I30 = I3.
It becomes 3 + I32.

Further, VP30 = (VCC + Vthn31
b + Vthn31d) (Vthn31b to d are TN31b to
(threshold voltage of d) or more, TP31, TN31
Current I3 to VCC through b, TN31c, TN31d
1 flows. At this time, since I33 and I32 continue to flow, the current I30 flowing from the pad P30 to VCC is the sum of all of them, and I30 = (I33 + I32 + I3
It becomes 1).

Next, consider a case where the pads P31 and P32 are not bonded and only the pad P33 is bonded to the power supply potential VCC.

In such a case, the pad P33 is set to VCC.
When bonded to, TN33a has a high resistance, so N3
3a is raised to VCC, and inverters I33a, I3a
The gate potential of TP33 is set to VCC via 33b.
Here, when the potential VP30 higher than the normal operating voltage is applied to the pad P30 in the same manner as described above, when VP30 becomes (VCC + Vthn33b) or more (here | Vth
p33 | <Vthn33b), TP33, TN33
A current I33 flows to VCC through b.

Here, assuming that the gate-source voltage of TP33 is VG33, the potential of the node N33b is VSS when the pad P33 is not bonded to VCC, that is, when the operation mode 1 is in the non-selected state.
With reference to the potential VP30 of the pad P30, VG33
= (VP30-VSS). When the pad P33 is bonded to VCC, that is, the operation mode 1
When is selected, the potential of N33b is VCC,
With reference to the potential VP30 of the pad P30, VG33 =
(VP30-VCC).

Considering the drain current ID33 of the TP33 with respect to each VG33, the result is as shown in FIG. 10. Paying attention to the single transistor of the TP33, VG33 =
(VP30-VSS), that is, when VCC is not bonded, that is, when the drain current ID33 when the operation mode 1 is in the non-selected state is bonded to VCC, that is, when the operation mode 1 is selected It can be seen that the drain current is larger than the drain current ID33.

Therefore, depending on whether or not the VCC bonding has been performed on the pad P33, the pad P30 is connected to VCC +.
Vthn33b ≦ VP30 ≦ (VCC + Vthn32b + V
current value I33 when a potential VP30 of thn32c) is applied
Will be different. At this time, pad P30 and VC
When the current I30 between C is detected, the currents I32 and I31 do not flow as in the case described above, so that I30 = I33. Therefore, VC of pad P33 is
The presence or absence of C bonding can be detected.

Here, for simplicity, N-channel transistors TN31b, TN31c, TN31d, TN32 are used.
b, TN32c and TN33b all have the same Vth
Think as FIG. 11 shows the potential V applied to the pad P30.
T when P30 is selected or not selected
Currents I31, I3 flowing through P31, TP32, TP33
2, I33 and current I flowing between pad P30 and VCC
It is a figure showing the characteristic of 30.

The operation modes 1, 2, and 3 are shown in FIGS.
3, as shown in FIGS. 14 and 15, the current I30 (thick solid line) flowing through the pad P30 in the non-selected operation mode and the pad P3 when the operation mode is selected, respectively.
The circuit operation mode can be detected by comparing with the current I30 flowing through 0 (solid line).

When a plurality of operation modes are selected, the same idea can be applied. In the case of three kinds of operation modes, the current comparison values at the time of selecting each of the seven modes are prepared in advance and The operation mode can be checked by comparing the comparison value with the detected current.

Here, V1, V2, and V3 are selected as the measurement potentials in the operation modes 1, 2, and 3. At that time, as a comparison value of the current when the mode is selected, as shown in FIG.
~ Ith7 is preset.

Assuming that the operation modes 1 and 3 are selected, the operation mode 3 detection area (VCC
When the potential V3 of + Vth ≦ VP30 ≦ VCC + 2Vth) is applied to the pad P30, the detected current becomes smaller than Ith1 and it is understood that the operation mode 3 is selected.

Next, the operation mode 2 detection area (VCC + 2
When the potential V2 of (Vth ≦ VP30 ≦ VCC + 3Vth) is applied to the pad P30, the detected current becomes larger than Ith2, and it can be seen that the operation mode 2 is unselected.
Here, since it is known that the operation mode 3 has already been selected, Ith3 can be ignored.

Finally, the operation mode 1 detection area (VCC +
When the potential V1 of 3 Vth ≦ VP30) is applied to the pad P30, the detected current becomes smaller than Ith5, and it is understood that the operation mode 1 is selected. Similarly to the above, since it is known that the operation mode 2 has been deselected, Ith4, Ith6, and Ith7 can be ignored.

In this way, a plurality of operation modes can be detected. Further, even when a plurality of other operation modes are selected, the same method can be used for detection.

Further, as shown in FIG. 17, it is possible to obtain the operation mode detection region by changing the threshold voltage of the N-channel transistor, and Vth61N = 3Vth, Vth6.
By setting 2N = 2Vth and Vth 63N = Vth, it is possible to have the same operation mode detection area as the circuit shown in FIG.
Furthermore, it is also possible to change the threshold value of the P-channel transistor so that the detection current has a width.

As described above, by utilizing the difference in the voltage at which the current starts to flow from the pad P30 to VCC by changing the potential applied to the detection pad P30, which of the plurality of operation modes is selected even after the package is encapsulated. Or
It becomes possible to detect electrically with one pin.

In the circuit shown in FIG. 7, by replacing the pad with a fuse as shown in FIG. 18 as an embodiment of the invention described in claim 5, a similar circuit can be assembled with the fuse. Further, as an embodiment of the invention described in claim 6, it is possible to mix fuses and pads as shown in FIG.

FIG. 20 is a diagram showing the structure of a circuit operation mode detecting device according to an embodiment of the invention described in claim 7.

In this embodiment, the coincidence between the information given on the wafer and the information given by bonding is detected.

The detection circuit shown in FIG. 20 has bonding pads P91, P92, P93, fuses F91, F9.
2, N-channel transistor TN9i (i = 1 to 6; T
N91 and TN92 are high resistance transistors, TN93 and T
N96, TN94, TN95 threshold Vth), P-channel transistor TP9i (i = 1 to 4, threshold Vth)
p) and an inverter I9i (i = 1 to 8).

Here, the P-channel transistor TP91
-TP94 all have the same characteristics, and all N-channel transistors TN93-TN95 have the same characteristics.

Since the potential applied to the detection pad is VP9 = constant, the current flowing through the detection pad depends only on the voltage applied to the gate of the P-channel transistor, that is, whether or not the fuse is blown. Therefore, the relationship of I91a = I92b = I93a = I93b = Ic is established.

Now, consider that the fuses F91 and F92 are not cut. Here, the pads 91, P92,
When a voltage VP9 higher than the normal operation voltage is applied to each of P93, when the voltage VP9 is Vth + VCC or more, the current I9 is increased.
1a and I93a start flowing, and pads P91 and P92,
The current flowing from P93 to VCC is I91 = Ic, I9
2 = Ic and I93 = 2Ic.

Next, consider the case where only the phase F91 is disconnected. Since phase F91 was disconnected, TP9
1, the gate potential of TP94 becomes VCC, I91a,
I93a has a considerably smaller value than Ic. Therefore, the current flowing from P91 to VCC can be almost ignored, and P92 and P93 have almost the same current value. Here, the blow of the fuse can be detected by adjusting the channel width of the P-channel transistor or the like to give a difference in current value.

Here, the pad P91 is a fuse F.
The pad P92 used in the mode selected by cutting 91 is the pad P9 used in the mode selected by cutting the fuse F92.
3 can be thought of as a pad used in both modes.

For example, an IC having two operation modes A and B
Consider the case where this embodiment is applied to. Figure 21
(A) And (b) is a figure which shows some chip | tip bonded to the lead frame, respectively.

As shown in FIG. 21A, assume that the A mode is selected and only the A pad is bonded to the lead frame. At this time, the fuse P in the circuit shown in FIG.
By turning off 91, the detection circuits connected to the pads used in the selected mode are connected to all the pads. When the fuse F91 is cut and the A mode is selected, the same current value can be detected from all the pads used in the A mode.

Therefore, as shown in FIG.
When only one pad is erroneously bonded, a current value different from that of the other pins is detected from the bonded pin, and a bonding error can be easily found.

[0088]

As described above, according to the first aspect of the present invention, the number of detection pads is set to be smaller than the number of circuit operation modes for a plurality of circuit operation modes and the detection pads are also used. It is detected by one pad whether two or more operating modes are selected at the same time, and more information can be obtained with less space.

According to the second aspect of the invention, since the control pad is provided in addition to the detection pad to switch the detection unit, many circuit operation modes can be detected with less pads. .

According to the third aspect of the present invention, the priority order is set for the circuit operation modes. Therefore, it is possible to prevent a plurality of circuit operation modes from being selected from a plurality of circuit operation modes. it can.

According to the invention described in claim 4, since the operation mode is detected by changing the potential applied to the detection pad, the operation mode selected by the minimum number of detection pads even after the package is enclosed. Can be detected.

According to the seventh aspect of the invention, since the coincidence between the information given on the wafer and the information given by bonding is detected, the independent detection of the circuit operation modes is combined into one. Thus, it is possible to check whether the information on the wafer matches the information after assembly by bonding or the like, and it is possible to prevent malfunction of the operation mode of the internal circuit in the product after packaging.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a circuit operation mode detection device according to an embodiment of the invention described in claim 1.

FIG. 2 is a diagram showing a relationship between currents between pads P and VCC in the device shown in FIG.

FIG. 3 is a diagram showing a configuration of a circuit operation mode detection device according to an embodiment of the invention as set forth in claim 2;

4 is a diagram showing a relationship between currents between pads P and VCC in the device shown in FIG.

FIG. 5 is a diagram showing a configuration of a circuit operation mode detection device according to an embodiment of the present invention.

6 is a diagram showing a difference in detected current depending on an operation mode in the device shown in FIG.

FIG. 7 is a diagram showing a configuration of a circuit operation mode detection device according to an embodiment of the invention as set forth in claim 4;

FIG. 8 is a diagram showing an example of a cross-sectional structure in a conventional detection device.

9 is a diagram showing an example of a cross-sectional structure of the apparatus shown in FIG.

10 is a diagram showing a relationship between a gate potential and a drain current of a transistor in the device shown in FIG.

11 is a diagram showing characteristics of a detected current and an applied voltage in the device shown in FIG.

12 is a diagram showing a relationship between a pad-VCC current in the device shown in FIG.

13 is a diagram showing another relationship between the pad-VCC current in the device shown in FIG.

14 is a diagram showing another relationship between the pad-VCC current in the device shown in FIG.

15 is a diagram showing another relationship between the pad-VCC current in the device shown in FIG.

16 is a diagram showing a relationship between a detection threshold value and an applied voltage in the device shown in FIG.

FIG. 17 is a diagram showing a configuration of a circuit operation mode detection device according to another embodiment of the invention as set forth in claim 4;

FIG. 18 is a diagram showing a configuration of a circuit operation mode detection device according to an embodiment of the present invention.

FIG. 19 is a diagram showing a configuration of a circuit operation mode detection device according to an embodiment of the present invention.

FIG. 20 is a diagram showing a configuration of a circuit operation mode detection device according to an embodiment of the present invention.

21 is a diagram showing bonding to a lead frame in the device shown in FIG.

FIG. 22 is a diagram showing a configuration of a conventional circuit operation mode detection device.

[Explanation of symbols]

A, B, C, D, E, F, P31 to P33, P61 to P
63, P81 to P82 circuit operation switching pads P, PX, PY, P30, P60, P70, P80, P
91 to P93 Pads connected to the outside of the package TA4 to TA10, TC1, TC2, TP31 to TP3
3, TP61 to TP63, TP71 to TP73, TP8
1-TP83, TN91-TN94 P-channel transistors TA0, TN31b, TN31c, TN31d, TN3
2d, TN32c, TN33b, TN61b to TN63
b. TN71b, TN71c, TN71d, TN72
b, TN72c, TN73b, TN81b, TN81
c, TN81d, TN82b, TN82c, TN83
b, TN93 to TN96 N-channel transistors TA1 to TA3, TE6 to TE9, TN31a to TN3
3b, TN61a to TN63a, TN71a to TN73
a, TN81a to TN83a, TN91 to TN92 High resistance N channel transistors IA1 to IA6, IC2, IC3, IE3 to IE7, I
31a to I33a, I31b to I33b, I61a to I
63a, I61b to I63b, I81a to I83a, I
81b to I83b, I91 to I98 Inverters NOR3 to NOR5 NOR gates F71 to F73, F83, F91 to F92 Circuit operation switching fuses L1 to L6 Lead frames A1 to A6, B1 to B6 Bonding pads

Claims (7)

[Claims] 1. A detection pad having a number smaller than the number of circuit operation modes for detecting a circuit operation mode selected from a plurality of circuit operation modes in accordance with a value of a current flowing through the pad, and a set circuit operation mode, respectively. And a plurality of conduction control circuits that receive the potentials of the corresponding operation mode switching pads and output a conduction control signal according to the bonding state of the operation mode switching pads. And a plurality of current supply circuits which are commonly connected to the detection pad and are controlled to conduct in accordance with the conduction control signals of the corresponding conduction control circuits to give different conduction currents to the detection pad, respectively. Operation mode detection device. 2. A plurality of detection units each comprising the conduction control circuit according to claim 1, an operation mode switching pad, and a current supply circuit; and a connection control circuit for switching and controlling the detection pad and each of the detection units. 2. The circuit operation mode detecting device according to claim 1, further comprising a control pad for supplying a switching control signal to the control circuit. 3. A detection pad having a number smaller than the number of circuit operation modes for detecting a circuit operation mode selected from a plurality of circuit operation modes according to a value of a current flowing through the pad, and a set circuit operation mode, respectively. The plurality of operation mode switching pads and the potentials of the corresponding operation mode switching pads are received, and the plurality of operation modes are selected in accordance with the bonding state of the operation mode switching pads and the preset priority order. Of the conduction control circuit that selectively selects the operation mode from among the selection circuits, the conduction control circuit that receives the operation mode selected by the selection circuit, and outputs the conduction control signal according to the selected operation mode. A current supply circuit for determining and controlling a current value flowing through each detection pad according to a conduction control signal. Road operation mode detection unit. 4. A detection pad having a number smaller than the number of circuit operation modes for detecting a circuit operation mode selected from a plurality of circuit operation modes in accordance with a value of a current flowing through the pad, and a set circuit operation mode, respectively. And a plurality of conduction control circuits that receive the potentials of the corresponding operation mode switching pads and output a conduction control signal according to the bonding state of the operation mode switching pads. And a plurality of currents that are commonly connected to the detection pad and are supplied with a specific potential via the detection pad to give a conduction current to the detection pad based on the value of the conduction control signal of the corresponding conduction control circuit. A circuit operation mode detection device comprising: a supply circuit. 5. A detection pad having a number smaller than the number of circuit operation modes for detecting a circuit operation mode selected from a plurality of circuit operation modes in accordance with a value of a current flowing through the pad and a set circuit operation mode, respectively. Multiple operation mode switching fuses, and multiple conduction control circuits that output conduction control signals according to the connection / disconnection status of the corresponding operation mode switching fuses, and common connection to the detection pad A plurality of current supply circuits that are supplied with a specific potential via the detection pad and that provide the detection pad with a conduction current based on the value of the conduction control signal of the corresponding conduction control circuit. And circuit operation mode detector. 6. A circuit operation mode detection device according to claim 4, comprising a plurality of operation mode switching fuses and a conduction control circuit according to claim 5. 7. A plurality of detection pads for detecting a circuit operation mode selected from a plurality of circuit operation modes according to a current value flowing through the pad, and a chip provided according to the set circuit operation mode, A plurality of operation mode switching fuses that are connected or disconnected before packaging, and a plurality of conduction control circuits that output a conduction control signal according to the connection / disconnection state of the corresponding operation mode switching fuses, respectively. A plurality of current supply circuits for supplying a conduction current to a detection pad according to a conduction control signal of a corresponding conduction control circuit.