JPH07262767A - Synchronous dram - Google Patents

Abstract

PURPOSE:To increase the speed of continuous reading of data from different banks and to attain high-speed reading from an arbitrary address in an SDRAM performing the operation in synchronization with a clock supplied from the outside. CONSTITUTION:When data are continuously read from different banks 51-54 and each of the banks 51-54 is selected as the reading object, the number of clocks CLK subtracted by one from the number of banks, i.e., three clocks CLK are made not to be supplied after that. Data D4-D4 from the banks 51-54 are multiply out putted by shifting by one clock of the clocks CLK, the data D1-D4 outputted multiplexed, by are selected by means of an output data selecting circuit 7 and outputted to the outside.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous DRAM (Synchronous DRA) which operates in synchronization with a clock signal (hereinafter referred to simply as a clock) supplied from the outside.
M [DynamicRandom Access Memory]. Below, SD
RAM).

[0002]

2. Description of the Related Art Generally, an SDRAM is a bank (BAN) whose active state and inactive state can be independently controlled.
K), a plurality of memory cell array regions are provided, and banks are selected by giving a bank address together with an active instruction.

[0003]

Currently, in SDRAMs, the maximum clock frequency is around 100 MHz, but in conventional SDRAMs, a pipeline system is adopted, and the length of one pipe is Since the upper limit of the clock frequency is determined, it has been difficult to increase the speed of reading from an arbitrary address more than it is now.

In view of the above point, the present invention does not adopt a pipeline system, but makes it possible to speed up continuous reading from different banks and to speed up reading from an arbitrary address. It is an object to provide an SDRAM.

[0005]

FIG. 1 shows the SDRA of the present invention.
It is a circuit diagram showing the principle of the main part of M, SDRA of the present invention
M denotes banks 1 ₁ to 1 _n (banks 1 ₃ to 1 _n-1 are not shown) and clock supply circuits 2 ₁ to 2 _n (clock supply circuits 2 ₃ to 2 _n-1 are not shown). Omitted) and an output data selection circuit 3. Note that n is a power of 2.

[0006] Here, the clock supply circuit 2 ₁ to 2 _n, respectively, which are provided corresponding to the bank ₁ 1 to 1 _n, the clock CLK supplied externally, corresponding banks ₁ 1 - 1 _n .

However, these clock supply circuits 2 ₁ to 2
_n is the clock CLK that is supplied after that when the corresponding bank 1 ₁ to 1 _n is selected for reading.
Among them, n-1 clocks CLK are not supplied to the corresponding banks 1 ₁ to 1 _n .

Further, the output data selection circuit 3 is provided in the bank 1
_The data DQ to be output to the outside is selected from the data D1 to Dn output from ₁ to 1 _n .

The output data selection circuit 3 is, for example,
The selection operation is controlled by a signal obtained by delaying the bank address input with the read instruction by n clocks and decoding the delayed bank address.

[0010]

In the present invention, when the corresponding banks 1 ₁ to 1 _n are selected for reading, of the clocks CLK supplied thereafter, n-1 clocks CL.
Clock supply circuits 2 ₁ to 2 _n are provided so as not to supply K to the corresponding banks 1 ₁ to 1 _n .

[0011] As a result, in the case of reading the data D1~Dn continuously from different banks _{1 1 ~1 n,} the bank ₁ 1 -
Clock CLK for reading data D1 to Dn from 1 _n
Can be performed multiple times by shifting by 1 clock each.

In the present invention, the banks 1 ₁ ...
Since the output data selection circuit 3 that selects the data DQ to be output to the outside among the data D1 to Dn output from 1 _n is provided, the data D1 that is multiply output from the banks 1 ₁ to 1 _n. ~ Dn can be selected and output to the outside.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will now be described with reference to FIGS.
Burst length (length of data read by one read command)
The description will be made by taking as an example the case where the above is applied to the SDRAM set to 1.

FIG. 2 is a circuit diagram showing an essential part of an embodiment of the present invention. In the figure, 5 _{1 to} 5 ₄ are banks, and 6 _{1 to} 6 ₄ are clocks CLK supplied from the outside as bank clocks. BCL
The clock supply circuit supplies K1 to BCLK4 to the banks 5 _{1 to} 5 ₄ .

Further, 7 is the data DQ to be output to the outside of the data D1 to D4 output from the banks 5 _{1 to} 5 _4.
Is an output data selection circuit and 8 is an output data selection control circuit for controlling the selection operation of the output data selection circuit 8.

The clock supply circuits 6 _{1 to} 6 ₄ have the same circuit configuration. For example, the clock supply circuit 6 ₁ is configured as shown in FIG.

In the figure, 10 is a clock input terminal to which a clock CLK is input, 11 to 13 are NAND circuits, and 14 to 1
Reference numeral 6 is an inverter, 17 is a ternary counter, CACCL _{1 is} an internal read command signal of H level output from a predetermined control circuit (not shown) when a read command for the bank 5 ₁ is input, and output from the inverter 15. CLK-DIS is a clock disable signal.

Here, the ternary counter 17 is reset when the internal read command CACCL1 is set to H level, and its output is set to H level. Thereafter, the number of clocks CLK is counted, and the third clock CLK is counted. Is counted, the output is returned to the L level.

FIG. 4 is a waveform diagram for explaining the operation of the clock supply circuit 6 _1. FIG. 4A shows the clock CL.
K, FIG. 4B shows an internal read command signal CACCL1, FIG. 4C
Shows the output of the ternary counter 17, FIG. 4D shows the clock disable signal CLK-DIS, and FIG. 4E shows the block clock BCLK1.

That is, in the clock supply circuit 6 ₁ , when the bank 5 ₁ is not selected as a read target, the output of the ternary counter 17 is L level and the internal read command signal CACCL1 is L level. The clock disable signal CLK-DIS = H level.

As a result, in this case, the clock CLK supplied to the clock input terminal 10 is transferred through the NAND circuit 11 and the inverter 14 to the bank clock BCLK1.
Is supplied to the bank 5 ₁ .

On the other hand, when a read command for selecting the bank 5 ₁ is input, the internal read command signal CACCL1 = H level is set correspondingly, and the ternary counter 17 is reset. Output = H level,
The counting is started from the clock CLK, the clock disable signal CLK-DIS is set to L level, the output of the NAND circuit 11 is fixed to H level, and the passage of the clock CLK supplied to the clock input terminal 10 is blocked. It

After that, when the ternary counter 17 counts the third clock CLK, the ternary counter 17
The output is set to the L level, and the clock disable signal C
LK-DIS = H level, and the clock CLK supplied to the clock input terminal 10 is supplied to the bank 5 ₁ as the bank clock BCLK1 via the NAND circuit 11 and the inverter 14.

That is, the clock supply circuit 6 ₁ cuts off the passage of three clocks CLK supplied subsequently when a read command for selecting the bank 5 ₁ is input.

The output data selection circuit 7 is constructed as shown in FIG. In the figure, 19 to 22 are banks 5 ₁
5 ₄ data input terminal to which data D1~D4 is input that is output from, 23 to 26 output data selection control signal is the output data selection control signal SL1~SL4 supplied from the output data selection control circuit 8 is input It is the input end.

27-30 are data input terminals 19-2.
2 is a transmission gate circuit for controlling the passage of data D1 to D4 input to 2; 31 to 34 are enhancement type pMOS transistors; and 35 to 38 are enhancement type nMOS transistors.

Further, 39 to 42 are inverters for inverting the output data selection control signals SL1 to SL4, 43 is a latch circuit for latching the data selected by the transmission gate circuits 27 to 30, 44 and 45 are inverters, and 46. Is the data output terminal.

Here, the output data selection control signal SL1 =
H level, output data selection control signals SL2 to SL4 = L
When the level is set, the transmission gate circuit 27 = ON,
The transmission gate circuits 28 to 30 are turned off, and the data D1
Is selected.

Further, the output data selection control signal SL2 = H
Level, output data selection control signals SL1, SL3, SL
4 = transmission gate circuit 28 = L level
It is turned on and the transmission gate circuits 27, 29, 30 are turned off, and the data D2 is selected.

The output data selection control signal SL3 = H
Level, output data selection control signals SL1, SL2, SL
4 = Transmission gate circuit 29 = L level
It is turned on and the transmission gate circuits 27, 28, 30 are turned off, and the data D3 is selected.

Further, the output data selection control signal SL4 = H
When the level and output data selection control signals SL1 to SL3 are set to L level, the transmission gate circuit 30 = ON, the transmission gate circuits 27 to 29 = OFF, and the data D4 is selected.

The output data selection control circuit 8 is constructed as shown in FIG. In the figure, BS0 and BS1 are bank addresses, 47 is bank addresses BS0 and BS
It is a delay circuit that delays 1 by 4 clocks.
Is a D flip-flop circuit (DFF).

Reference numerals 56 and 57 are inverters, 58 is a bank address decoder, and 59 to 62 are NOR.
Circuit.

The D flip-flop circuits 48 to 55 are provided.
Are configured as shown in FIG. 64, 6 in the figure
Reference numeral 5 is a transmission gate circuit, 66 and 67 are enhancement type pMOS transistors, and 68 and 69 are enhancement type nMOS transistors.

Reference numerals 70 to 72 are inverters. In the inverter 72, 73 and 74 are enhancement type pMOS transistors, and 75 and 76 are enhancement type nMOS transistors. Reference numeral 77 is a latch circuit, and 78 and 79 are inverters.

Here, the D flip-flop circuits 48, 5
The bank addresses BS0 and BS1 input to 2 are delayed by 4 clocks and output from the D flip-flop circuits 51 and 55.

In this case, the bank address BS
When 0 = L level and bank address BS1 = L level, the output data selection control signal SL1 = H level, the output data selection control signals SL2 to SL4 = L level, and the output data selection circuit 7 selects the data D1. It

When bank address BS0 = H level and bank address BS1 = H level, output data selection control signal SL2 = H level, output data selection control signals SL1, SL3, SL4 = L level, and output data The data D2 is selected in the selection circuit 7.

When the bank address BS0 = H level and the bank address BS1 = L level, the output data selection control signal SL3 = H level, the output data selection control signals SL1, SL2, SL4 = L level, and the output data The data D3 is selected in the selection circuit 7.

When the bank address BS0 = L level and the bank address BS1 = H level, the output data selection control signal SL4 = H level, the output data selection control signals SL1 to SL3 = L level, and the output data selection circuit. At 7, the data D4 is selected.

FIGS. 8 and 9 are time charts for explaining an example of the read operation in this embodiment. Bank 5 ₁ → bank 5 ₂ → bank 5 ₃ → bank 5 ₄ → bank 5
The operation waveforms are shown when data is continuously read in the order of ₁ → bank 5 ₂ → bank 5 ₃ → bank 5 ₄ .

8A and 9A show clock CL.
K, FIGS. 8B and 9B are data D1 output from the bank 5 ₁ , FIGS. 8C and 9C are data D2 output from the bank 5 ₂ , and FIGS. 8D and 9D are data D3 output from the bank 5 ₃ . Figure 8E, FIG. 9E data D4, FIG. 8F output from bank 5 _4, FIG. 9F state of the output data selection control signal SL1 to SL4, Figure 8G, FIG. 9G data DQ outputted from the output data selection circuit 7 Is shown.

[0043] That is, when performing such a continuous readout, first, at time T1, an active command for activating a bank 5 ₁ gave (ACTV1), activates the bank 5 _1, then the time in T3, the active command for activating a bank 5 ₂ gave (ACTV2), activates the bank 5 _2.

Next, at time T5, an active command (ACTV3) for activating the bank 5 ₃ is given, and the bank 5 ₃ is activated.
The activated, at time T7, an active command for activating a bank 5 ₄ gave (ACTV4), activate the bank 5 _4.

Next, at time T8, a read instruction (RD1)
And the address of the bank 5 ₁ and the column address are given to start the read operation from the bank 5 ₁ , and then the time T9
Then, the read instruction (RD2), the address of the bank 5 ₂ and the column address are given to start the read operation from the bank 5 ₂ .

Next, at time T10, a read command (RD
3) and gives an address and a column address of the bank 5 _3, to start the read operation from the bank 5 _3, then, at time T11, giving the address of the read command (RD4) and the bank 5 ₄ and a column address , to start the read operation from the bank 5 _4.

Next, at time T12, a read command (RD
1) and the address of the bank 5 ₁ and the column address are given, and the read operation from the bank 5 ₁ is continued.
Next, at time T13, the read instruction (RD2) and bank 5
Given a _second address and a column address, causing continue to perform the read operation from the bank 5 _2.

Next, at time T14, a read command (RD
3), the address of the bank 5 ₃ and the column address are given, and the read operation from the bank 5 ₃ is continued,
Next, at time T15, the read instruction (RD4) and bank 5
The address of ₄ and the column address are given, and the read operation from the bank 5 ₄ is continued.

As a result, immediately after time T11, the bank 5 ₁
The output of the data D1 from the
The output of the data D2 from the bank 5 ₂ is started immediately after, the output of the data D3 from the bank 5 ₃ is started immediately after the time T13, and then the output of the data D2 from the bank 5 ₄ is started immediately after the time T14. The output of the data D4 is started.

Further, immediately after the time T15, the output of the data D1 from the bank 5 ₁ is started, and then the time T15.
Output of the data D2 from the bank 5 ₂ is started immediately after 16 and then output of the data D3 from the bank 5 ₃ is started immediately after the time T17 and then from the bank 5 ₄ immediately after the time T18. The output of the data D4 is started.

Here, the output data selection control signals SL1 to SL1.
Since the state of SL4 is as shown in FIGS. 8F and 9F, the data DQ output from the output data selection circuit 7
Becomes as shown in FIGS. 8G and 9G.

[0052] Thus, in the present embodiment, when reading data continuously from different banks 5 ₁ to 5 _4, if for each of the banks 5 ₁ to 5 _4, are selected for reading After that, the number of clocks CLK obtained by subtracting 1 from the number of banks, that is, three clocks CLK is not supplied, and the data D1 to D1 from the banks 5 _{1 to} 5 ₄ are not supplied.
The output of D4 is multiplexed by shifting by one clock of the clock CLK, and the data D1 output in multiplex
.About.D4 are selected by the output data selection circuit 7 and output to the outside.

Therefore, according to this embodiment, continuous reading from different banks 5 _{1 to} 5 ₄ can be speeded up, and reading from any address can be speeded up.

In the above embodiments, the case where the burst length is 1 has been described as an example, but the present invention can be applied even when the burst length is set to 2 or more. .

[0055]

As described above, according to the present invention, when data is continuously read from different banks, if each of the banks is selected as a read target, then it is externally read. Of the clocks supplied, the number of banks minus 1 is not supplied, and the data from different banks are read out in a multiplex manner by shifting the clocks supplied from the outside by one clock each. Since it is configured to select the data to be output multiplex and to output it to the outside, it is possible to speed up continuous reading from different banks and speed up reading from an arbitrary address. .

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a principle of a main part of an SDRAM of the present invention.

FIG. 2 is a circuit diagram showing a main part of an embodiment of the present invention.

FIG. 3 is a circuit diagram showing a clock supply circuit provided in an embodiment of the present invention.

FIG. 4 is a waveform diagram for explaining the operation of the clock supply circuit provided in the embodiment of the present invention.

FIG. 5 is a circuit diagram showing an output data selection circuit provided in an embodiment of the present invention.

FIG. 6 is a circuit diagram showing an output data selection control circuit provided in an embodiment of the present invention.

FIG. 7 is a circuit diagram showing a D flip-flop circuit which constitutes an output data selection control circuit provided in an embodiment of the present invention.

FIG. 8 is a time chart for explaining an example of a read operation in the embodiment of the present invention.

FIG. 9 is a time chart for explaining an example of the read operation in the embodiment of the present invention.

[Explanation of symbols]

(Fig. 1) 1 ₁ , 1 ₂ , 1 _n bank 2 ₁ , 2 ₂ , 2 _n clock supply circuit 3 Output data selection circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Yukinori Kodama, 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor, Kensho Suzuki, 1015, Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Yoshihiro Takemae 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Masao Taguchi 1015, Kamedotachu, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Jun Hatakeyama 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Junji Ogawa, 1015, Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited

Claims (3)

[Claims] 1. A first bank, a second bank, ...
Is a power of 2) and is provided corresponding to each of the first, second, ..., Nth banks, supplies an externally supplied clock signal to the corresponding bank, and the corresponding bank reads. Of the clock signals to be supplied after that, a plurality of clock supply circuits configured not to supply n−1 clock signals to the corresponding bank; A synchronous DRAM comprising: an output data selection circuit that selects data to be output to the outside from data output from the second ... nth bank. 2. The clock supply circuits each have a counter for counting the clock signals,
When a read instruction for the corresponding bank is input, an internal read instruction signal output corresponding to this,
2. The synchronous D according to claim 1, wherein the output of the counter is used to control the supply of the clock signal to the corresponding bank.
RAM. 3. The output data selection circuit is configured to control a selection operation by a signal obtained by delaying a bank address input with a read instruction by n clocks and decoding the bank address. A synchronous DRAM according to item 1 or 2.