JPH07262050A - Recovering device from runaway - Google Patents

Abstract

PURPOSE:To automatically recover a state just before runaway when the runaway has occurred. CONSTITUTION:A processor part 1 executes a given task and when the execution is normally performed, a counter reset signal 27 is generated from a decoder part 2 in a fixed cycle, and according to the counter reset signal 27, a counter part 23 intermittently resets counting. When a runaway is generated at the processor part 1, the decoder part 2 stops generating the counter reset signal 27, and the counter part 23 is not reset but continues counting as it is. When the count value exceeds a fixed value, a recovery signal 22 is transmitted to the processor part 1 and the processor part 1 recovers the state before the runaway.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a runaway recovery device.

[0002]

2. Description of the Related Art Generally, in a computer or the like, when a runaway occurs, an operator pushes a reset switch to restart the computer from the beginning.

Therefore, conventionally, there has been no means in a computer or the like for automatically returning to a state immediately before a runaway when a runaway occurs.

[0004]

In the conventional computer, there is no means for automatically returning to the state immediately before the runaway when a runaway occurs, and there is no way but to press the reset switch to restart the entire system from the beginning. I didn't, so
There was a problem that the contents of work memory etc. were cleared by the reset of the whole system, and all the work done so far was wasted.

In view of the above situation, it is an object of the present invention to provide a runaway recovery device capable of automatically returning to a state immediately before a runaway when a runaway occurs.

[0006]

According to the present invention, a processor unit that executes a given task and a counter reset signal is generated at a constant cycle when the task is normally executed in the processor unit. And a counter unit which is reset by a counter reset signal and which sends a return signal to the processor unit when the count value exceeds a certain value. is there.

[0007]

The operation of the present invention is as follows.

The processor unit executes a given task.

When the task is normally executed in the processor section, the processor section causes the decoder section to generate a counter reset signal at a constant cycle.

Then, the counter section is reset intermittently by the counter reset signal, so that the count value does not exceed a preset constant value. Therefore, the processor section directly executes the task. To continue.

However, when a runaway occurs in the processor section, the decoder section does not generate a counter reset signal, so the counter section is not reset and continues counting.

Then, the count value of the counter section exceeds the predetermined value, and at that time, a return signal is sent to the processor section, and the processor section is returned to the state immediately before the runaway.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

1 and 2 show an embodiment of the present invention.

In the figure, reference numeral 1 denotes a processor unit such as a CPU for executing a given task in a computer, and 2 denotes a task unit connected to the processor unit 1 via an address bus 3 and a data bus 4. A decoder unit 5 for management, 5 is a memory connected to the lower order of the decoder unit 2 via an address bus 3 and a data bus 4, and 6 is a memory 5
An interrupt table assigned to a part of the interface, 7 is an interface connected to the lower part of the decoder unit 2 via the address bus 3 and the data bus 4, and 8 to 10 are each connected to the interface 7, for example, a sensor. And external devices such as actuators and valves.

In this case, the tasks executed by the processor unit 1 include the input of the detection data 11 from the external device 8 such as a sensor, the control calculation based on the detection data 11 and the memory 5 based on the control calculation. Rewriting of control variables and external devices 9, 10 such as actuators and valves
Means output of control signals 12 and 13 for.

Other external devices include floppy disk drives, hard disk drives, magneto-optical disk drives, CD-ROM drives and other external storage devices, displays and other display devices, and printers and other printing devices. , Etc., but omitted for convenience of explanation.

Reference numeral 14 is a crystal oscillator, and 15 is a crystal oscillator 14.
A frequency divider that divides the frequency of the clock signal 16 generated in (1) (reduces the frequency) to generate a processor unit operating clock signal 17 of several MHz to several tens of MHz, and 18 is generated by the crystal oscillator 14. It is a frequency divider that divides the clock signal 16 to generate a task management clock signal 19 of about several hundred kHz.

The processor unit operating clock signal 17 enters the clock input of the processor unit 1, and the task management clock signal 19 enters the timer interrupt input of the processor unit 1.

A frequency divider 21 for dividing the clock signal 16 generated by the crystal oscillator 14 to generate a counting clock signal 20 of several Hz to several tens Hz is provided.
A counter unit 23 is provided which counts the counting clock signal 20 and generates a return signal 22 such as a task reset signal or an interrupt signal (NMI non-maskable interrupt) sent to the processor unit 1 when the count exceeds a certain value. .

The counter unit 23 is provided with, for example, a 5-digit register 24, the lower 4 bits of which are used as counting bits 25, and the highest 1 bit is used as a carry bit 26. When a carry is generated in the use bit 26, the count bit 25 is reset and the return signal 22 is generated.

The count number for carrying the carry bit 26 can be set externally.

When the task in the processor unit 1 is normally executed, the processor unit 1
The decoder unit 2 is provided with a counter reset signal 2 at a constant cycle.
7 is generated.

Numeral 28 is an initial reset signal which is given to the counter section 23 when the system is started up.

Next, the operation will be described.

When the computer system according to the present invention is started up, first, the crystal oscillator 14 oscillates the clock signal 16, and the clock signal 16 is divided by the frequency divider 15 to obtain several MHz to several tens of MHz. The processor unit operating clock signal 17 is used as the processor unit operating clock signal 17.
Is input to the clock input of the processor unit 1.

As a result, the processor unit 1 operates at the frequency of the processor unit operation clock signal 17.

The decoder unit 2, the memory 5 and the interface 7 are connected to the processor unit 1 via the address bus 3 and the data bus 4, and the processor unit 1, the memory 5 and the interface 7 are managed by addresses. Therefore, the decoder unit 2 is connected via the address bus 3.
By designating an address to the external unit 8 connected between the processor unit 1 and the memory 5 via the data bus 4 or the processor unit 1 and the interface 7,
Data can be exchanged with the device 10.

As a result, the processor unit 1 has the memory 5
The external device 8-10 is controlled by executing the program stored in.

Further, the crystal oscillator 14 is controlled by the frequency divider 18.
The clock signal 16 oscillated from the
The task management clock signal 19 has a frequency of about Hz, and the task management clock signal 19 is input to the timer interrupt input of the processor unit 1.

Then, a timer interrupt is generated in the processor unit 1 in accordance with the cycle of the task management clock signal 19.
As shown in FIG. 2, after a certain dead time B from the rise, the processor unit 1 inputs the detection data 11 from the external device 8 such as a sensor and the detection data 11 according to the program stored in the memory 5. Control calculation based on,
Rewriting the control variables to the memory 5 based on the control calculation,
A large number of tasks such as output of control signals 12 and 13 to external devices 9 and 10 such as actuators and valves (1 to 1
n) are sequentially switched or interrupted to perform time-division parallel processing of these tasks.

On the other hand, when the computer system is started up, the frequency divider 21 divides the frequency of the clock signal 16 oscillated from the crystal unit 14 to several Hz to several tens Hz.
The count clock signal 20 is transmitted to the counter unit 23.

Then, the counter section 23 waits for the dead time a by the initial reset signal 28, and then the lower 4 digits of the counting bit 2 of the register 24 provided therein.
5 is used to start counting the count clock signal 20.

When each task in the processor section 1 is normally executed, the counter section reset signal 27 is generated from the decoder section 2 at a constant cycle b in which the task makes one cycle. Reset signal 2
7 causes the counter unit 23 to count the count bit 25 before the carry bit 26 of the register 24 is carried.
Will be reset.

Therefore, when the task is executed normally,
A new count is generated in the counter section 23 every cycle b.

However, as shown in FIG. 2, when a runaway a occurs and the task execution in the processor unit 1 is not normally performed, the task switching is stopped midway and the task is not looped. Therefore, the counter reset signal 27 is not generated from the decoder unit 2 even if the predetermined period B has elapsed.

However, since the counter section 23 counts by the counting clock signal 20 independently of the processor section 1, the counting of the counting bit 25 is continued as it is, and the preset predetermined count is set. When the number is reached (time C), a carry occurs in the most significant carry bit 26 of register 24.

As a result, the counting bit 25 is reset, and at the same time, the return signal 22 is generated toward the processor section 1.

The return signal 22 is input to the processor unit 1 as a task reset signal or an interrupt signal.

When the return signal 22 is the task reset signal, the processor unit 1 resets only the task that is running out of control and restarts the task from the first task, as indicated by the broken line D in FIG. To do so.

Alternatively, when the return signal 22 is an interrupt signal, the processor unit 1 interrupts the task in runaway, calls the contents of the interrupt table 6 of the memory 5, and stores it in the interrupt table 6. Executed instructions. The instruction is, for example, an instruction for resetting a task as shown by a broken line D in FIG. 2 or an instruction for waiting for an operator's instruction as shown by a virtual line E in FIG.

As described above, according to the present invention, even if a runaway occurs, only the task is automatically reset without resetting the entire system. Therefore, the contents of the work memory or the like are retained as they are without being erased. Therefore, it is possible to perform safety return and quick return.

Therefore, the present invention is suitable for fields in which reliability is particularly important, such as banking, medical care, transportation, and aerospace.

The present invention is not limited to the above-described embodiments, and it goes without saying that various modifications can be made without departing from the gist of the present invention.

[0045]

As described above, according to the runaway recovery device of the present invention, when a runaway occurs, it is possible to automatically return to the state immediately before the runaway.

[Brief description of drawings]

FIG. 1 is a schematic system diagram of an embodiment of the present invention.

FIG. 2 is a time chart of FIG.

[Explanation of symbols]

 1 processor section 2 decoder section 22 return signal 23 counter section 27 counter reset signal

Claims (1)

[Claims] 1. A processor unit for executing a given task, a decoder unit for generating a counter reset signal at a constant cycle when the task in the processor unit is normally executed, and a counter reset signal. A runaway recovery device, comprising: a counter section that is reset by the counter section and sends a return signal to the processor section when the count value exceeds a certain value.