JPH07260835A - Signal strength detector - Google Patents

Abstract

PURPOSE:To improve accuracy in a signal strength detection of an analog signal such as white noise, etc. CONSTITUTION:An output in which high frequency components are removed by a filter 4 is converted by an A-D converter 16 to a digital value. The converted digital value is accumulated by an adder 8, and more significant bit of the accumulated result is used as a signal strength detected result. An analog signal 1 is attenuated to a linear area of amplifying characteristics of a preamplifier 2 in response to the signal strength detected result. Accordingly, the preamplifier 2 is always operated in the linear area of the characteristics, thereby improving a signal strength detecting accuracy.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a signal strength detector,
In particular, the present invention relates to a signal strength detector that detects the signal strength of a noisy analog signal such as white noise.

[0002]

2. Description of the Related Art Generally, a radar device mounted on a platform such as an aircraft or an artificial satellite applies a transmission pulse to a target on the ground at regular intervals and receives the reflected echo to perform necessary processing for imaging. ing. The level of the reflected echo that is received is not always constant and may become excessive. Therefore, the signal strength of the received signal is detected at each transmission / reception cycle, and the level is stabilized by applying a certain amount of attenuation for reception. May protect the vessel.

That is, as shown in FIG. 5, in response to the reference trigger 70, a transmission pulse 71 is transmitted at regular intervals, and a reflection echo resulting therefrom is input as a reception signal 72. In this case, one cycle A of the reference trigger 70 is one transmission / reception cycle, and the strength of the received signal in the signal strength detection section B is the detection target.

When the intensity of the received signal C1 exceeds the reference value, the attenuation amount of an attenuator (not shown) is increased for subsequent received signals. That is, the received signal C2 is attenuated to a low level and then input. As described above, by attenuating according to the detection result of the signal strength, the level can be stabilized and the receiver can be protected. In such a case, it is necessary to accurately obtain the strength of the received signal.

Further, when a celestial body such as the sun is observed and imaged by using a well-known radio interferometer, when a high time resolution is required, the correlation value between the reception signals of the antenna is set for each short cycle. In addition to the calculation, it is necessary to accurately obtain the reception electric field strength for each antenna in the same cycle.

As described above, when the signal strength of the analog signal is accurately obtained, the signal strength detector is used. Conventionally, there have been two types of signal strength detectors of this type, for example.

The first method is disclosed in Japanese Patent Laid-Open No. 57-3576.
It is described in Japanese Patent No. about this,
This will be described with reference to FIG.

In FIG. 6, when the rate multiplier 3 is driven by the output of the adder / subtractor 2, its output becomes a signal of a constant cycle having a duty ratio corresponding to the contents of the adder / subtractor 2, and the lowpass filter 4 The direct-current voltage a corresponds to the contents of the adder / subtractor 2. This voltage a is input to the comparator 6 together with the analog voltage b to be measured, and the voltage is compared here.

While the voltage a is lower than the voltage b, the adder / subtractor 2 is switched to the addition mode by the output of the comparator 6, and when one cycle of the pulse output from the pulse generator 1 elapses, the adder / subtractor 2 The contents are added by the value corresponding to one step. This operation is repeated, and when the relationship between the voltage a and the voltage b is reversed, the adder / subtractor 2 is switched to the subtraction mode by the output of the comparator 6, and the content is subtracted by one step.

As a result, the relationship between the voltage a and the voltage b is reversed again, and this time, the contents of the adder / subtractor 2 are added by one step. When this operation is repeated thereafter, the voltage a repeats increasing / decreasing for each cycle of the pulse centering on the voltage b, and the convergence of the comparison operation is detected by this operation, and the output of the adder / subtractor 2 at this time is calculated. The calculation is performed by the device 7, and a signal corresponding to the analog voltage b is applied to the display device 8 for display.

The second method is the method shown in FIG. In the figure, a signal input 1 is amplified by a preamplifier 2 to a predetermined level, its output is passed through a detection diode 3, and then a high-frequency component is removed by a low-pass filter 4.
The output of the low-pass filter 4 is integrated for a certain period by an analog integrator 5 using an operational amplifier, and then the signal strength value 7
Is output as.

[0012]

In the former one of the two methods of the above-mentioned conventional signal strength detector, the signal level generated for comparison with the input analog signal is output from the pulse generator. Since there is only one step of the pulse to increase, there is a disadvantage that it takes time to detect the coincidence state when the level difference between the two is large. To detect the strength of the high frequency signal (video band), An adder / subtractor, rate multiplier, and arithmetic unit that operate at extremely high speed are required. Furthermore, when a wideband noise signal is used as the input signal, the display content changes constantly,
There is also the drawback that the value will not be constant.

In the latter case, a wide range of noise signals can be dealt with, but if the dynamic range of the signal input is large, the time waveform will enter the region beyond the linear region of the preamplifier or the detector diode with a certain probability. However, there is a drawback that a loss occurs in the calculation of the intensity value, and the linearity in measurement is deteriorated. Furthermore, the ratio of the offset component due to the analog integration operation to the input signal level is
There is also a drawback that it increases when the input signal level is low.

The present invention has been made to solve the above-mentioned drawbacks of the prior art, and its object is to provide a signal strength detector capable of detecting the strength of an analog signal with higher accuracy. .

[0015]

A signal strength detector according to the present invention comprises a filtering means for removing high frequency components from an input analog signal and an AD for converting the filtering output into a digital value.
It is characterized in that it includes a conversion means and a calculation means for calculating an average value of the converted digital values, and the calculated average value is used as a detection result.

[0016]

The filtering means removes high-frequency components from the input analog signal such as white noise and converts the filtered output into a digital value. The average value of the converted digital values is calculated, and this calculated value is used as the signal strength detection result. The average value is calculated by accumulating the converted digital values and using the upper predetermined bits of the accumulation result as the signal strength detection result.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of an embodiment of a signal strength detector according to the present invention, and the same portions as those in FIG. 7 are designated by the same reference numerals. In the figure, a signal strength detector according to an embodiment of the present invention includes a preamplifier 2 that inputs an input analog signal 1 through an attenuator 11 and amplifies the analog signal.
A multiplier 13 that squares the amplified output 20, a low-pass filter 4 that removes high-frequency components from the squared output 130, and an output 40 after the removal that is approximately the same as the maximum width of the analog input range of the AD converter 6. And a prescaler 15 that amplifies up to the level.

Further, the signal strength detector of the present embodiment has an output 150 of the prescaler 15 for each cycle of the clock signal 61.
Is converted into digital data, and an adder 8 for sequentially adding the converted digital data 60 is included. That is, the sampling is performed for each cycle of the clock signal 61, and the adder 8 accumulates the sampling.

Furthermore, the signal strength detector of the present embodiment is a comparator for comparing the digital data 12 of predetermined upper bits of the addition result of the adder 8 with the signal strength set value 91 which is a preset reference value. 9 and the input analog signal 1 input to the preamplifier 2 according to the comparison result.
And an attenuator 11 for attenuating. When the attenuator 11 performs the attenuation operation as a result of the comparison operation, the comparator 9 outputs the operation information 90 which is 1-bit information indicating that. Then, the high-order predetermined bit digital data 12 of the addition result of the adder 8 and the information 90 of the comparator 9 are output as the signal strength data of this detector.

The number of bits of the digital data 12 is determined according to the number of bits of the AD converter 6. For example, using a 6-bit AD converter 6, one detection section (see FIG.
When the AD conversion is performed 1000 times in the detection section B), the upper 9 bits of the accumulation result of the adder 8 may be output as the digital data 12. In other words, by removing the upper bits of the accumulation result, the quantization error is canceled,
The detection results in one detection section are averaged.

In such a configuration, the analog signal 1 input to the attenuator 11 at regular intervals is a noise signal with a wide dynamic range and a wide dynamic range in which the amplitude probability distribution follows a Gaussian distribution. White noise is given as an example of the analog signal 1.

The attenuator 11 attenuates the analog signal 1 only when the comparator 9 outputs the control signal 10.
When the control signal 10 is not output from the comparator 9, the analog signal 1 is sent to the preamplifier 2 as it is.

The preamplifier 2 has an amplification characteristic consisting of a linear region and a curved region as shown in FIG. The preamplifier 2 is operated only within the range where the input level is X or higher and Y or lower, and the preamplifier 2 and the preamplifier 2 are operated.
A sufficient level difference 31 from the saturation level of is set. As a result, the output level of the preamplifier 2 becomes X1 or more and Y1 or less, and the preamplifier 2 always operates in the linear region.

The signal amplified by the preamplifier 2 is squared by the multiplier 3. Here, even if the maximum input level Y1 to the preamplifier 2 is input, the output of the multiplier 3 is prevented from entering the saturation region of the input / output characteristics. That is, the operating point of the multiplier 3 is set sufficiently low so that the multiplier 3 always operates in the straight line portion.

As a result, the probability 42 that the input amplitude is outside the linear region 41 of the preamplifier 2 and the multiplier 3 in the amplitude probability distribution curve of the noisy signal shown in FIG. it can.

The squared output 130 output from the multiplier 13
After the high-frequency component is removed by the low-pass filter 4, it is input to the prescaler 5 including a high-precision low-offset type operational amplifier and amplified to a level matching the analog input range of the AD converter 6, and the AD signal is added by the clock signal 7. It is converted into a digital signal by the converter 6.

At this time, the cutoff frequency fc of the low-pass filter 4, the band characteristic of the prescaler 5, the AD converter 6
The period T of the clock signal 7 is selected as follows.

First, the A / D converter 6 has a maximum analog input range, and the gain of the prescaler 5 is increased accordingly.

Next, the operational amplifier in the prescaler 5 originally has a narrow band, but the band is further narrowed by increasing the gain to be slightly narrower than the band of the low-pass filter 4. That is, referring to FIG. 4 showing the frequency band characteristics of the prescaler 5 and the low-pass filter 4, the characteristic 51 of the low-pass filter 4 is made slightly wider than the characteristic 52 of the prescaler 5. Note that FIG.
The symbol fc is the cutoff frequency of the low pass filter 4.

The period T of the clock signal 7 is selected to be slightly larger than the reciprocal 1 / fc of the cutoff frequency of the low pass filter 4. This is to roughly sample the output 40 of the low pass filter 4.

Returning to FIG. 1, the digital data 60 converted by the AD converter 6 is accumulated in the adder 8 and the upper predetermined bits of the accumulation result are output as the digital data 12. The data 12 is compared with a signal strength setting value corresponding to the output level Y1 at the point Y in FIG. 2 in the comparator 9, and if the data 12 is larger than the setting value, the control signal 10 is output to the attenuator 11. As a result, the attenuator 11 attenuates the input analog signal according to the attenuation amount 32 shown in the figure, and inputs the level to the preamplifier 2 as Z in the figure.

Further, from the comparator 9, information 90 indicating that the damping operation has been performed is added to the data 12,
It is output as the signal strength data of this detector. This information 90 indicates that the damping operation has been performed when the value is “1” and indicates that the damping operation has not been performed when the value is “0”. Information 9 added to this data 12
If 0 is considered, the correct detection value can be obtained.

The switching of the attenuation amount in the attenuator 11 is performed in a section other than the detection section B in FIG.
That is, it is performed between the end of one detection section and the start of the next detection section.

Here, assuming that the analog signal input to this detector is V = 2 ^1/2 Vrms cos ωt, the multiplier 13
The multiplication output 130 of V becomes V ² = Vrms ² + Vrms ² cos 2ωt (1) The first term on the right side of the equation (1) is a DC component proportional to the signal strength to be obtained, and the second term is an invalid high frequency component. This invalid high frequency component is removed by the low pass filter 4. As a result, a signal having a waveform in which the direct current component slightly includes the alternating current component is input to the prescaler 15.

Since the prescaler 15 operates in a narrow band as described above (see FIG. 4), after the AC component is further removed from the output of the multiplier 13, it is converted into digital data by the AD converter 6 and added by the adder 8 Entered in.

In short, by performing the square operation required for signal detection and the amplification operation of the preceding stage at a low level in the linear operation region by the attenuator, the linearity of the intensity detection value with respect to the noisy input signal can be enhanced. .

Further, after the output of the low-pass filter is taken out at a low level and amplified by an operational amplifier having a small offset,
Since AD conversion is performed and addition is performed, the ratio of the offset amount to the signal level can be suppressed as compared with the conventional analog integration method.

Further, the error to the digital data due to the frequency components near the cutoff frequency and higher than that included in the signal input to the AD converter and the quantization error for each sampling are obtained by taking the upper bit of the addition result. It is possible to remove the digits and extract the value that converges to the true intensity value.

The final data 12 accumulated by the adder 8 as described above is a squared value, not an absolute value.
If necessary, you can calculate the square root. This data 1
Reference numeral 2 is for controlling the attenuator 11, and a relative value is sufficient.

Although the case of white noise has been described in the above embodiments, the present invention is not limited to this and it is obvious that the present invention can be widely applied to the case of detecting the signal strength of an analog signal. Further, it is obvious that the present invention can be widely applied not only to a radar device mounted on an artificial satellite or the like but also when detection of signal strength is required.

[0042]

As described above, according to the present invention, a high frequency component is removed from an input analog signal such as white noise, converted into a digital value, an average value of the converted digital values is calculated, and the calculated value is calculated. By using the signal strength detection result, there is an effect that the signal strength detection accuracy can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a signal strength detector according to an embodiment of the present invention.

FIG. 2 is a diagram showing the input / output characteristics of the preamplifier in FIG. 1 and its operating range.

FIG. 3 is an amplitude probability distribution map of a noisy signal.

FIG. 4 is a band characteristic diagram of the low-pass filter and the prescaler in FIG.

FIG. 5 is a waveform diagram showing an operation of a general radar device using a signal strength detector.

FIG. 6 is a block diagram showing a configuration of an example of a conventional signal strength detector.

FIG. 7 is a block diagram showing the configuration of another example of the conventional signal strength detector.

[Explanation of symbols]

 2 preamplifier 4 low-pass filter 6 AD converter 8 adder 9 comparator 11 attenuator 13 multiplier 15 prescaler

Claims (6)

[Claims] 1. A filtering means for removing high frequency components from an input analog signal, an AD converting means for converting the filtering output into a digital value, and a calculating means for calculating an average value of the converted digital values. A signal strength detector including the calculated average value as a detection result. 2. The calculating means includes accumulating means for accumulating the digital values converted by the AD converting means,
A signal strength detector characterized in that a digital value of upper predetermined bits of the accumulation result is used as the detection result. 3. Amplifying means for amplifying the analog signal, which has a linear region and a curved region, and inputs the amplified analog signal to the filtering means; and the analog signal according to the detection result. The signal strength detector according to claim 1 or 2, further comprising an attenuator that attenuates the signal to a linear region and then inputs the amplified signal to the amplifier. 4. The AD conversion means converts an input signal into a digital value at every predetermined period, and an input allowable maximum value of this converter and a maximum value of the filtered output are substantially the same. The signal strength detector according to any one of claims 1 to 3, further comprising: a prescaler that amplifies the filtered output so as to be input to the converter. 5. The filtering device includes a multiplier that multiplies the analog signal and a low-pass filter that removes a high frequency component of the multiplication output.
The signal strength detector according to any one of 1. 6. The signal strength detector according to claim 1, wherein the analog signal is white noise.