JPH07256560A - Polishing cloth and manufacture thereof and flattening of substrate - Google Patents

Abstract

PURPOSE:To reduce the global stage difference caused by the roughness and fineness of a pattern, as for a polishing cloth and the flattening of a basic plate. CONSTITUTION:A polishing cloth is formed by attaching an upper layer polishing cloth 2 which is harder than an underlayer polishing cloth 1, on the cloth 1 and has the grooves 3 for cutting-divide the underlayer polishing cloth 2 and isolate the divided parts. A polishing cloth has the grooves 3 formed in lattice form. A method for forming the polishing cloth consists of a process for attaching the upper layer polishing cloth 2 which is harder than the under-layer polishing cloth 1, on the layer 1, and a process for forming the grooves 3 for cutting-divide the upper layer polishing cloth 2 and isolate the divided parts. A method for flattening a substrate for polishing the surface of the semiconductor substrate is achieved by using the under or upper layer polishing cloth.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a polishing cloth to be attached to a plate of a polishing plate when polishing the surface of a semiconductor substrate or the like, a method for manufacturing the same, and a method for planarizing the substrate.

As device performance improves, wiring density increases and miniaturization progresses, so the depth of focus of exposure in the lithography process is becoming shallower. Further, as the number of wiring layers increases, the unevenness of the substrate surface becomes large, and there is an increasing demand for planarization of the interlayer insulating film.

The most efficient method for flattening the interlayer insulating film is by polishing. The polishing cloth has the greatest effect on the flattening efficiency of the polishing.

[0004]

2. Description of the Related Art At present, a polishing cloth used for flattening a semiconductor substrate in a semiconductor device manufacturing process is shown in FIG.
Most of them have a structure called IC1000 / SUBA400 (manufactured by Rodel) as shown in. Although this structure has not been published, the polishing cloth is made of soft and thick SUBA400 and hard and thin IC1000.
It has a layered structure. And, IC1000 with many holes is often used. The interlayer insulating film deposited on the semiconductor substrate is polished and flattened by using the polishing cloth having such a structure.

When the polishing cloth having the two-layer structure is used for polishing as described above, the variation in the polishing amount within the substrate surface is much improved as compared with the case of the IC1000 alone. For example, if the polishing cloth of IC1000 alone is used, the variation of the polishing amount in the substrate surface will be 20%.
If you use 1000 / SUBA400 polishing cloth, it will be reduced to about 7%.

[0006]

[Problems to be Solved by the Invention] However, IC1000
When polishing is performed using a polishing cloth of / SUBA400, the thickness of the interlayer insulating film on the dense area of the wiring is about 0.35 μm thicker than the thickness of the interlayer insulating film on the sparse area. This difference in thickness is called a global step.

As the wiring becomes finer, the depth of focus of exposure becomes shallower, and it is necessary to reduce the global level difference to about 0.2 μm in the device of the 0.35 μm rule.
Semiconductor devices have dense wiring areas (especially SRAM areas)
There is a dense region (logic region), and it is difficult to reduce the global step difference in the chip where these regions coexist to 0.2 μm or less in a device with a 0.35 μm rule.

According to the present invention, the variation in the polishing amount within the substrate surface
The aim is to reduce the level to 00 / SUBA400 polishing cloth and to reduce the global level difference to less than 0.2 μm.

[0009]

[Means for Solving the Problems]
1) A polishing cloth having a groove 3 formed by laminating a harder upper polishing cloth 2 on a lower polishing cloth 1 and cutting the upper polishing cloth 2 to separate the divided parts, or 2 ) The polishing cloth according to 1 above, wherein the grooves 3 are formed in a grid pattern, or 3) a step of adhering a harder upper polishing cloth 2 to the lower polishing cloth 1 and cutting and dividing the upper polishing cloth 2 And a method of manufacturing a polishing cloth having a step of forming a groove 3 for isolating the divided portion, or 4) using a polishing cloth described in 1 or 2 above, and planarizing the substrate by polishing the surface of the substrate. To be done.

[0010]

The reason why the global step becomes large when the polishing cloth has a two-layer structure is that the upper hard polishing cloth is largely deformed by the deformation of the lower soft polishing cloth during polishing, as shown in FIG. This is because not only the convex region of the upper interlayer insulating film but also the concave region is polished.

Therefore, the present inventors attach the upper layer polishing cloth to the lower layer polishing cloth, and then cut and divide the upper layer polishing cloth to isolate the divided portions so as to minimize the influence of the lower layer polishing cloth. Tried that.

Therefore, as shown in FIG. 2, the IC1000
Create a polishing cloth with a / SUBA400 structure. That is, the hard polishing cloth IC1000 is bonded onto the soft polishing cloth SUBA400. Next, a groove having a depth at which the upper layer polishing cloth was cut was formed. The grooves are formed, for example, in a lattice shape as shown in FIG. 1, and the individual upper polishing cloths divided by the grooves are isolated.

[0013]

Embodiments FIGS. 1 (A) and 1 (B) are explanatory views of an embodiment, and FIG.
Is a cross-sectional view and FIG. 1 (B) is a plan view.

In the figure, reference numeral 1 is a soft lower polishing cloth, SU
BA400 and 2 are hard upper polishing cloths, and IC1000 and 3 are grooves formed in a grid pattern. 2A to 2C are explanatory views of an embodiment of the manufacturing method.

In FIG. 2A, a hard polishing cloth IC1000 and a soft polishing cloth SUBA400 are prepared. In Figure 2 (B),
Glue the hard polishing cloth IC1000 onto the soft polishing cloth SUBA400.

In FIG. 2 (C), grid-like grooves having a depth at which the upper polishing cloth is cut are formed. The area of the island-like region isolated by the groove was 5 mm × 5 mm, the groove width was 3 mm, and the groove depth was 3 mm.

In order to investigate the effect of this embodiment, a wafer having a chip pattern shown in FIG. 5 was prepared. The hatched portion of this chip pattern is a convex portion. This wafer was polished using the polishing cloth of the example and the polishing cloth of the IC1000 / SUBA400 structure of the conventional example. The polishing conditions are as follows: SC112 (colloidal silica) polishing agent, 200g / polishing pressure.
It is cm ² .

Twenty-five 6-inch wafers were evaluated using each of these two polishing cloths. The evaluation items are the in-plane variation of the polishing amount and the global level difference. The results are shown in Table 1.

[0019]

[Table 1] Global variation of in-plane variation of polishing amount Example 7.2 ± 2.8% 0.20 μm Conventional example 7.0 ± 2.7% 0.34 μm As can be seen from Table 1, the in-plane variation of polishing amount is almost the same, The global level difference in the example is reduced to about 60% of that in the conventional example. Therefore, it became clear that the example is effective in improving the global step.

According to the results of experiments conducted by the present inventors, the thickness of the upper polishing cloth is 0.5 mm or more, and the length of one side of the rectangular or square island region cut in a grid pattern is 5 to 15 mm, and the groove width is Is
0.5mm or less and groove pitch of 5 to 15mm are suitable.

In the examples, IC1000 was used as the upper polishing cloth and SUBA400 was used as the lower polishing cloth, but a soft rubber-like material such as silicone rubber, non-woven fabric, polyurethane, etc. was used as the lower polishing cloth, and a hard upper layer was formed on top of this. A polishing cloth may be adhered.

Although the semiconductor wafer is flattened in the embodiment, the present invention is also effective for a quartz substrate or a glass substrate of a mask or a reticle, or a transparent glass substrate of a liquid crystal display device instead of this. .

[0023]

EFFECTS OF THE INVENTION According to the present invention, the variation in the polishing amount in the substrate surface is suppressed to the extent that the IC1000 / SUBA400 polishing cloth is used, and the thickness of the interlayer insulating film on the dense area of the wiring and the sparse area It was possible to reduce the difference, that is, the global level difference to less than 0.2 μm.

As a result, a device with a rule of 0.35 μm can be applied, which can contribute to miniaturization of semiconductor devices.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of an embodiment.

FIG. 2 is an explanatory diagram of an example of a manufacturing method.

FIG. 3 is an explanatory diagram of a conventional example.

[Figure 4] Illustration of problems

FIG. 5: Chip pattern formed on a sample wafer

[Explanation of symbols]

 1 Soft lower-layer polishing cloth SUBA400 2 Hard upper-layer polishing cloth IC1000 3 Grooves formed in a grid pattern

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical indication location H01L 21/304 321 M (72) Inventor Fumitoshi Sugimoto 1015 Uedoda, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Incorporated (72) Inventor Village ▲ Kaku ▼ Maki 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Fujitsu Limited

Claims (4)

[Claims] 1. A groove (3) comprising a lower polishing cloth (1) and an upper polishing cloth (2) which is harder than the lower polishing cloth attached to the upper polishing cloth, and the upper polishing cloth (2) is cut and divided to separate the divided parts. ) Is included. 2. The polishing cloth according to claim 1, wherein the grooves (3) are formed in a lattice shape. 3. A step of adhering a harder upper polishing cloth (2) to the lower polishing cloth (1), and a groove (3) for cutting and dividing the upper polishing cloth (2) to isolate the divided parts. And a step of forming a polishing cloth. 4. A method of planarizing a substrate, which comprises polishing the surface of the substrate with the polishing cloth according to claim 1.