JPH07255130A - Compensator of reactive power - Google Patents

Abstract

PURPOSE:To shorten the waiting time wasted until a power-factor improving capacitor is connected again after issue of its making command, by outputting the gate signal of a thyristor from a gate circuit when anode-cathode voltage of the thyristor is changed from its backward voltage into its forward or its power supply voltage reaches the peak value after the issue of the making command. CONSTITUTION:To AND circuits 19a, 19b, the making command of a power- factor improving capacitor is inputted. Also, the peak voltage of a power supply 1 is sensed by its sensor 17, and is inputted to the AND circuits 19a, 19b via OR circuits 18a, 18b respectively. The outputs of the AND circuits 19a, 19b are applied to the gates of thyristors 10a, 10b via gate circuits 13a, 13b and pulse transformers 20a, 20b respectively. Then, the anode-cathode voltage of one of the thyristors 10a, 10b is changed from its reverse voltage to its forward voltage, and this change is sensed by one of forward-voltage sensors 14a, 14b, and further, one of one-shot multivibrators 15a, 15b is driven by the output of one of the sensors 14a, 14b. Thereby, the waiting time wasted until the power- factor adjusting capacitor is connected is shortened, and as a result, the rush current into the capacitor is suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reactive power compensator for power factor compensation and voltage fluctuation compensation.

[0002]

2. Description of the Related Art FIG. 4 shows an entire system of a conventional reactive power compensator.

In the figure, 1 is a power station, substation,
Power supply representing a transformer or the like at the demand end, 2 is a system connected to the power supply 1, 3 is a capacitor device for a reactive power compensator described later that is connected to the system 2, and 4 is a line load connected to the system 2 or an arc at the demand end It is a load that rapidly changes the reactive power of the furnace, rolling mill, etc.

Reference numeral 5 is a reactive power detection transducer for detecting reactive power by connecting to a current transformer 6A (CT shown in the figure) and a transformer 6B (PT shown in the figure), and 7 is a gate signal output means for outputting a gate signal. The means 7 determines a capacitor bank of the reactive power compensating device capacitor device 3 in order to compensate the reactive power according to the reactive power detected by the reactive power detection transducer 5 and outputs a closing command signal. 8 is provided, and a gate controller 9n that inputs a closing command signal and a forward voltage detection signal described later and outputs a gate signal is provided.

On the other hand, in the reactive power compensator capacitor device 3 described above, the antiparallel thyristors 10a and 10b, the capacitor 11 and the DC reactor 12 are connected in series to the system 2 to form a capacitor bank. A plurality of anti-parallel thyristors 10
Between a and 10b gate and cathode (hereinafter referred to as gate)
Is connected to the gate controller 9n so that the gate signal from the gate controller 9n is input.

With the above configuration, when reactive power fluctuations are caused by the load 4 connected to the grid 2, first, the reactive power detection transducer 5 receives a current signal and a voltage signal via the current transformer 6A and the transformer 6B. Is input to.

In the reactive power detection transducer 5, the phase and magnitude of the reactive power are calculated from the input current signal and voltage signal, and as shown in FIG. The reactive power detection signal is output, while the negative reactive power detection signal is output when the reactive power is advanced.

Next, the closing bank calculator 8 to which the reactive power detection signal is input determines the capacitor bank to be closed in a preset order.

For example, the closing bank calculator 8 is adapted to drop the capacitor banks into the system 2 in a preset order. First, the phase-advancing capacitor reactive power equivalent amount and the reactive power generated by the first capacitor bank are set. The power detection signal is compared, and when the reactive power signal is in phase lag (+) and the capacitor bank reactive power is equivalent, a corresponding command, for example, is output to the gate controller 9a. As a result, when a forward voltage detection signal described later is input, the gate signal is output from the gate controller 9a to the corresponding first capacitor bank, and the thyristors 10a and 10b are fired. Therefore, the thyristors 10a and 10b are brought into conduction, the capacitor 11 and the DC reactor 12 are connected to the system 2, and the lagging reactive power by the load 4 is canceled by the leading reactive power of the charged capacitor bank.

At this time, if the lagging reactive power due to the load 4 is large, that is, if the reactive power detection signal is larger than the equivalent amount of the reactive power of the capacitor when the first capacitor bank is turned on, the capacitor when the next capacitor bank is turned on is similarly set. It is compared with the equivalent amount of reactive power, and according to this result, a closing command is further issued to the next gate controller 9b,
Further, the next gate controller 9n is sequentially arranged in a predetermined order.
A close command is issued.

On the contrary, when the reactive power equivalent amount of the capacitor bank input as described above becomes larger than the reactive power signal by the load 4, the reactive power detection signal output from the reactive power detection transducer 5 is shown in FIG. As shown
It becomes a phase reactive reactive power and becomes negative.

In this case, the closing bank calculator 8 provided in the gate signal output means 7 sequentially outputs the capacitor bank trip command to the corresponding gate controller 9n, and the system 2 is connected.
To disconnect from. As a result, the reactive power is controlled to be the reactive power detection signal of zero or a certain value shown in FIG.

In this case, the capacitance of the capacitor bank is uniformly set to the same, but the capacitance of the capacitor is 1: 2 :.
By changing to 4: 8 ..., it is possible to perform fine reactive power compensation with a small number of capacitors.

Further, in FIG. 4, the DC reactor 12 for suppressing the oscillating inrush current and protecting the capacitor is provided, but the DC reactor 12 may not be provided.

Next, the operation of the capacitor device 3 for a reactive power compensator will be described in detail with reference to the schematic diagram 6 shown in FIG. 4 in which one capacitor bank is extracted.

First, a closing command is input from the closing bank calculator 8 to the gate circuit 13, and the forward voltage detector 14 is supplied.
When the forward voltage detection signals from a and 14b are input to the gate circuit 13 of the gate controller 9, the gate signal is changed to the thyristor 1
It is output to 0a and 10b. Along with this, the thyristors 10a and 10b are ignited, the anode and the cathode are electrically connected, and the capacitor 11 is connected to the system 2 and turned on.

In this case, as shown in FIG. 7, the power supply voltage Vr
The capacitor current ic advances 90 ° with respect to s.

Therefore, as shown in FIG. 7, the section in which the current flows to each of the thyristors 10a and 10b corresponds to the capacitor current ic and corresponds to the section S in which the current flows to the thyristor 10a.
1 and the section S2 flowing to the thyristor 10b.

Next, when the voltage across the capacitor 11 is zero or when the voltage across the capacitor 11 is between the peak state of the voltage of the power supply 1, the gate signal is output at the timing described below. .

That is, when the voltage of the power supply 1 is in a peak state, the voltage difference between the peak voltage of the power supply 1 and the voltage across the capacitor 11 is between the anode and cathode of the thyristors 10a and 10b (hereinafter referred to as "between AK"). ) Is applied. In this case, when the applied voltage between AK of the thyristors 10a and 10b is large and the thyristors 10a and 10b are ignited, a large oscillatory inrush current is generated.

Therefore, when the applied voltage between the AK of the thyristors 10a and 10b is small, the gate signal is applied. That is, the gate signal is given by the forward voltage detection signal described above.

As shown in FIG. 8, the capacitor voltage V
When c is between the peak of the power supply voltage Vrs and zero, the voltage between A and K of the thyristor 10a is T shown in FIG.
The section has a reverse voltage. In this case, the capacitor closing command U is output at time t1, and at time t2, the forward voltage detector 14a detects the forward voltage, and the gate signal V is output immediately after the closing. As a result, when the forward voltage of the thyristor 10a is small, the gate signal V
Is output, it is possible to suppress the generation of a large inrush current.

After that, at time t3 when the power supply voltage Vrs becomes zero, the voltage across the capacitor 11 is charged to a peak.

However, in practice, since the DC reactor 12 is connected in series to the capacitor 11, the power supply voltage Vrs
The voltage is charged to a value higher than the peak value of 1 by the applied voltage of the DC reactor 12.

Therefore, as described above, the capacitor current i
A gate signal is applied to the thyristors 10a and 10b so that c is advanced by 90 ° with respect to the power supply voltage Vrs.

In the reactive power compensator shown in FIG. 4,
Although the reactive power is adjusted by determining the capacitor bank to be input according to the reactive power of the grid 2, even if the voltage of the grid 2 or the power factor is detected and the capacitor bank is determined according to these values. Good.

[0027]

However, when the above-mentioned conventional reactive power compensator is subjected to the timing control as described above, the following inconvenient problem occurs.

That is, in the description of FIG. 8, time t4
After the turn-on command of the capacitor 11 is turned off and the gate signal is turned off, the capacitor current ic becomes zero, so that the capacitor voltage Vc becomes higher than the peak value of the power supply voltage Vrs by the applied voltage of the DC reactor 12. is there. It is also assumed that the peak value of the power supply voltage Vrs is lowered for some reason after the thyristors 10a and 10b are turned off.

At this time, the reverse voltage is applied to the thyristor 10a, and only the forward voltage is applied to the thyristor 10b. In this state, even if a re-closing command is input to the capacitor 11 at time t5, the voltage Vak between AK of the thyristor 10a does not immediately cross zero (portion A in the drawing), that is, the forward voltage detector 14a. Does not output forward voltage detection signal. Therefore, even if there is a capacitor closing command signal, it is necessary to wait until the capacitor 11 is discharged and the capacitor voltage Vc becomes lower than the peak value of the power supply voltage Vrs. There was a drawback that the adjustment could not be done finely.

Further, even in the reactive power compensator without the DC reactor 12, since there are many reactance elements between the lines, the capacitor voltage Vc is the peak of the power supply voltage Vrs in the same manner as above under the above conditions. Even if a state in which the voltage is higher than the value continues and there is a capacitor closing command signal, it is necessary to wait until the capacitor 11 is discharged and the capacitor voltage Vc becomes lower than the peak value of the power supply voltage Vrs. However, there is a drawback that the reactive power cannot be finely adjusted.

Therefore, the present invention provides a reactive power compensator capable of immediately outputting a gate signal regardless of the state of the charging voltage of the capacitor and the peak value of the power supply voltage when the capacitor is re-applied to the system. The purpose is to

[0032]

According to the invention of claim 1, a thyristor connected in anti-parallel and a capacitor and a reactor are connected in series to these thyristors, and the thyristor is fired by a gate signal and connected to the system. And multiple capacitor banks for adjusting the reactive power, and the reactive power of the system to set the reactive power of the system to a predetermined value, or
A means for outputting a closing command signal according to the voltage or power factor, a means for outputting a forward voltage detection signal when the voltage applied to the thyristor of the capacitor bank changes from a reverse voltage to a forward voltage, and a peak of the system voltage. A gate signal output means is provided which includes a means for outputting a detection signal and a means for outputting a gate signal to a corresponding thyristor in accordance with an AND condition of the closing command signal and the corresponding forward voltage detection signal or peak detection signal. is there.

According to a second aspect of the present invention, thyristors connected in anti-parallel and capacitors connected in series to these thyristors are fired by a gate signal and connected to the system to adjust reactive power. A plurality of capacitor banks, a means for outputting a closing command signal according to the reactive power of the system, or the voltage or the power factor so that the reactive power of the system has a predetermined value, and the voltage applied to the thyristor of the capacitor bank are AND of a means for outputting a forward voltage detection signal when a reverse voltage becomes a forward voltage, a means for outputting a peak detection signal of a system voltage, and a forward voltage detection signal corresponding to the closing command signal or the peak detection signal. A gate signal output means including means for outputting a gate signal to a corresponding thyristor is provided depending on conditions.

[0034]

According to the invention of claim 1, a gate signal is output from the gate signal output means when a closing command is issued and the applied voltage between the anode and the cathode of the thyristor becomes a forward voltage or the power supply voltage reaches a peak. To be done. This allows
When the capacitor is re-applied to the system, the waiting time can be shortened until the gate signal is output.Moreover, the capacitor voltage is higher than the peak of the power supply voltage due to the reactor voltage, but the inrush current is increased in the reactor. Since it is suppressed, the capacitor can be sufficiently protected.

According to a second aspect of the present invention, the gate signal is output from the gate signal output means when the closing command is issued and the applied voltage between the anode and the cathode of the thyristor becomes a forward voltage or when the power supply voltage reaches a peak. Is output. As a result, when the capacitor is reapplied to the system, the waiting time can be shortened until the gate signal is output.
Fine reactive power compensation is possible.

[0036]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of a gate signal output means provided in a reactive power compensating apparatus showing a first embodiment of the present invention.

In FIG. 1, the same reference numerals as those in FIG. 6 showing the conventional example indicate the same or corresponding portions, and the main differences are the one-shot multi-circuits 15a and 15b, the voltage transformer 16 and the voltage peak detection. Device 17 and OR circuit 18a,
18b and AND circuits 19a and 19b are additionally provided.

Reference numerals 20a and 20b denote gate circuits 13.
The pulse transformers a and 13b are shown.

Here, the one-shot multi circuit 15a,
15b outputs a one-shot pulse signal when the forward voltage detection signals from the forward voltage detectors 14a and 14b change from "0" to "1". Voltage transformer 16
Is to lower the power supply voltage to a low level voltage and insulate it. The voltage peak detector 17 is the voltage transformer 1
The peak time of the input voltage waveform from 6 is detected, and a pulse signal is output as a peak voltage signal at that time.

When the pulse signals from the voltage peak detector 17 or the pulse signals from the one-shot multi-circuits 15a and 15b are input to the OR circuits 18a and 18b, they are Hi.
It outputs the gh signal. AND circuit 19a, 1
9b outputs a High signal to the gate circuits 13a and 13b when the logical product of the closing command signal and the High signals from the OR circuits 18a and 18b is established.

The operation of the above configuration will be described with reference to FIG. 2. First, when the capacitor voltage Vc is lower than the peak value of the power supply voltage Vrs, that is, from time t1 to time t4.
In the meantime, it is assumed that, for example, at t2, the closing command signal is output from the same closing bank computing unit 8 as shown in FIG.

In this case, the AND circuit 19a shown in FIG.
The closing command signal is input to 19b, and when the voltage between A and K of the thyristor 10a changes from the reverse voltage to the forward voltage at time t3, the forward voltage detector 14a outputs a pulse signal to the one-shot multi-circuit 15a. And the OR circuit 1
The High signal is input to the AND circuit 19a via 8a, and the gate signal is output from the gate circuit 13a to the thyristor 1.
It is output to 0a.

As a result, the closing command signal is input,
At the time t3 when the voltage between AK of the thyristor 10a changes from the reverse voltage to the forward voltage, the gate signal is changed to the thyristor 10a.
a is supplied to a and the generation of a large inrush current is suppressed. When the closing command signal is turned off at time t4, the AND circuit 19
The logical product of a is not established, and the gate signal is not output to the thyristor 10a. As a result, as at time t5,
The capacitor current ic also becomes zero.

In this case, even if the gate signal is turned off,
It flows through the thyristor 10a until the capacitor current ic becomes zero. Further, the capacitor voltage Vc is the power supply voltage Vrs.
Is charged by a voltage (Vl in the figure) applied to the DC reactor 12 higher than the peak value of.

Next, it is assumed that the closing command signal is input to the AND circuits 19a and 19b at time t6 when the capacitor voltage Vc from time t5 to t8 is higher than the power supply voltage Vrs. At this time, when the power supply voltage Vrs reaches the peak at time t7, the voltage peak detector 17 detects the peak value and the peak detection signal is output to the AND circuits 19a and 19b via the OR circuits 18a and 18b. This allows
The AND conditions of the closing command signal and the peak detection signal are satisfied by the AND circuits 19a and 19b, the thyristor 10a is ignited, the capacitor current ic starts to flow, and the capacitor voltage Vc starts to rise.

As described above, in the configuration of FIG. 6 showing the conventional example, as shown in FIG. 8, when the capacitor voltage Vc is higher than the peak value of the power supply voltage Vrs, the A of the thyristor 10a is changed.
-It takes some time to reach the zero crossing voltage between K and
Since the capacitor 11 was kept waiting until the discharge was completed, it was not possible to maintain the reactive power at a predetermined value in response to fluctuations in the reactive power. However, according to the present embodiment, the peak point of the power supply voltage Vrs, that is, the thyristor. When the forward voltage of 10a, 10b is low, the standby time can be as short as one cycle or less because the gate signal is detected and output. Therefore, the reactive power can be adjusted in a short time.

Next, a second embodiment of the present invention will be described with reference to FIG.

In FIG. 3, the same reference numerals as those of FIG. 6 showing the conventional example indicate the same or corresponding portions, and the main differences between them are the one-shot multi-circuits 15a and 15b, the voltage transformer 16 and the voltage peak detection. Device 17 and OR circuit 18a,
18b and AND circuits 19a and 19b are additionally provided, and the second embodiment is one in which the present invention is applied to a capacitor bank circuit in which a DC reactor is not provided.

Here, the one-shot multi circuit 15a,
15b outputs a one-shot pulse signal when the forward voltage detection signals from the forward voltage detectors 14a and 14b change from "0" to "1". Voltage transformer 16
Is to lower the power supply voltage to a low level voltage and insulate it. The voltage peak detector 17 is the voltage transformer 1
The peak time of the input voltage waveform from 6 is detected, and a pulse signal is output as a peak voltage signal at that time.

When the pulse signals from the voltage peak detector 17 or the pulse signals from the one-shot multi-circuits 15a and 15b are input to the OR circuits 18a and 18b, they are Hi.
It outputs the gh signal. AND circuit 19a, 1
9b outputs a High signal to the gate circuits 13a and 13b when the logical product of the closing command signal and the High signals from the OR circuits 18a and 18b is established.

With the above structure, as described with reference to FIG.
Even if the gate signal is turned off, it flows through the thyristor 10a until the capacitor current ic becomes zero. Further, the capacitor voltage Vc is charged to a state higher than the peak value of the power supply voltage Vrs by the voltage due to the reactance between the lines.

This capacitor voltage Vc is the power supply voltage Vrs
In the higher state, the closing command signal is the AND circuit 19
It is assumed that data is input to a and 19b. At this time, the power supply voltage V
When rs reaches the peak, the voltage peak detector 17 detects the peak value, and the peak detection signal is OR circuits 18a, 18
It is output to the AND circuits 19a and 19b via b. As a result, the AND circuits 19a and 19b satisfy the AND condition of the closing command signal and the peak detection signal, the thyristor 10a is fired, the capacitor current ic starts to flow, and the capacitor voltage Vc starts to rise.

As described above, even if the DC reactor 12 is omitted from the conventional example shown in FIG. 6, the capacitor voltage Vc becomes equal to the power source voltage Vr due to the reactance between the lines, as shown in FIG.
It becomes higher than the peak value of s, and the discharge of the capacitor 11 is waited until it is finished. Therefore, the reactive power could not be maintained at a predetermined value in response to the fluctuation of the reactive power. The gate point is output by detecting the peak point of the voltage Vrs, that is, the time when the forward voltage of the thyristors 10a and 10b is low. Therefore, the reactive power can be adjusted in a short time.

[0055]

As described above, according to the first aspect of the present invention, when the closing command is issued and the applied voltage of the thyristor reaches the forward voltage or the power supply voltage reaches the peak, the gate signal is output. Therefore, the capacitor can be immediately turned on when the capacitor is turned on again, the standby time can be shortened, and the inrush current of the capacitor can be reduced.

Further, according to the second aspect of the invention, even in a circuit in which the DC reactor is not provided in the capacitor bank, the capacitor can be immediately inserted at the time of re-insertion, the standby time can be shortened, and the reactive power can be finely adjusted. it can.

[Brief description of drawings]

FIG. 1 is a partial circuit diagram of a gate signal output means included in a reactive power compensator according to a first embodiment of the present invention.

FIG. 2 is an explanatory view showing the operation of FIG.

FIG. 3 is a partial circuit diagram of a gate signal output means included in a reactive power compensating apparatus showing a second embodiment of the present invention.

FIG. 4 is a system diagram of a reactive power compensator showing a conventional example.

5 is a characteristic diagram of a reactive power detection transducer provided in FIG.

FIG. 6 is a partial circuit diagram of the gate signal output means provided in FIG.

FIG. 7 is an explanatory diagram showing the relationship between the power supply voltage and the capacitor current of FIG.

FIG. 8 is an explanatory diagram showing the operation of FIG.

[Explanation of symbols]

 3 Capacitor Device for Reactive Power Compensator 4 Load 5 Reactive Power Detection Transducer 7 Gate Signal Output Means 8 Closing Bank Calculator 9a, 9b, 9n Gate Controller 10a, 10b Thyristor 11 Capacitor 12 DC Reactor 13a, 13b Gate Circuit 14a, 14b Forward voltage detector 15a, 15b One-shot multi-circuit 17 Voltage peak detector 18a, 18b OR circuit 19a, 19b AND circuit

Claims (3)

[Claims] 1. A thyristor connected in anti-parallel and a capacitor and a reactor connected in series to these thyristors, the plurality of thyristors being ignited by a gate signal to be connected to a system to adjust reactive power. Capacitor bank, means for outputting a closing command signal according to the reactive power of the system, or the voltage or the power factor so that the reactive power of the system has a predetermined value, and the voltage applied to the thyristor of the capacitor bank. Of the forward voltage detection signal or the peak detection signal corresponding to the closing command signal and the means for outputting the forward voltage detection signal when the forward voltage is changed from the reverse voltage to the forward voltage detection signal A gate signal output means comprising means for outputting the gate signal to a corresponding thyristor in accordance with an AND condition. Effective power compensation device. 2. Thyristors connected in antiparallel and capacitors connected in series to these thyristors, and a plurality of capacitor banks for adjusting the reactive power by firing the thyristors in response to a gate signal and connecting them to the grid. When,
Means for outputting a closing command signal according to the reactive power of the system, or the voltage or the power factor so that the reactive power of the system is set to a predetermined value, and the voltage applied to the thyristor of the capacitor bank are reversed from reverse voltage. When the voltage becomes a voltage, a means for outputting a forward voltage detection signal, a means for outputting a peak detection signal of the voltage of the system, and a gate according to an AND condition of the forward voltage detection signal corresponding to the closing command signal or the peak detection signal. A reactive power compensator comprising: a gate signal output means including means for outputting a signal to a corresponding thyristor. 3. The gate signal output means includes a closing bank calculator that outputs a closing command signal in accordance with the reactive power of the grid, the voltage, or the power factor, and the voltage applied to the thyristor is reversed from the reverse voltage. Forward voltage detector that outputs a forward voltage detection signal when a voltage is reached, a voltage peak detector that detects a peak of the voltage of the system and outputs a peak detection signal, the peak detection signal or the forward voltage detection signal And an AND circuit that outputs an ON signal by the logical product of the closing command signal and the peak detection signal or the forward voltage detection signal output via the OR circuit, and an AND circuit that outputs the ON signal. 3. The reactive power compensator according to claim 1 or 2, further comprising a gate circuit that outputs the gate signal in response to an ON signal that turns on.