JPH0725408U - ΔV detection control device of reactive power compensator - Google Patents

Abstract

(57) [Abstract] [Purpose] In the reactive power compensator SVC of the ΔV detection control system installed as a countermeasure against flicker in arc furnaces,
The DC detection circuit 12 has a specific load fluctuation frequency Δf.
In the .DELTA.V control circuit 13 and .DELTA.V control circuit, the control error due to the phase delay respectively generated is eliminated. [Configuration] The DC detection circuit 12 for the DC detection of the system voltage V _L, and system voltage V _L (AC), a phase of 90 ° Okurashi voltage of the voltage V _L (V _L1), and is advanced 90 ° Using a different voltage (V _L2 ), AC calculation method of In addition, the ΔV control circuit 1
The creation of the ΔV control signal V _C at 3, the DC detection signal V _L
(DC) is performed through the BPF 19, and the phase delay in this BPF is corrected by the APF 20 that changes the phase advance characteristic according to Δf detected by the Δf detection circuit 21.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a ΔV detection control system of a reactive power compensator (hereinafter referred to as SVC) installed in a power system as a countermeasure against flicker generated in an arc furnace or the like.

[0002]

[Prior art]

The SVC ΔV detection control method detects the system flicker (ΔQ) as the voltage fluctuation ΔV and controls the closed loop by using ΔV detected from the system voltage V _L as a control signal to suppress the voltage fluctuation due to ΔQ. An example is shown in FIG. 6 (Japanese Utility Model Laid-Open No. 60-42043).

[0003] In FIG, 1 is a system bus, infinite bus E power source side Inpi the _S - Tsunagare and through dance X _S, to supply the load 2. The SVC is a thyristor control reactor (hereinafter referred to as TCR) and a filter (hereinafter referred to as FC) that are connected in parallel to the system bus 1 and controls the reactive power Q _TCR supplied to the system to increase or decrease. , Stabilizes the system voltage _VL .

The SVC ΔV detection control is performed by detecting the voltage fluctuation ΔV of the system. This is the system voltage V received via the voltage transformer PT._LIs converted to DC by the voltage detector 5, and the reference value V is added by the adder 6._refIs taken out as ΔV and is passed through a voltage controller 7 which is a low-pass filter (hereinafter referred to as LPF) for stabilizing the control and the like. _C It is what Reference value V_refIs the output V of the voltage controller 7._COf the control signal V_CIs the TCR current I by the function circuit 9._TCR Is linearly converted in accordance with the relationship between the firing phase angle β and the firing phase angle β, and then the sawtooth wave V created by the power supply synchronization circuit 11 is generated by the pulse generation circuit 10._SYNCThe gate pulse G that controls the phase of the thyristor of the TCR at this cross timing is compared with_1,G₂Generate. In this way, the reactive power Q that suppresses the flicker ΔQ_TCRIs supplied to the system by closed loop control.

[0005]

[Problems to be solved by the device]

 During the operation of the arc furnace, the flicker ΔQ changes at the load fluctuation frequency Δf (20Hz <Δf <commercial frequency) according to the load operation pattern of the arc furnace customer.

Therefore, in the conventional ΔV detection control method shown in FIG. 6, a phase delay occurs in ΔV passed through the voltage detector 5 and the voltage regulator 7, resulting in a control error.

This phase delay will be described with reference to FIG. 7, which represents the control system of FIG. 6 with a transfer function. The voltage detector 5 converts the system voltage V _L into a DC by passing it through a squarer, an integrating circuit, and a switch.

[Equation 2] The phase delay here is φ ₁ = −tan ⁻¹ (ω / ω ₀₁ ). Voltage regulator 7 is a proportional integral circuit having a transfer function _{(K 2/1 + ST 2} ), the phase lag here is ^{_{φ 2 = -tan -1 (ω /}} ω 02). Assuming that the voltage detector 5 and the voltage regulator 7 have the necessary characteristics and a double cycle Δf occurs with respect to the commercial frequency, the phase delay is, for example, φ ₁ ≈ -30 °, φ ₂ ≈ -30 °. Therefore, the total phase delay of the control signal V _C is φ ₀ = φ ₁ + φ ₂ ≈−60 °.

This phase delay φ₀The control error due to is as shown in FIG. 8, for example. Now, the ΔV control signal V output from the voltage regulator 7_CThe phase delay of ′ is the true ΔV control signal V_CIt is assumed that the phase is delayed by 60 ° with respect to. At this time, the ΔV control signal V_C'And a sawtooth power supply synchronization signal V_SYNCGate pulse G generated at the intersection with_1,G ₂ Is the true control signal V_CWith respect to the timing (solid line) corresponding to, it shifts back and forth as shown by the broken line. Due to this deviation, the TCR current I_TCR′ Is the current I for the true value_TCR It is very different from, and it is also the reverse control. Therefore, it not only contributes to the improvement of flicker but also causes an unstable phenomenon in the system, which is a big problem for practical use.

Therefore, an object of the present invention is to provide a circuit system capable of eliminating the phase delay of the ΔV control signal V _C due to Δf.

[0010]

[Means for Solving the Problems]

The control circuit of the voltage detection type SVC provided by the present invention detects the system voltage V _L by converting it to a direct current, and creates a ΔV control signal from this variation to perform feedback control, thereby producing a voltage fluctuation ΔV of the system flicker level. In the reactive power compensator for suppressing the voltage, the system voltage V _L (AC) is detected, and the voltage V _L1 obtained by delaying the phase of the system voltage V _L by 90 ° and the voltage V _L2 advanced by 90 ° are created,

[Equation 3] A voltage detection circuit for performing DC detection of the system voltage V _L by performing the calculation of the bandpass filter to create a ΔV control signal by extracting the flicker component and suppression target from the DC signal (hereinafter BPF referred.) And , A Δf detection circuit that detects the load fluctuation frequency Δf from the DC signal input to this BPF, and the phase advance characteristic according to the detected Δf to change the position of the ΔV control signal generated with respect to Δf in the BPF. An all-pass filter (hereinafter referred to as APF) that corrects the phase delay is provided.

[0011]

[Action]

Above configuration, in the voltage detection circuit, in order to remove AC components from the square value of the system voltage V _L, phase-shift direction with respect to the system voltage V _L is ± opposite direction 90 ° two different voltages (V _L1, V _L2) of the square value ^{_{(V L1 2, V L2 2}} ) row Nau DC detected by the AC adding used. Since this calculation is performed at high speed, the phase delay due to the calculation itself can be ignored. In particular, this method cancels the phase error caused by Δf when creating the phase shift voltage by using two types of phase shift voltages (V _L1 , V _L2 ), thus reducing the influence of Δf and improving the detection accuracy. Can be higher.

Further, the BPF used as the voltage regulator cuts out low frequency components to take out the voltage variation ΔV, and cuts out high frequency components to stabilize the control. This B PF can reduce the phase delay with respect to Δf as compared with the LPF, thereby reducing the control error. Further, the phase delay in this LPF is corrected by the APF connected to this latter stage in accordance with Δf, and the control accuracy is further improved.

As described above, the above configuration corrects the influence of the phase delay due to Δf in both the voltage detection circuit and the voltage regulator.

[0014]

【Example】

 FIG. 1 shows an embodiment of this invention. In this embodiment, the voltage detection circuit and the ΔV control circuit (voltage regulator) in the configuration of FIG. 6 are improved so as to eliminate the control error due to the influence of Δf and to improve the response speed. Is common to FIG. Therefore, common parts are given the same reference numerals and the description thereof is omitted, and the voltage detection circuit 12 and the ΔV control circuit 13, which are the characteristic parts of the present invention, will be described below.

The voltage detection circuit 12 receives the system voltage V _L through the voltage transformer PT and outputs this DC conversion signal. The AC phase shifter (90 ° Lag) 14 a and the AC phase shifter (90 ° Lead) ) 14b and squarers 15a, 15b, 15c, adders 16a, 16b, 16c, coefficient units 17a, 17b, and 1/2 switch 18 are combined.

The circuit 12 converts the system voltage V _L into a direct current by the following procedure. First, the system voltage (V _L ) detected by the voltage transformer PT, the voltage (V _L1 ) obtained by delaying the phase by 90 °, and the voltage (V _L2 ) advanced by 90 ° are respectively set to 2 voltages. Square with the riders 15a, 15b, 15c. Next, the adder 16a adds _VL ² and _VL1 ² and the adder 16b adds _VL ² and _VL2 ² , respectively, and these addition values are multiplied by 1/2 by the coefficient units 17a and 17b. Further, after adding the added value by the adder 16c, the 1/2 switch 18 opens and closes the average value to obtain the voltage detection signal V _L (DC) corresponding to the effective value. Expressing this operation as an expression

[Equation 4]

The ΔV control circuit 13 extracts the voltage fluctuation component of the flicker level from the output of the voltage detection circuit 12 while stabilizing the control and outputs the ΔV control signal V _{C. The} BPF 19, APF 20, and It is composed of the Δf detector 21.

The BPF 19 takes out the voltage fluctuation of the flicker level to be suppressed. The APF 20 corrects the phase delay due to the Δf component in the BPF. This APF has a constant gain and only performs phase control compensation according to Δf. The Δf detector 21 detects the frequency of Δf from the input voltage to the BRF 19 and outputs it as a control signal for commanding the phase correction amount to the APF 20.

Next, the processing performed by the voltage detection circuit 12 and the ΔV control circuit 13 will be described.

The system voltage V _L taken out by the voltage transformer PT

[Equation 5]

[Equation 6] And the value obtained by squaring them with the squarers 15a, 15b, 15c is

[Equation 7] Becomes

These squared values V ₀ , V ₀₁ , V ₀₂ are added by adders 16a, 16b, 16c, coefficient units 17a, 17b, and 1/2 switch 18,

[Equation 8] Is calculated,

Now, assuming that the Δf component does not occur and only the fundamental wave is generated, as shown in FIG. 2, V ₀₁ and V ₀₂ have symmetrical waveforms that are 180 ° out of phase with respect to V 0. From the equation (1), V _L (DC) = V ₀ .

However, when Δf occurs, as shown in FIG. 3, V _L1 and V _L2 cause a phase delay corresponding to Δf in the AC phase shifters 14 a and 14 b to become V _L1 ′ and V _L2 ′, which causes an error. ΔE1 (= V _L1 ′ −V _L1 ) and ΔE ₂ (= V _L2 ′ −V _L2 ) occur. In this case, the above-mentioned relationship of V _L (DC) = V ₀ is not completely established, but the error ΔE ₁ and the error ΔE ₂ are positive and negative as shown in the figure, and their values are substantially equal ( ΔE ₁ + ΔE ₂ ≈0). Therefore, even if the equation (1) is calculated using the phase-delayed voltages V _L1 ′ and V _L2 ′,

[Equation 9] A DC signal _VL (DC) with a small error due to Δf can be taken out.

Next, the operation of the ΔV control circuit 13 will be described. The BPF 19 extracts only the flicker component and uses it as the control signal V _C , but if the Δf component is included in this, a phase delay occurs when passing through the BPF 19. Then, the Δf detector 21 detects the frequency of Δf included in the voltage V _L (DC) input to the BPF 19, and the APF 20 corrects the phase delay corresponding to the frequency.

Here, the transfer function of the BPF 19 is

[Equation 10]

The phase change is φ ₁ = 90 ° −2 · tan ⁻¹ (ω / ω ₀ ) [where ω ₀ = 1 / T ₁ ], and the transfer function of the APF 20 is

[Equation 11] The phase change is φ ₂ = + 2 · tan ⁻¹ (ω / ω _a ) [where ω _a = 1 / T _a ].

Therefore, the transfer function G ₀ (S) obtained by combining the BPF and the APF is G ₀ (S) = G ₁ (S) · G ₂ (S)

[Equation 12] And the combined value φ ₀ of the phase change is

[Equation 13] [However, ω = 2π · Δf, ω ₀ is a constant value, and ω _a is a variable value]

Here, by setting the phase change φ ₀ = 0 °, the phase correction by the APF 20 is completely performed.

[Equation 14] Therefore, Δf may be detected and f _a may be changed.

The Δf detection circuit 21 can be configured as shown in FIG. In FIG. 4, 22 is a filter for cutting harmonics, 23 is an LPF for detecting a direct current component, 24 is a comparator, and 25 is a PLL synchronizing circuit, which is input to the BPF 19 as shown in FIG. A signal V _{DC1 in} which harmonics are removed is created from the voltage V _L (DC), and this is compared with a DC component V _DC2 extracted by the LPF 23 by the comparator 24, and the cross timing is detected to detect a PLL circuit. At 25, a clock signal V _PLL corresponding to Δf is created. In this circuit, the circuit constant f _{a of} APF is

[Equation 15] Ra in equation (5) may be changed according to the detected frequency of Δf.

In the above-described embodiment controlled as described above, the following control response speed of the SVC is dominant. (Consider based on 60Hz)

[Equation 16] ΔV control circuit 13 is τ (DC) ≧ 2τ (ω ) ≒ 5.3m sec.

[0031] Therefore, the total control ^{delay, τ (L) ≧ τ 2} (ω) + τ 2 (DC) ≒ 6m sec and ing.

As described above, the response speed is increased, and high-speed control can be realized. This is a result of the adoption of the AC addition method in the voltage detection circuit 12 and the adoption of the BPF 19 in the ΔV control circuit 13.

[0033]

[Effect of device]

 In this invention, the voltage detection circuit 12 and the ΔV control circuit 13 each employ a circuit system in which the phase error due to Δf is corrected and at the same time the response speed of each circuit is increased. Nonetheless, high flicker reduction effect can be expected.

[Brief description of drawings]

FIG. 1 is a control system diagram of a reactive power compensator showing an embodiment of the present invention.

FIG. 2 is a voltage waveform diagram showing the operating principle of the voltage detection circuit of FIG.

FIG. 3 is a voltage waveform diagram for explaining that the voltage detection circuit of FIG. 1 can perform calculation with a small error with respect to Δf.

FIG. 4 is a block diagram of a ΔV control circuit showing a specific example of the Δf detection circuit in FIG.

5 is a voltage waveform diagram of each part of the Δf detection circuit of FIG.

FIG. 6 is a control system diagram showing a conventional reactive power compensator.

7 is a block diagram illustrating a phase delay with respect to Δf in the control system of FIG.

FIG. 8 is a diagram illustrating a state in which a control error occurs due to a phase delay with respect to ΔV in a conventional reactive power compensator.

[Explanation of symbols]

1 system bus 2 load 12 voltage detection circuit 13 ΔV control circuit 14a, 14b AC phase shifter 15a, 15b, 15c squarer 16a, 16b, 16c adder 17a, 17b coefficient unit 18 1/2 coefficient unit 19 bandpass filter (BPF) 20 All-pass filter (APF) 21 Δf detection circuit E _S Infinite bus SVC Reactive power compensator TCR Thyristor control reactor

Claims (1)

[Scope of utility model registration request] 1. A performs created by feedback control of the ΔV control signal from the fluctuation of the direct current signal of the system voltage V _L, the reactive power compensator for suppressing a voltage fluctuation ΔV of the flicker level of the system, the system voltage V _L ( AC) and detects the phase of this voltage V _L by 9
A voltage V _L1 delayed by 0 ° and a voltage V _L2 advanced by 90 ° are created, and The voltage detection circuit that performs the DC calculation of the system voltage V _L by performing the calculation of ## EQU1 ##, the bandpass filter that extracts the flicker component to be suppressed from the DC conversion signal to create the ΔV control signal, and the bandpass filter A Δf detection circuit that detects the load fluctuation frequency Δf from the input DC signal, and a phase advance characteristic is changed according to the detected Δf to correct the phase delay of the ΔV control signal that occurs with respect to Δf in the bandpass filter. An all-pass filter for controlling the ΔV detection control device of the reactive power compensating device.