JPH07251523A - Thermal recording apparatus - Google Patents

Abstract

PURPOSE:To provide a thermal recording apparatus equipped with self-diagnostic function automatically judging whether or not a heat history-control circuit is normal. CONSTITUTION:In a thermal recording apparatus selectively driving a plurality of the heating elements constituting a thermal head to generate heat and applying recording to a recording object on the basis of the generated heat, a heat history-control circuit 21 reading the present estimated temp. from a temp. history memory at each time when image data is applied to compare the same with set temp. and outputting a drive pulse for selectively driving the heating elements and a test image data generation circuit 22 inputting test image data to the heat history control circuit 21 are provided. Further, a counter 23 counting the drive pulse outputted from the heat history-control circuit 21 corresponding to the input of the test image data, a judging circuit judging whether or not the operation of the heat history control circuit is good on the basis of the count value of the counter 23 and a switch turning the drive power supply of the thermal head OFF during a test image data input period are provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thermal recording apparatus, and more particularly to a self-diagnosis function of a main circuit.

[0002]

2. Description of the Related Art As a printer or a recorder, a plurality of heating elements constituting a thermal head are selectively driven to generate heat, and the heat-sensitive recording paper is colored based on the generated heat.
A thermal recording device is used in which recording is performed by transferring the ink of an ink ribbon onto a recording paper.

By the way, the temperature of the heating element changes according to the driving state. FIG. 3 is an explanatory diagram showing an example of the temperature transition state of the heating element. As shown in the figure, when the temperature of the heating element is T ₀ and a drive pulse having a pulse width t _ON and an amplitude of V is applied, the temperature of the heating element rises to a temperature T _{P at} which the recording operation can be performed. To do. Then the temperature of the sufficient energization pause period _t'OFF, if any, with heating elements as shown by the broken line A will be lowered to T _0, the maximum temperature by applying a driving pulse again exceeds the temperature T _P There is no.

On the other hand, as shown by the solid line B, the driving cycle
Is faster, the temperature T₀The temperature starts to rise again before
The temperature gradually rises and the maximum temperature becomes warm.
Degree T _PWill exceed. As a result, in the case of thermal recording paper,
The coloring area increases, and notes such as "tailing" and "crushing" are displayed.
This will cause a phenomenon of deterioration of recording quality. And the worst
In some cases, the heating element will be burned out.

The applicant of the present application, in order to solve such inconvenience, Japanese Patent Application No. 1-275507 (Japanese Patent Application Laid-Open No. 3-1507).
No. 36876), a thermal recording device (hereinafter referred to as a prior application) using a thermal history control circuit for temperature tracking is proposed. This is to read the current estimated temperature from the temperature history memory every time image data is added to the heating element, compare it with the set temperature, and output the drive pulse for selectively driving the heating element. Is.

FIG. 4 is a block diagram of an embodiment of the prior application. The input data d _i to be recorded is temporarily stored in the line buffer 1 and used as a switch element.
Is read out to one of the input terminals. The first memory 4 stores in advance heat storage temperature data related to the recording operation of the plurality of heat generating elements that form the thermal head 9. The heat storage temperature data stored in the first memory 4 corresponds to a predetermined current heat storage temperature data R _i-1 and recording according to the temperature around the thermal head 9 measured by the temperature sensor 10 such as a thermistor. The output data of the AND gate 7 related to the presence / absence is used as an address and read as the next heat storage temperature data R _i . The heat storage temperature data R _i read from the first memory 4 is temporarily stored in the second memory 2 via the latch 5. Then, the heat storage temperature data R _i temporarily stored in the second memory 2 is read out as the above-mentioned current heat storage temperature data R _i-1, and is added to the first memory 4 as an address via the latch 3. Together with this, it is applied to one input terminal of the comparator 7. The preset temperature data SD is added to the other input terminal of the comparator 7. The output signal of the comparator 7 is applied to the other input terminal of the AND gate 7. The output data O _i of the AND gate 7 is applied as an address to the first memory 4 as described above, and is also applied as a drive signal to the heating element of the thermal head 9. Reference numeral 11 is a thermal recording paper, which is sent by a motor 12 at a predetermined speed. A timing control circuit 8 outputs a control signal for controlling the operation of each unit. In FIG. 4, a thick line indicates the flow of heat storage temperature data, and a broken line indicates the flow of various control signals.

FIG. 5 is a block diagram showing an example of a drive circuit for the thermal head 9, and FIG. 6 is a timing chart showing an example of operation when the circuit of FIG. 5 does not perform thermal history control. Data of m dots for one line shown in (a) output from the AND gate 7 are sequentially stored in the shift register 13 according to m clocks CLK shown in (b). When one line of data is stored in the shift register 13,
It is latched in the latch 14 by the latch pulse LAT shown in (c). The output data of these latches 14 is applied to one input terminal of each NAND gate 15. The enable signal E shown in (d) is applied to the other input terminal of the NAND gate 15.
N ′ is commonly added via the inverter 16.
It should be noted that the dash “′” indicates that it operates in negative logic. The output terminal of the NAND gate 15 is connected to one end of a heating element 17 that constitutes a thermal head,
The positive terminal of the DC power supply 18 is commonly connected to the other end of the.

In such a configuration, the enable signal
During t ₀ when EN ′ is at the L level, a drive current flows from the DC power supply 18 to the heating element 17, and recording is performed based on the recording data of one line. However, in the driving method of FIG. 6, the application time of the driving pulse per line is only t ₀ , and the thermal history control cannot be performed.

Therefore, in the prior application, for example, as shown in the timing chart of FIG. 7, the data DATA of m dots is transferred to the thermal head 9 four times, and the enable signal EN ′ is applied four times to record one line. . Here, the single transmission of each data DATA is the same as in FIG. 6, but the pulse width t ₀ ′ of the enable signal EN ′ is set to 1/4 of the pulse width t ₀ in FIG. That is, the energy applied to the heating element 5 by one driving is 1/4 of that in the case of FIG.
Since one line is recorded by sending A and the enable signal EN ', the sending of the recording paper 11 is also synchronized with this sequence, and the first one step of the four times of data transfer corresponds to one step of FIG. Step feed with the same feed amount.

By thus recording one line by data transfer four times, the pattern of the drive pulse applied to the heating element 5 is 15 as shown in FIG. 8 depending on the method of taking the data d _{1 to} d ₄ each time. It will be one of the streets (2 ⁴ -1 = 15). That is, the heating element 5 is driven and controlled according to the accumulated heat temperature, and as a result, driven according to any of these 15 patterns.

It should be noted that although FIG. 8 has been described as recording one line by sending the data DATA and the enable signal EN ′ four times, it may be n times (n is an integer of 2 or more), In the case of n times, there are 2 ⁿ -1 driving patterns. Details of such heat storage control will be described. The print data stored in the address Ax of the line buffer 1 corresponds to the mxth dot in the main scanning direction to be printed as shown in FIG. 9, and when this data is “1”, the mxth dot is printed. To record.

The timing control circuit 8 sends the address A _k to the second memory 2 which temporarily stores the heat storage temperature data at the k-th clock of the internal clock CLK shown in (a) of the timing chart of FIG. As a result, the second memory 2 outputs the heat storage temperature data R _i−1 , _k corresponding to the mk-th heating element as shown in FIG. In the k + 1 cycle of the internal clock CLK, the clock
As the CLK rises, the latch 3 latches the heat storage temperature data R _i-1 , _k as shown in FIG. The heat storage temperature data R _i−1 , _k latched by the latch 3 is applied to the comparator 7 and compared with the initially set temperature data SD.
These heat storage temperature data R _i-1 , _k and temperature data
SD is quantized into a plurality of s bits. The comparator 7 is
For example, if the temperature data SD is set to 200 ° C. and the heat storage temperature data R _i−1 , _k is 100 ° C., “1” is output to the AND gate 7, and the temperature data SD is set to 200 ° C. If the heat storage temperature data R _i−1 , _k is 250 ° C., “0” is output to the AND gate 7.

In this k + 1 clock cycle, the original data d _k corresponding to the kth dot is read from the line buffer 1 to the AND gate 7 and is output as the output data of the comparator 7 as shown in (f). Is ANDed. The output data O _k of the AND gate 7 is added to the heating element 5 of the thermal head 9 as data to be actually recorded. That is, the heating element 5 of the thermal head 9 is in a recording state because the recording data d _k is “1” and the heat storage temperature data R _i−1 , _k.
Is only lower than the temperature data SD.

In the k + 1 cycle, the following control is performed simultaneously with the above process. That is, the heat storage temperature data R
_i−1 , _k and the output data O _k of the AND gate 7 are input to the first memory 4 as addresses. Here, the comparator 7
Since the AND gate 7 can be composed of a high speed gate element, the settling of the output data O _k of the AND gate 7 is a few 1
It becomes about 0 ns, and if the clock cycle is several 100 ns, the data reading from the first memory 4 can be completed within one clock.

The first memory 4 outputs the following heat storage temperature data R _i , _k as shown in (d) according to the addresses R _i-1 , _k and O _k . For example, the heat storage temperature data R _i-1 , _k
When 100 ° C., O _k is 1 in the case when the heat storage temperature data R _i, and outputs the 180 ° C.-bit data as _k, O _k is 0 in case if regenerative temperature data R _i, the bit data of the 50 ° C. as _k Output.

In the k + 2 cycle, the latch 5 latches the heat storage temperature data R _i , _k output from the memory 4 at the rise of the clock CLK in the k + 2 cycle as shown in (e).
The data latched by the latch 5 is added to the other port of the memory 2 and written in the address A _k . The series of operations from to is pipeline-processed in parallel, and the heat storage temperature data R _i−1 , _{k + 1} is read from the memory 2 in the clock cycle of _{k + 1} .

The thermal head 9 receives m recording data by executing the operations 1 to m m times. After the transfer of m data, the timing control circuit 8 activates the latch pulse LAT as shown in FIG. 7C, and activates the enable signal EN ′ once for the time t ′ as shown in FIG. 7D. Then, a drive current is passed through the heating element 5. The data transfer of m pieces and the transmission of the latch pulse LAT and the enable signal EN ′ are repeated a plurality of times. FIG. 7 shows an example of repeating four times. It should be noted that the data in the line buffer 1 is not updated during these repeated operations a plurality of times, but is updated in synchronization with this cycle with a plurality of repeated operations as one cycle.

Next, the heat storage temperature data setting of the memory 4 will be described. The temperature change of the heating element 5 of the thermal head 9 can be simulated by the amplitude and pulse width of the drive pulse with the initial temperature T ₀ as a reference. That is,
The structure of the thermal head 9 is known, and the physical property constants of each part are also known. From these, the thermal response of the thermal head 9 can be modeled and described using a heat conduction equation. By giving an initial temperature as an initial condition to this heat conduction equation and giving the amplitude and pulse width of the drive pulse as input energy to the system, the temperature of the heating element 5 of the thermal head 9 at each time can be simulated by numerical calculation. Since the heat conduction equation is non-linear, numerical calculation by a computer is performed using the one-dimensional finite element method, and the temperature state after data transfer is simulated and predicted and tabulated in the memory 4.

In the configuration shown in FIG. 4, the transfer period of m dot data to the thermal head 9 and the enable signal EN are used.
Since the pulse width of ′ is constant, the temperature after data transfer can be predicted by simulation if the initial temperature T ₀ is known. FIG. 11 is an explanatory diagram of such a simulation state, (a) shows a temperature change state when a drive pulse is applied for time t ′, and (b) shows a temperature change state when a drive pulse is not added. ing.

The initial temperature T ₀ is used as a parameter in the memory 4, and the temperature T ′ after the transfer cycle with and without the drive pulse is tabulated as data in advance. That is, the heat storage temperature data R _i−1 , _k is used as the initial temperature T _0.
By inputting the output signal O _k of the AND gate 7 to the address of the memory 4 as an ON / OFF signal of the driving pulse, the memory 4 outputs the temperature T ′ after the transfer cycle as bit data R _i , _k. become.

By storing such data in the memory 4, the heat storage temperature is successively calculated. Then, the comparator 6 compares the heat storage temperature data with the set temperature one by one,
As a result, a pulse train suitable for past heat storage temperature data is selected from the plurality of pulse trains in FIG.
Highly accurate heat history control is performed. In the above description, the temperature control is an open loop. Moreover, an error occurs in the simulation data depending on the ambient temperature. Therefore, the temperature sensor 10 is used for the thermal head 9
Measure the temperature of the heat sink of the
To the memory 4 and the data in the memory 4 is switched. Further, when the temperature of the heat dissipation plate of the thermal head 9 rises too much, the drive pulse is cut so as to prevent the temperature from further rising.

The pulse width of the drive pulse may be variable in order to improve the recording quality according to changes in the chart feed speed and the ambient temperature. In this case, the data read from the memory 4 may be changed by switching the address of the memory 4 according to the chart feed speed and the ambient temperature. Further, by updating the data in the line buffer 1 in synchronization with the data transfer cycle, it is possible to record the change state of the measurement signal in detail.

With such a configuration, basically, the application pattern of the drive pulse of the thermal head can be finely set by a simple combination of one read-only memory and the comparator, and the recording quality can be improved.

[0024]

However, in such an apparatus of the prior application, if the heat history control circuit fails for some reason, the heat history control is lost, and in the worst case, the thermal head may be burned out. is there. The present invention focuses on such a point, and an object thereof is to provide a thermal recording apparatus having a self-diagnosis function of automatically determining whether or not the thermal history control circuit is normal. .

[0025]

According to the present invention for solving such a problem, a plurality of heating elements constituting a thermal head are selectively driven to generate heat, and recording is performed on a recording target based on the generated heat. In the thermal recording device, a thermal history control circuit that reads out the current estimated temperature from the temperature history memory every time image data is added, compares it with the set temperature, and outputs a drive pulse for selectively driving the heating elements, and , A test image data generation circuit for inputting test image data to the heat history control circuit, a counter for counting drive pulses output from the heat history control circuit in response to test image data input, and a count value of this counter A judgment circuit for judging whether the operation of the thermal history control circuit is good or not based on Characterized by providing.

[0026]

In the self-diagnosis of the thermal history control circuit, test image data is input from the test image data generation circuit to the thermal history control circuit, and the thermal head drive power is turned off. The counter counts the drive pulses output from the thermal history control circuit in response to the input of the test image data, and the determination circuit compares the count result with a reference value to determine whether the operation of the thermal history control circuit is good or bad.

By performing such self-diagnosis of the thermal history control circuit prior to actual measurement each time the power is turned on, the thermal head can be prevented from burning.

[0028]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention, and the portions common to FIG. 4 are designated by the same reference numerals. In the figure, reference numeral 21 is a heat history control circuit, and as described above, the temperature history memory 4 is added every time image data is added.
Then, the current estimated temperature is read out and compared with the set temperature, and a drive pulse for selectively driving the heating elements of the thermal head 9 is output. Reference numeral 22 denotes a test image data generation circuit, which inputs test image data to the heat history control circuit 21. A counter 23 counts drive pulses output from the thermal history control circuit 21 in response to test image data input. A timing signal is added from the timing control circuit 8 to the counter 23. 24
Is a comparator, the count value of the counter 23 is input to one input terminal, and the reference setting value corresponding to the test image data output from the test image data generating circuit 22 is input to the other input terminal via the CPU 25. Has been entered. The CPU 25 controls the operation of the entire apparatus, and FIG. 1 shows only the self-diagnosis system of the thermal history control circuit 21. A thermal head drive power source 26 selectively supplies drive power to the thermal head 9 via the switch 27.

The operation of FIG. 1 will be described with reference to the timing chart of FIG. The following series of operations for self-diagnosis of the heat history control circuit 21 are executed every time the power is turned on, for example, under the control of the CPU 25. To execute the self-diagnosis, the switch 27 is turned off, and the thermal head 9 and the driving power supply 26 are disconnected. In this state, test image data is input from the test image data generation circuit 22 to the thermal history control circuit 21 over a period of several lines as indicated by a and b. Here, the image data shown in b is a data string individually corresponding to each heating element of the thermal head 9, and in FIG. 2, so-called “solid black” in which printing is performed by heating all the heating elements of one line. The example of image data is shown.

The counter 23 counts the number of drive pulses of the thermal head output from the thermal history control circuit 21 during the period in which the image data is input (for the period of 6 lines shown by A in FIG. 2). Output to the comparator 24. d1 to d3 show examples of drive pulses output from the thermal history control circuit 21. d1 is the heat history control circuit 21
Is an example of the drive pulse in the case of normal operation, and shows a state in which the drive pulse is appropriately thinned in consideration of the heat storage effect of the heating element. Count value B of the counter 23 in this case
Is n ×, where n is the number of heating elements of the thermal head 9.
4. On the other hand, if the thermal history control circuit 21 is defective, the drive pulse becomes d2 or d3, and the count value B is different. d2 shows an example in which no thinning is performed, and d3 shows an example in which no drive pulse is output. The count value B is compared with the reference set value by the comparator 24. As the reference set value, a count value when the thermal history control circuit 21 is normally operating is set in advance.

When the reference set value and the count value B match, the comparator 24 judges that the heat history control circuit 21 is operating normally, and when they do not match, the heat history control circuit 21. 21 is judged not to operate normally,
These determination results are output to the CPU 25. CPU25
When the thermal history control circuit 21 is operating normally based on the determination result added from the comparator 24, the switch 27 is turned on to execute the print recording by the thermal head 9, and the thermal history control circuit 21 If is not operating normally, an alarm display indicating "abnormal" is displayed to alert the operator.

As a result, it is possible to self-diagnose the malfunction of the device due to the "abnormality" of the thermal history control circuit 21, and to enhance the reliability of the recording device. In the above embodiment, the generation circuit for outputting the image data of "solid black" is provided as the image data for the test, but it is sufficient if the operation of the thermal history control circuit 21 can be substantially confirmed. It is also possible to share the grid image data generation circuit and the like incorporated in the.

The determination circuit is not limited to the comparator, but the count value is directly input to the CPU 25, and the CPU 2
It is also possible to make a determination by software processing inside 5.

[0034]

As described above, according to the present invention,
It is possible to provide a highly reliable thermal recording device having a self-diagnosis function of automatically determining whether or not the thermal history control circuit is normal.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a timing chart illustrating the operation of FIG.

FIG. 3 is a temperature transition explanatory diagram of a heating element when heat history control is not performed.

FIG. 4 is a block diagram showing an embodiment of the device of the prior application.

FIG. 5 is a block diagram showing an example of a drive circuit of a thermal head.

FIG. 6 is a timing chart showing an example of an operation when heat history control is not performed in the circuit of FIG.

FIG. 7 is a timing chart illustrating the operation of FIG.

FIG. 8 is a pattern example diagram of drive pulses according to the timing chart of FIG. 7.

FIG. 9 is a perspective view of a main part of FIG.

FIG. 10 is a timing chart illustrating the operation of FIG.

FIG. 11 is an explanatory diagram of simulation data used in the thermal history control circuit of the prior application.

[Explanation of symbols]

 8 Timing Control Circuit 9 Thermal Head 21 Thermal History Control Circuit 22 Test Image Data Generation Circuit 23 Counter 24 Comparator 25 CPU 26 Thermal Head Drive Power Supply 27 Switch

Claims (1)

[Claims] 1. A thermal history recording apparatus for selectively driving a plurality of heating elements constituting a thermal head to generate heat and recording on a recording target based on the heat generation, a temperature history memory every time image data is added. The thermal history control circuit that reads out the current estimated temperature from the above and compares it with the set temperature, and outputs the drive pulse for selectively driving the heating elements, and input the image data for test to this thermal history control circuit A test image data generation circuit, a counter that counts drive pulses output from the heat history control circuit in response to test image data input, and a judgment that determines whether the operation of the heat history control circuit is good or bad based on the count value of this counter A thermal recording apparatus comprising a circuit and a switch for turning off a driving power source of a thermal head during a test image data input period.