JPH07250254A - Method and device for compressing signal - Google Patents

Abstract

PURPOSE:To provide a method and device for compressing signal with which the number of bits in the data of chrominance signals can be reduced, further, gradations can be made multiple, and the capacity of a data memory corresponding to this number of gradations can be decreased. CONSTITUTION:When respective input signals 101, 102 and 103 to which numbers up to the third order are applied are composed of three bits and provided with five kinds of values, the respective input signals 101, 102 and 103 are handled as quinary numeral, and the second input signal 102 is increased five-fold by a multiplier 104. Then, the first input signal 101 and an intermediate signal 105 as the multiplied result of the second input signal 102 are added to each other by an adder 106, the third input signal 103 is added to this added result, and a resultant output signal 108 of eight bits is outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal compression method and a signal compression apparatus for compressing data of an input signal to an output device of multi-value gradation.

[0002]

2. Description of the Related Art In an output device that cannot express many gradations, various methods are used to compensate for the gradations so that a visual gradation can be obtained.

The number of colors displayed on the display is 16
From 256 colors to less than natural colors. However, the narrow range (collection of pixels) on the display appears to be a mixture of the colors of each pixel when viewed from a sufficient distance, so the colors of the pixels within that range are averaged, and visually It is possible to express more colors than the gradation can be displayed on the display, and it seems that the gradation has increased. One of the applications of this principle is dithering.

FIG. 6 shows a concept of a binary dithering method used for an output device which can handle only binary values of black and white (0, 1). In FIG. 6, 301 is an input signal, 302 is a dither matrix, and 303 is an output signal. Further, the matrix of the input signal 301 and the matrix of the dither matrix 302 corresponds to one pixel of the output device, and the number in the inside is the gradation of the data in each pixel. The input signal 301 is a signal input from the input means, and can normally have gradations from 0 to the maximum number of colors limited by the software used. The dither matrix 302 is from 0 to the input signal 301.
It has a value up to the maximum gradation and has a certain pattern. The input signal 301 is compared with the dither matrix 302, and if the input signal 301 is larger in each pixel, 1 is output, and 0 is output, and an output signal 303 having only two values of 0 and 1 is obtained. This output signal 303 is
When viewed from a sufficient distance, a smooth gradation change appears.

Next, FIG. 7 shows a multi-valued dithering method. In FIG. 7, 401 is an m-bit input signal, 402 is a higher-order signal composed of higher-order n bits of the input signal 401, 40
3 is a lower signal composed of lower (mn) bits of the input signal 401, 404 is a (m-n) bit dither matrix, 405 is a dither matrix 404 and lower signal 403.
And 406, a comparison result output from the comparison device 405, 407 an addition device for the higher-level signal 402 and the comparison result 406, and 408 an output signal from the addition device 407. First, the m-bit input signal 401 is adjusted to the required number of gray levels (2 ⁿ +1), and the upper signal 402 (n bits)
And lower-order signal 403 (mn bits). For the (mn) bits of the lower signal 403, the dither matrix 404 is used to perform the binary dithering shown in FIG. 6 by the comparator 405 to obtain a 1-bit comparison result 406 (0 or 1). The adder 407 generates the output signal 408 by adding 1 bit of the comparison result 406 to n bits of the higher-order signal 402. At this time, since the higher-order signal 402 has n bits and 2 ⁿ values and the comparison result 406 is 1-bit 0 or 1, the output signal 408 is (n +
It can have (2 ⁿ +1) values in 1) bits. Therefore, this dithering is referred to as (2 ⁿ +1) gradation dithering. Further, in dithering, since (m−n) -bit data of the lower signal 403 becomes 1 bit of the comparison result 406, (n +) is applied to the m-bit input signal 401.
1) The data is compressed to obtain a bit output signal.

The output signal obtained as described above is 8
It is handled in units of integer multiples (8, 16, 32 bits, etc.) of bits (generally expressing 8 bits as 1 byte).
FIG. 8 shows a conventional example in which a color information signal obtained by dithering is output to an output device. Here, the color information obtained by dithering is red, green, blue (hereinafter, RGB
It is decomposed into. 501,50 in the figure
Reference numerals 2, 503 denote R, G, B input signals,
Reference numeral 504 indicates an output signal. In the conventional method, the input signal 5
01, 502, and 503 are given by 2 bits each, and a total of 6 bits of output signal 504 is given to the output device. That is, by using three types of 2-bit signals, the output signal is a signal in one byte, and gradation expression is performed using gradations of each of the RGB three values.

As another method, it is conceivable to use an input signal of 3 bits or more for each of RGB and generate an output signal extending over 2 bytes or more. This requires a large amount of memory, requires two or more accesses in the case of an 8-bit data bus, and has the disadvantage of including a large amount of wasted memory depending on the number of signals.

[0008]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention As shown above,
Conventionally, even for an output device capable of multi-valued gradation expression and having a large number of gradations, in order to reduce the number of bits of data for a color signal, the gradations of three types of RGB color signals are dithered. It was represented by a total of 6 bits of 2 bits (3 values). That is, the data of the color signal is converted into the data within 1 byte, and the gradation expression is performed using a small number of gradations (3 values of 2 bits for each color).

On the other hand, when it is attempted to give a color signal to the multi-value gradation output device as data of 3 bits or more, which is larger than in the conventional case, the data exceeds 1 byte, and However, there is a problem in that it requires twice as much time to access and requires a larger amount of memory for color signal data.

The present invention solves the above-mentioned problems, and provides an output device capable of multi-value gradation expression with a color signal represented by gradation having a large number of bits corresponding to the output device. Signal compression that can be given after reducing the number of bits of data, rich gradation expression can be performed in the output device, and the amount of memory for color signal data with respect to the number of gradations can be reduced compared to the conventional method. It is an object to provide a method and a signal compression device.

[0011]

In order to achieve the above object, a signal compression apparatus based on the signal compression method of the present invention comprises:
m (m = positive integer) bit signals are input respectively,
a plurality of input means given numbers up to q (q = a positive integer), and the number of types of the m-bit signal is n (n = a positive integer, n <2 ^m ) Corresponding to each input means of the input means, multiplying means for multiplying the input m-bit signal by n ^p (p = q−1), and output from the multiplying means corresponding to each input means. And adding means for adding each of the generated signals, and each of the input means is configured to handle the m-bit signal input to each of the input means as an n-ary number.

[0012]

According to the above configuration, each signal of the input signals given numbers up to q (q = positive integer) is composed of m bits and the number of types is n (n = positive integer, n <2. ^m ), treat each signal as an n-ary number with respect to the input signal,
For each signal of the input signal, this signal is multiplied by n ^p (p = q−1) corresponding to the signal number. The multiplication result of each signal of the input signal is added and output. As described above, the number of bits of the input signal is compressed and output as the output signal.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A signal compression apparatus based on a signal compression method according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a signal compression apparatus based on the signal compression method of this embodiment. 101, 102, 1 in the figure
Reference numeral 03 designates input terminals A, B, C as input means, respectively.
Input signals (R signal, G signal, B signal) input to 1
Reference numeral 04 is a multiplication device as multiplication means, and 105 is a multiplication device 1.
The intermediate signal output from 04, 106 is an adding device as an adding unit, 107 is an intermediate signal output from the adding device 106, and 108 is a final output signal. Input signals (R signal, G signal, B signal) 101, 102, 103
Is the signal after the dithering shown in FIG.
As shown in the conventional example, when there are (n + 1) bits, (2 ⁿ +
1) Can have a value. That is, the input signal 101,
Since 102 and 103 use 3 bits in which the number of signals is increased from the conventional one, they have 5 values from 0 to 4.

Here, it is used that each input signal of R signal, G signal, and B signal has only five values. Normally, a 3-bit signal can have 8 values from 0 to 7, so there is waste in handling data having only 5 values from 0 to 4.

Therefore, the memory amount can be reduced by considering the data as a quinary system instead of an octal system. That is, in the embodiment shown in FIG.
Considering 01 as the first digit of the quinary system and the input signal 102 as the second digit of the quinary system, the input signal 102 is multiplied by 5 (× 5) using the multiplication device 104. The internal configuration of the multiplication device 104 is shown in FIG.

In FIG. 2, 201 is an input signal to the multiplication device 104 (input signal 102 in FIG. 1), 202 is a shift device, 203 is an intermediate signal output from the shift device 202, 204 is an addition device, and 205 is multiplication. The output signal from the device 104 (the intermediate signal 105 in FIG. 1) is shown. In the shift device 202, the input signal 201 (5 of 0, 1, 2, 3, 4
By shifting the value) by 2 bits (2 bit shift), an intermediate signal 203 (five values of 0, 4, 8, 12, 16) obtained by quadrupling (× 4) the input signal 201 is obtained. Next, the adder 204 adds the input signal 201 to the intermediate signal 203 and outputs the output signal 2 obtained by multiplying the input signal 201 by five.
05 (5 values of 0, 5, 10, 15, 20) is obtained. In this way, the intermediate signal 105 of FIG. 1 is obtained.

In FIG. 1, the adder 106 adds the input signal 101 to the intermediate signal 105 and outputs the intermediate signal 1
I get 07. The combination of the intermediate signals 107 obtained here is shown in FIG. In FIG. 3, the vertical axis represents the input signal 101, the horizontal upper row represents the input signal 102, and the horizontal lower row represents the intermediate signal 105. As can be seen here, the intermediate signal 107 is 0 to 2
It becomes an integer value up to 4, and all combinations of the input signal 101 and the input signal 102 are represented by 5 bits (0 to 32). This 5-bit intermediate signal 107 and 3-bit input signal 103 are combined to make 8 bits (1 byte).
Becomes

By the above method, the number of bits of the input signal can be compressed and output as the output signal, and even if the color signal data has a larger number of bits than the conventional one, the data within 8 bits (1 byte). Then, it can be applied to an output device having multi-value gradation. Therefore, rich gradation expression can be performed in the output device. Further, the amount of memory for color signal data with respect to the number of gradations can be reduced as compared with the conventional case.

In the above embodiment, 8 bits (1 byte)
However, as shown in FIG. 4, it is also possible to implement a development type obtained by developing the above embodiment. FIG. 4 is a circuit diagram when the signal compression devices are assembled in series. 701 to 704 in FIG. 4 are the first to q
Th input signal, 705 to 707 are multiplication devices corresponding to the respective input signals, 708 to 710 are addition devices, and 711 is an output signal.

Each of the input signals 701 to 704 has a data width of m bits, and the data used is m
The number of types (n types) is less than the number of all types that can be represented by the data width of bits. Also, the multiplication device 7
From 05, the multiplication device 707 multiplies each input signal by the power of n squared by one less than the number of the input signal. Here, when q−1 is p, the multiplication device 707 corresponding to the qth input signal 704 is
4 becomes n ^p times (× n ^p ). as a result,
The input signal 702 is multiplied by n in the multiplier 705 (× n ¹ = ×
Since n) the calculated result is an input to the adder 709, the above-mentioned calculation is performed using this result and the input signal 703, the multiplier 706, and the adder 709. That is, the output signal 711 is obtained with the input signal 701 as the first digit of the n-ary number, the input signal 702 as the second digit of the n-ary number, and the subsequent input signal 704 as the q-th digit of the n-ary number.

Further, even if the structure shown in FIG.
The same can be done with. FIG. 5 is a circuit diagram when the signal compression devices are assembled in parallel. 801 to 804 in FIG.
Are the 1st to qth input signals, 805 to 8
Reference numeral 07 denotes a multiplication device corresponding to each input signal, 808
Is an adder, and 809 is an output signal. Input signal 801
To input signal 804 has the same format as input signal 701 to input signal 704 of FIG. Also, the multiplication device 805
From multipliers 807 to multipliers 705 to 70 of FIG.
The same calculation as in 7 is performed. As a result, the input signal 802 is multiplied by n (× n ¹ = × n) in the multiplier 805, and the input signal 8
03 is multiplied by n ² (× n ² ) by the multiplier 806, and the input signal 804 is multiplied by n ^P (× n ^p ) by the multiplier 807.
All of these calculation results are added by the adder 808 to obtain the output signal 809. Also in this embodiment, similarly to the output signal 711 in FIG. 4, the input signal 801 is the first digit of the n-ary number, the input signal 802 is the second digit of the n-ary number, and the input signal 804 is the q-th digit of the n-ary number. The output signal 809 is obtained.

[0023]

As described above, according to the present invention, q (q =
Each of the input signals given numbers up to a positive integer) is composed of m bits and the number of types is n (n = a positive integer, n
<2 ^m ), each signal is n
It is treated as a base number, and the multiplication means corresponds to each signal of the input signal by n ^p corresponding to the signal number.
It can be multiplied by (p = q-1). Then, the multiplication result of each signal of the input signal can be added and output. As described above, the number of bits of the input signal can be compressed and output as the output signal.

Therefore, a color signal represented by a gradation having a large number of bits corresponding to this output device is given to an output device capable of expressing a multi-value gradation after reducing the number of bits of this data. be able to. as a result,
Rich gradation expression is possible in the output device.

Further, the amount of memory for color signal data with respect to the number of gradations can be reduced as compared with the conventional one.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a signal compression device according to an embodiment of the present invention.

FIG. 2 is an internal configuration diagram of a multiplication device of the same embodiment.

FIG. 3 is an operation explanatory diagram of the adding device of the embodiment.

FIG. 4 is a block diagram of a signal compression device according to another embodiment.

FIG. 5 is a block diagram of a signal compression device according to still another embodiment.

FIG. 6 is a conceptual diagram of a binary dithering method.

FIG. 7 is a block diagram of a circuit based on a multivalued dithering method.

FIG. 8 is an explanatory diagram of a conventional RGB signal output method.

[Explanation of symbols]

 104 Multiplier 106 Adder A, B, C input terminals

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location // G06T 5/00 G06F 15/68 320 A

Claims (2)

[Claims] 1. A signal composed of m (m = positive integer) bits, wherein the m bits are for an input signal composed of a plurality of signals given numbers up to q (q = positive integer). The number of types of signals configured by is n (n = positive integer, n <2 ^m ).
, Each signal of the input signal is treated as an n-ary number, each signal of the input signal is multiplied by n ^p (p = q−1), and the result of the multiplication is calculated. And a signal compression method for outputting an output signal based on the signal obtained by the addition. 2. A plurality of input means to which signals of m (m = positive integer) bits are respectively input and are given numbers up to q (q = positive integer), and the number of kinds of the m-bit signals. Is n (n = positive integer, n <2 ^m ), the ^m input corresponding to each input means of the plurality of input means is input.
Each of the input means has multiplication means for multiplying the bit signal by n ^p (p = q−1) and addition means for adding each signal output from the multiplication means corresponding to each input means. A signal compression device, wherein the means is configured to handle the m-bit signal input to each of the input means as an n-ary number.