JPH07249290A - Memory device and its control method - Google Patents

Abstract

PURPOSE:To perform operation at a high speed by making the potential of only the left node of a memory cell referable making a left word line only a high potential or making the potential of only the right node of a memory cell referable making a right word line only a high potential. CONSTITUTION:In this memory cell C, potentials of the left node NL and the right node NR both are made 'H', further, only either potential of the both can be made 'H'. In this case, the potential of the left word line WL and the potential of the right word line WR can be controlled independently. Then, when the potential of the right word line WR is made 'L' and only the potential of the left word line WL is controlled to 'H', the potential of the left node NL can be transmitted to the left bit line BL without affecting to the potential of the right bit line BR. Also, when the potential of the left word line WL is made 'L' and only the potential of the right word line WR is controlled to 'H', the potential of the right node NR can be transmitted to the right bit line BR without affecting to the potential of the left bit line BL.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improved memory cell of a static random access memory (hereinafter referred to as SRAM) and a memory device using the improved memory cell, and more specifically, to a logical operation function. A memory device having

[0002]

Various improvements have been made to SRAMs, but the basic structure of memory cells has not changed significantly. An example of the basic structure of a SRAM memory cell is WILLIAM N. CAR.
R), Jack Peas Maze (JACK P. MA
ISE) “Moss / LSII Design and
Application "(" MOS / LSI Design
and Application "), page 211, Figure 7.12. Referring to FIG. 21, the conventional memory cell has transistors T1 and T1 for storage.
2 and T3 which is the gate transistor of T1 and T2
And T4 and loads TL1 and TL2. The gates of the gate transistors T3 and T4 are connected to the word selection signal line.

In such a memory cell, the gate transistors T3 and T4 are simultaneously controlled via the word selection signal line. For example, when reading data from this memory cell, the potential of the word selection signal line is set to a high level. As a result, the potentials of Q1 and Q2 are transmitted to the bit lines (1) bit and (0) bit. When writing data to this memory cell, the bit lines (1) bit and (0) bit are set to a predetermined potential and the word selection signal line is set to a high level. As a result, the potentials of the bit lines (1) bit and (0) bit are held in the transistors T1 and T2.

Further, as an approach to overcome the von Neumann bottleneck in a conventional computer and achieve massively parallel arithmetic, research has been conducted on a functional memory in which a memory element has an arithmetic function. The functional memory architecture is an architecture that integrates a memory function and a calculation function by introducing a logical operation function into the memory. A functional memory that is one of the conventional techniques of such a functional memory and executes an exclusive OR operation in the memory is known as a content addressable memory (hereinafter referred to as CAM). An example of such a CAM memory cell is WILLNAM N. CARR,
Jack Peas Maze
Written "MOS / LS Design and Application"("MOS / LSI Design and application"
Application ”) page 224, FIG. 7.20.

Referring to FIG. 22, a memory cell forming a conventional CAM includes transistors T1, T2, T3, T4, TL1 and TL2, which form the basic memory cell described above, and an exclusive OR element. Constituting T5, T
6, T7 and T8. In this memory cell, when a predetermined potential is applied to the bit lines B (0) and B (1), the exclusive OR of the logical value corresponding to this potential and the logical values stored in the transistors T1 and T2 is obtained. It is calculated and sent to the signal line SUM.

[0006]

However, in the above-described conventional SRAM memory cell, the gate transistors T3 and T4 are simultaneously controlled by one word selection signal line, and the bit lines (1) bit and ( 0) cannot be controlled independently. In addition, in the conventional SRAM memory cell, the power supply voltage Vc
A constant voltage is supplied to the c and ground voltages, and the voltages are not changed. Further, due to the above-mentioned structural restriction, there is a problem that operations that can be executed by this conventional memory cell are limited, and operations other than read / write operations cannot be executed.

Further, in the above-mentioned CAM memory, the data to be ORed with the storage value of the memory cell is supplied from the outside by the bit lines B (0) and B (1), and the logic The result of the sum operation is supplied to the outside through the signal line SUM. Therefore, in this CAM, when the storage value of the first memory cell and the storage value of the second memory cell are calculated and stored in the third memory cell, the storage value of the first memory cell is And the second
There is a problem in that the calculation result with the memory value of the memory cell must be temporarily stored outside and then written again in the third memory cell.

Further, in this CAM memory, it is necessary to provide an exclusive OR element in each cell. Therefore 1000
In a CAM memory having a memory cell array of 1000 columns, it is necessary to incorporate 1,000,000 exclusive OR elements. Therefore, there is a problem that the number of elements increases and the degree of integration decreases.

Further, in this CAM memory, operations other than the operation type of the logical operation element provided in advance in each cell cannot be performed. Therefore, in order to execute many kinds of calculations, it is necessary to install many kinds of calculation elements in each cell, and in this respect as well, an increase in the number of elements and a decrease in the degree of integration become problems.

[0010]

The memory cell of the present invention comprises:
In order to solve the above problems, a transistor that receives a left word line at its gate to connect the left bit line and a memory cell and a right word line that is controlled independently of the left word line receive a right bit line. And a transistor connecting the memory cell and a power supply terminal for receiving a power supply voltage from another circuit,
A ground terminal for receiving a ground voltage from another circuit.

In order to solve the above-mentioned problems, in the memory device of the present invention, one row in the horizontal direction is connected to the same left word line, right word line, word power supply line and word ground line, and one row in the vertical direction. Are connected to the same left bit line and right bit line, respectively, a bit line control circuit for controlling the bit lines connected to the memory cells, and one in each lateral row of the memory cells. And a word line control circuit that controls the potentials of the left word line, the right word line, the word power supply line, and the word ground line in each column.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1, a memory cell C according to a first embodiment of the present invention comprises an nMOSFET 1 for storing data.
And 2, drain loads 5 and 6 of FETs 1 and 2, and nMOSFETs 3 and 4 for gates which are on / off controlled by left and right word lines WL and WR.

The drains of the FETs 1 and 2 for storing data are connected to the word power supply line W via drain loads 5 and 6.
Connected to V. On the other hand, the sources of FETs 1 and 2 are
It is connected to the word ground line WG. By applying the power supply voltage Vcc to the word power supply line WV and the ground voltage GND to the word ground line WG, the memory cell C becomes a state in which data can be stored. here,
That the memory cell C is in a state capable of storing data,
It is assumed that "memory cell C is activated".

In activated memory cell C, stored data is represented as the potentials of left node NL and right node NR. Here, when the potential of the left node NL is high level “H” = Vcc and the potential of the right node NR is low level “L” = GND, “1” is stored in the memory cell C. Conversely, when the potential of the left node NL is “L” and the potential of the right node NR is “H”, “0” is stored in the memory cell C.

When writing data to the memory cell C,
The potentials of the left bit line BL and the right bit line BR are set to potentials representing write data. After a predetermined potential is applied to the left bit line BL and the right bit line BR, the potentials of the left word line WL and the right word line WR are both set to "H". At this time, the potential of the left bit line BL changes to the right bit line BR.
If it is higher than the potential of, the memory cell C is written with "1". On the contrary, the potential of the right bit line BR is equal to that of the left bit line BL.
If the potential is higher than the potential of, the memory cell C is written with "0". This operation is no different from the normal SRAM write operation.

When reading the data written in the memory cell C, the potentials of the left word line WL and the right word line WR are both controlled to "H". When the potentials of the left word line WL and the right word line WR are both set to "H", the left node N
The potentials of L and right node NR are transmitted to left bit line BL and right bit line BR, respectively. Then, by referring to the potentials transmitted to the left bit line BL and the right bit line BR, the content of the data stored in the memory cell C can be determined. This operation is a normal general-purpose S
There is no difference from the case of the RAM read operation.

Further, in the memory cell C of this embodiment, it is possible to refer to only the potential of either the left node NL or the right node NR. At this time, the potential of the left word line WL and the potential of the right word line WR are independently controlled.
If the potential of the right word line WR is set to “L” and the potential of the left word line WL is controlled to “H”, the potential of the left node NL is changed to the left bit line BL without affecting the potential of the right bit line BR. Can be transmitted to. Further, the potential of the left word line WL is set to “L”, and only the potential of the right word line WR is set to “H”.
If controlled to, the potential of the right node NR can be transmitted to the right bit line BR without affecting the potential of the left bit line BL.

Further, in the memory cell C of this embodiment, the following operations can be performed by controlling the potentials of the word ground line WG and the word power supply line WV.

First, by applying an equal potential to the word power supply line WV and the word ground line WG, the data held in the memory cell C is erased and the memory cell C is initialized. Here, applying the same voltage to the word power supply line WV and the word ground line WG,
It is supposed to "inactivate the memory cell C". Secondly, by displacing the power supply voltage applied to the word power supply line WV and the ground voltage applied to the word ground line WG by a certain amount, the potential of the left node NL and the right node are retained while the stored data is saved. The NR potential can be changed. At this time, the displacement amounts of the potentials of the left node NL and the right node NR are equal to the displacement amounts of the power supply voltage and the ground voltage. For example, the potential of the left node NL is “H”
= Vcc and the potential of the right node NR is “L” = GND, if the word power line WV is set to 1.5 Vcc and the word ground line WG is set to 0.5 Vcc, the potential of the left node NL is set to 1.5 Vcc and the right node is set to 1.5 Vcc. NR potential is 0.5 Vcc
To rise respectively.

Next, the memory device according to the present invention will be described. In the memory device of the present invention, the number of columns and the number of rows of the memory cell group are not limited, and a memory cell group of, for example, 256 rows and 256 columns can be realized. However, in order to facilitate understanding, the memory cell group has three rows. The case of two columns will be described.

Referring to FIG. 2, the memory device according to the present invention includes six memory cells C11 and C2 for storing data.
1, C31, C12, C22 and C32, and word line control circuits 40, 50 and 60 for controlling the right word line WR, the left word line WL, the word power supply line WV and the word ground line WG of each memory cell in units of rows. , Word address decoders 12, 22 for controlling each word line control circuit,
32 and a bit line control circuit 7 for controlling the right bit line BR and the left bit line BL connected to each memory cell in column units.
Including 0 and.

The memory cells C11 to C32 of this embodiment are
It is the same as the memory cell C described in the first embodiment. The memory cells C11 to C32 are arranged in a matrix of 3 rows by 2 columns and form a memory cell array CA.

Left word line W of memory cells C11 to C32
The potentials of L, the right word line WR, the word power supply line WV, and the word ground line WG are controlled in units of rows. For example,
In the first row of the memory cell array CA, the left word line WL11 of the memory cell C11 and the left word line WL12 of the memory cell C12 are connected to one left word line WL1. Similarly, the memory cell C11 and the memory cell C
12 right word lines WR, word power supply lines WV and word ground lines WG
It is connected to V1 and the word ground line WG1.

In order to control the memory cell array CA,
Word addresses WA10, WA20 and WA30, bit address BA, control signal CS, and operation mode signal AM are externally supplied.

The word addresses WA10, WA20, and WA30 are assigned to the signal line 10, the signal line 20, and the signal line 3, respectively.
It is a 2-bit signal transmitted via 0 and designates a row position in the memory cell array CA. In this embodiment, when the word address is "00", the first row is set to "0".
When it is "1", the second row is designated, and when it is "10", the third row is designated.

The bit address BA is a 1-bit signal transmitted via the signal line 71, and is a memory cell array CA.
Specify the column position in. In this embodiment, the first column is designated when the bit address BA is "0", and the second column is designated when the bit address BA is "1".

The operation mode signal AM is a 3-bit signal transmitted via the signal line 73, and is a memory cell array CA.
This is a signal for designating the type of logical operation to be executed by. In this embodiment, when the operation mode signal AM is "000", the normal mode is used, and when it is "001", the inversion mode is used.
The logical sum mode is designated when "010", the reverse shift mode is designated when "011", and the ready mode is designated when "100".

The control signal CS is a 1-bit signal transmitted through the signal line 72 and specifies either a read operation or a write operation. In this embodiment, a read operation is designated when the control signal CS is "0", and a write operation is designated when the control signal CS is "1".

Bit lines BL1 to BL1 of the memory cell array CA
The bit control circuit 70 controls the potential of BR2 and the connection between the bit lines. Bit control circuit 70
Are controlled by bit address BA, control signal CS, and operation mode signal AM. Bit control circuit 70
Has the following two functions. The first is a function as a column address decoder that performs a read operation and a write operation on the column designated by the bit address BA. The second is a function of connecting predetermined bit lines to each other by the bit address BA and the operation mode signal AM.

Referring to FIG. 9, bit control circuit 70
Are transfer gates 731, 732, 733, 7
34, 741, 742 and 743, an input / output circuit (hereinafter, I / O circuit) 711, and a bit line selection circuit 72.
Including 1 and.

Referring to FIG. 10, the transfer gate TG is composed of two FETs. The transfer gate TG, when the potential of the terminal TGC is “H”,
The terminal TG1 and the terminal TG2 are electrically connected, and the terminal TG
When the potential of C is "L", the terminals TG1 and TG2 are electrically insulated.

Referring again to FIG. 9, the I / O circuit 711
Signal lines 712 and 7 according to the instruction of the control signal CS.
A read / write operation is performed on 13. The I / O circuit 711 omits the function of selecting a bit line from the normal SRAM column address decoder, and can be easily realized by slightly modifying the conventional column address decoder.

Bit line selection circuit 721 receives connection instruction signal lines 722-7 based on bit address BA and operation mode signal AM received via signal lines 71 and 73.
Apply a predetermined potential to 25 and transfer gate 7
31 to 743 are controlled. The relationship between the input and output of the bit line selection circuit 721 is shown in the truth table of FIG. In the table of FIG. 11, “*” indicates that either “H” or “L” may be used. A logic circuit having such an input / output relationship can be easily configured by combining logic elements.

Referring again to FIG. 9, transfer gates 731-734 have connection instruction signals 722 and 72.
3, the signal lines 712 and 713 and the bit line B
Connect L1 to BR2. Transfer gate 74
1 to 743 connect the bit lines to each other in accordance with the connection instruction signals 724 and 725.

Referring to FIG. 2 again, the control of each row of the memory cell array CA is performed by word addresses WA10 and WA2.
0 and WA30 to the word address decoders 12, 2
2 and 32 by sending. The word address decoders 12, 22 and 32 are ordinary decoders, which decode the word addresses 10, 20 and 30 and send a selection signal to one of the word line control circuits 40, 50 and 60. For example, a word address W designating the first column of the memory cell array CA
When A10 is sent to the word address decoder 12, the word address decoder 12 sends the selection signal SS13 to the word line control circuit 40 via the signal line 13. The selection signal SS13 is sent by setting the potential of the signal line 13 to "H".

The word line control circuits 40, 50 and 60 are circuits having exactly the same configuration, and one word line control circuit is provided for each row of the memory cell array CA. Word line control circuit 40,
50 and 60 are word address decoders 12, 2
The left word line WL, the right word line WR, the word power supply line WV, and the word ground line WG in the corresponding column are controlled based on the selection signals SS sent from 2 and 32 and the operation mode signal 73. To do. For example, the word line control circuit 40 uses the operation mode signal AM and the selection signals SS13 and S.
Left word line WL based on S23 and SS33
1, the right word line WR1, the word power supply line WV1 and the word ground line WG1 are controlled.

FIG. 12 is a diagram showing the relationship between the input and output of the word line control circuit 40. "*" In FIG.
It indicates that either "H" or "L" may be used. Also,
In FIG. 12, the place where three values are continuously written in the column of WV1 and the column of WG1 indicates that the potentials of WV1 and WG1 change during the calculation. For example, when the operation mode signal AM is in the inversion mode, 13 =
The column of WV1 in the case of “L”, 23 = “*”, 33 = “H” indicates that WV1 once drops from Vcc to 0.5 Vcc and then returns to Vcc again.

Referring to FIG. 13, word line control circuit 4
0 is a decoder 44 for decoding the operation mode signal AM
A right word line control circuit 46 that controls the potential of the right word line WR1, a left word line control circuit 47 that controls the potential of the left word line WL1, and a potential of the word power supply line WV1 and the word ground line WG1. Power control circuit 48
And timing control signal lines 451, 452 and 453.
And a timing control circuit 45 for synchronizing the right word line control circuit 46, the left word line control circuit 47, and the power supply control circuit 48 by changing the potential of 2 at a predetermined time interval.

The decoder 44 is a normal decoder,
By decoding the operation mode signal AM, the potential of the signal line 441 in the normal mode, the potential of the signal line 442 in the inversion mode “001”, the potential of the signal line 443 in the logical sum mode “010”. The reverse shift mode "01
When it is "1", the potential of the signal line 444 is set to "H". The operation mode signal AM is in the ready mode "10".
In the case of "0", the potentials of the signal lines 441 to 444 are all set to "L".

The timing control circuit 45 has a signal line 441.
~ 444 and the potentials of the timing control signal lines 451, 452 and 453 are controlled at the timings shown in FIG. 14 according to the potentials of the signal lines 13, 23 and 33.

The right word line control circuit 46 has a signal line 441.
~ 444, the signal lines 13, 23 and 33, and the timing control signal line 451 control the potential of the right word line WR1 as shown in FIG. Referring to FIG. 15, such a right word line control circuit 46 has two AND circuits 461 and 462 and one OR circuit 463.
Composed of and.

The left word line control circuit 47 has a signal line 441.
~ 444, the signal lines 13, 23 and 33, and the potential of the timing control signal line 452, the potential of the left word line WL1 is controlled as shown in FIG. Referring to FIG. 16, such a left word line control circuit 47 is composed of three AND circuits 471, 472 and 473 and one OR circuit 474.

Referring again to FIG. 13, the power supply control circuit 4
8 is the signal lines 441 to 444, the signal lines 13, 23 and 3
3 and the potentials of the timing control signal line 453, the potentials of the word power supply line WV1 and the word ground line WG1 are controlled as shown in FIG. Referring to FIG. 17, such a power supply control circuit 48 includes a power supply switching circuit 481, a ground switching circuit 482, a transfer gate 483, and AND circuits 484 and 485. The AND circuit 484 is a deactivation signal line 486.
The potential of is set to "H". The AND circuit 485 sets the bias signal line 487 to "H". Power switching circuit 48
1 is a deactivation signal line 486 and a bias signal line 48.
A predetermined voltage is applied to the word power supply line WV1 according to the potential of 7. The relationship between the potentials of the inactivation signal line 486 and the bias signal line 487 and the voltage applied to the word power supply line WV1 is shown in FIG.

Referring to FIG. 17, the ground switching circuit 4
Reference numeral 82 denotes an inactivation signal line 486 and a bias signal line 4
A predetermined voltage is applied to the word ground line WG1 according to the potential of 87. The relationship between the potentials of the inactivation signal line 486 and the bias signal line 487 and the voltage applied to the word ground line WG1 is shown in FIG.

Referring to FIG. 19, a power supply switching circuit 481
Is composed of a transfer gate 4811, a transfer gate 4812, and a NOR circuit 4813. A voltage Vcc is applied to the transfer gate 4811. In addition, the transfer gate 4812
Is applied with 1.5 Vcc, which is a voltage 1.5 times Vcc. The power supply switching circuit 481 applies one of Vcc and 1.5 Vcc to the word power supply line WV1 as shown in FIG. 18 according to the potentials of the inactivation signal line 486 and the bias signal line 487.

Referring to FIG. 20, the ground switching circuit 4
Reference numeral 82 includes a transfer gate 4821, a transfer gate 4822, a NOR circuit 4823, and an OR circuit 4824. Transfer gate 48
A voltage GND is applied to 21. Further, the transfer gate 4822 is applied with 0.5 Vcc, which is 0.5 times the voltage Vcc, and the ground switching circuit 482 is shown in accordance with the voltages of the inactivation signal line 486 and the bias signal line 487. Vcc and 0.
Either one of 5 Vcc is applied to the word ground line WG1.

Next, the read operation of the memory device of the present invention in the normal mode will be described with reference to FIGS. When "1" is stored in the memory cell C11, the operation for reading the content will be described below.

2 and 3, the operation mode signal AM = "100" indicating the ready mode is sent to the signal line 73 before the operation is started. At time T0, the operation mode signal AM changes from the ready mode “100” to the normal mode “000” and the operation is started.

At time T0, the signal line 72 receives the control signal CS = "0" designating the read operation.
The bit address BA = "0" indicating the first column is sent to 1 and the word address WA10 = "00" designating the first row is sent to the signal line 10.

Referring to FIG. 9, the bit line selection circuit 721 in the bit control circuit 70 connects the transfer gates 731 to 743 in accordance with the bit address BA = "0" received via the signal line 71. Referring to FIG. 11, in this case, since only the potential of the signal line 722 is set to “H”, the left bit line BL1 and the signal line 713, and the right bit line BR1 and the signal line 712 are respectively set. Connected.

At time T0, the word address decoder 12 which receives the word address WA10 = "00" via the signal line 10 decodes "00". Referring to FIG. 3, as a result, the word address decoder 12
The selection signal SS13 is transmitted by setting the potential of the signal line 13 to "H".

Further, referring to FIG. 13, since the operation mode signal AM changes from the ready mode “100” to the normal mode “000” at the time T0, the decoder 44 in the word line control circuit 40 causes the signal line 441 to operate. The potential of is set to "H". The timing control circuit 45 is
The timer operation is started when the potential of the signal line 411 changes to “H”, and the potentials of the timing control signal lines 451, 452, and 453 are controlled at a predetermined timing. Referring to FIG. 14, in this case, the signal line 13
Since the potential of is "H", the potentials of the timing control signal lines 451, 452 and 453 are controlled at the timing of 14-a.

Referring again to FIG. 13, at time T1, the timing control circuit 45 determines that the timing control signal line 4 has
The potential of 51 and the potential of the timing control signal line 452 are set to "H". Referring to FIG. 3, since the potential of the timing control signal line 451 changes to “H”, the right word line control circuit 46 changes the potential of the right word line WR1 to “H”.
To As a result, the potential “L” of the right node NR11 of the memory cell C11 is transmitted to the right bit line BR1. Further, the potential of the timing control signal line 452 is “H”.
Due to the change, the left word line control circuit 47 sets the potential of the left word line WL1 to "H". As a result, the left node NL1 of the memory cell C11 is connected to the left bit line BL1.
The potential "H" of 1 is transmitted.

Then, the I / O circuit 711 whose read operation is designated by the control signal CS is connected to the right bit line BR.
By comparing the potential of 1 with the potential of the left bit line BL1, it is determined that the memory content of the memory cell C11 is "1", and "1" is sent to the data signal line D.

Next, the write operation of the memory device of the present invention in the normal mode will be described with reference to FIGS. 2 and 4. The operation for writing "0" in the memory cell C11 will be described below.

Referring to FIG. 4, before the operation is started, the operation mode signal AM =
"100" has been sent. At time T0, the operation mode signal AM changes from the ready mode “100” to the normal mode “000” and the operation is started.

At time T0, a control signal CS = "1" designating a writing operation is sent to the signal line 71 on the signal line 71.
Is a bit address BA = "0" indicating the first column, and the signal line 10 is a word address W designating the first row.
A10 = “00” is sent out.

Referring to FIG. 9, the bit line selection circuit 721 in the bit control circuit 70 connects the transfer gates 731 to 743 in accordance with the bit address BA = “0” received via the signal line 71. Referring to FIG. 11, in this case, since only the potential of the signal line 722 is set to “H”, the left bit line BL1 and the signal line 713, and the right bit line BR1 and the signal line 712 are respectively set. Connected. Further, since the control signal 72 indicates the write operation, the I / O circuit 711 sets the left bit line BL1 to "L" and the right bit according to the write data "0" sent to the data signal line D. The bit line BR1 is set to "H".

Referring to FIG. 13, since the operation mode signal AM changes from the ready mode “100” to the normal mode “000” at time T0, the decoder 44 in the word line control circuit 40 causes the potential of the signal line 441 to rise. Is set to "H". The timing control circuit 45 starts the timer operation when the potential of the signal line 411 changes to “H”, and controls the potential of the timing control signal lines 451, 452, and 453 at a predetermined timing. Referring to FIG. 14, in this case, since the potential of the signal line 13 is “H”, the timing control signal line 45
The potentials of 1, 452 and 453 are controlled at the timing of 14-a.

Referring to FIG. 14, at time T1,
The timing control circuit 45 uses the timing control signal line 451.
And the potential of the timing control signal line 452 is set to "H". Referring to FIG. 4, the timing control signal line 45
The change of the potential of 1 to "H" causes the right word line control circuit 46 to set the potential of the right word line WR1 to "H". As a result, the right node NR11 of the memory cell C11
Is transmitted to the potential "L" of the right bit line BR1. As the potential of the timing control signal line 452 changes to “H”, the left word line control circuit 47 causes the left word line WL1
The potential of is set to "H". As a result, the memory cell C
The potential “L” of the left bit line BL1 is transmitted to the left node NL11 of 11.

At time T10, timing control circuit 45 stops sending timing control signal 451 and timing control signal 452. As a result, the potential of the left node NL1 = “L”, the potential of the right node NR1 =
"H" is maintained and "0" is stored in the memory cell C11.

Next, the operation of the memory device of the present invention in the inversion operation mode will be described with reference to FIGS. A case will be described in which, when "1" is stored in the memory cell C11 in advance, the inverted "0" of the data stored in the memory cell C11 is stored in the memory cell C31.

Referring to FIGS. 2 and 5, the operation mode signal AM = "100" indicating the ready mode is sent to the signal line 73 before the operation is started. At time T0, the operation mode signal AM is ready mode = “100”
To inversion mode = “001”.

Referring to FIGS. 2 and 5, at time T0, the row storing the inverted data is designated by word address WA10, and the row storing the inverted data is designated by word address WA30. To be done. In this case, the signal line 10 has a word address WA10 = “00” that specifies the first row, and the signal line 30 has a word address WA30 = that specifies the third row.
"10" is transmitted respectively.

Referring to FIG. 9, the bit line selection circuit 721 in the bit control circuit 70 connects the transfer gates 731 to 743 since the operation mode signal AM designates the inversion mode "001".

Referring to FIG. 11, in this case, the signal line 7
Since only the 24 potential is set to "H", the left bit line BL1 and the right bit line BR1 are also set to the left bit line BL.
2 and the right bit line BR2 are connected to each other.

Referring again to FIGS. 2 and 5, time T
At 0, the word address WA1 is transmitted via the signal line 10.
0 = “00” received word address decoder 12
Decodes "00". As a result, the word address decoder 12 sends the selection signal SS13 by setting the potential of the signal line 13 to "H". At time T0, the word address WA is transmitted via the signal line 30.
30 = “10” received word address decoder 32
Decodes "10". As a result, the word address decoder 32 sends the selection signal SS35 by setting the potential of the signal line 35 to "H".

Referring to FIG. 13, since the operation mode signal AM changes from the ready mode "100" to the inversion mode "001" at time T0, the decoder 44 in the word line control circuit 40 causes the potential of the signal line 442 to rise. Is set to "H". When the signal line 442 is set to “H”, the timing control circuit 45 starts the timer operation and controls the potentials of the timing control signal lines 451, 452 and 453 at a predetermined timing. Referring to FIG. 14, in this case, since the operation mode is the inversion mode and the potential of the signal line 13 is “H”,
Timing control signal lines 451, 452 and 453 are set to 1
It is sent at the timing of 4-d. The potentials of the left word line WL1, the right word line WR1, the word power supply line WV1 and the word ground line WG1 are controlled according to the potentials of the timing control signal lines 451, 452 and 453.

At time T0, the word line control circuit 60 also starts the timer operation similarly to the word line control circuit 40, and the left word line WL3, the right word line WR3, the word power supply line WV3 and the word ground line WG3. Control the electric potential. Referring to FIG. 14, in this case, since the operation mode is the inversion mode and the potential of the signal line 35 is “H”, the left word line WL1, the right word line WR1, the word power supply line WV1 and the word ground line WG1 are not changed. Potential is 1
It is controlled at the timing of 4-f.

Referring to FIGS. 2 and 5, at time T1, word line control circuit 40 sets the potential of right word line WR1 to "H". As a result, the potential "L" of the right node NR11 of the memory cell C11 is transmitted to the right bit line BR1 and the left bit line BL1. Not only the potential of the right bit line BR1 but also the potential of the left bit line BL1 is changed by the bit control circuit 70.
This is because 1 and the right bit line BR1 are connected.

At time T1, the word line control circuit 60 changes both the potential of the word power supply line WV3 and the potential of the word ground line WG3 to 0.5 Vcc so that the word power supply line WV3 and the word ground line WG3 are connected. Equipotential. As a result, the memory cell C11 is inactivated,
The previously stored contents are deleted.

At time T3, the word line control circuit 60.
Sets the potential of the left word line WL3 to "H". As a result, the potential "L" of the left bit line BL1 is transmitted to the left node NL31 of the memory cell C31. That is,
The potential of the right node NR11 of the memory cell C11 is transmitted to the left node NL31 of the memory cell C31. In other words, the inverted potential of the left node NL11 of the memory cell C11 becomes the potential of the left node NL31 of the memory cell C31.

At time T5, the word line control circuit 60
Resets the potential of the word power supply line WV3 to Vcc and the potential of the word ground line WG3 to GND. At this time,
Since the potential of the left node NL31 of the memory cell C31 is lower than the potential of the right node NR31, “0” is held in the memory cell C31.

At time T10, the word line control circuit 4
0 returns the potential of the right word line WR1 and the word line control circuit 60 returns the potential of the left word line WL3 to "L". As a result, the memory cell C31 has the left bit line B
Separated from L1 and the right bit line BR1, "0" which is the inverted value of the stored content "1" of the memory cell C11 is stored in the memory cell C31.

At time T10, the operation mode signal AM is returned to the ready mode = “100”, and the potentials of the signal line 13, the signal line 35 and the left word line WL3 are returned to “L”. This ends the operation in the inversion mode.

Further, the above-mentioned operation is performed by the memory cell array C.
Not only the first column of A but also the second column is simultaneously performed. That is, when the above operation is completed, the inversion of the stored contents of the memory cell C12 is written in the memory cell C32. Therefore, according to the above-described operation, the inversion of the storage contents of the first row of the memory cell array CA is operated in parallel and written simultaneously to the third row of the memory cell array CA.

Next, the operation of the memory device of the present invention in the OR mode will be described with reference to FIGS. When “1” is stored in the memory cell C11 and “0” is stored in the memory cell C12 in advance, the storage content “1” of the memory cell C11 and the storage content “0” of the memory cell C12 are “OR”. A case where 1 "is stored in the memory cell C31 will be described.

Referring to FIGS. 2 and 6, the operation mode signal AM = "100" indicating the ready mode is sent to the signal line 73 before the operation is started. At time T0, the operation mode signal AM is ready mode = “100”
To inversion mode = “010”.

At time T0, the two rows that store the data to be ORed have the word address WA1.
It is designated by 0 and the word address WA20. The row in which the result of the logical sum is to be stored is designated by the word address WA30. In this case, the signal line 10 has a word address WA10 = “00” for designating the first row.
However, the signal line 20 has a word address W that specifies the second row.
A20 = “01” and a word address WA30 = “10” designating the third row are transmitted to the signal line 30, respectively.

Referring to FIG. 11, the bit control circuit 70
In the bit line selection circuit 721, the transfer mode 731 does not connect the transfer gates 731 to 743 because the operation mode signal AM specifies the logical sum mode “010”.

Referring again to FIGS. 2 and 5, time T
At 0, the word address WA1 is transmitted via the signal line 10.
0 = “00” received word address decoder 12
Decodes "00". Referring to FIG. 6, as a result, the word address decoder 12 sends the selection signal SS13 by setting the potential of the signal line 13 to "H". At time T0, the word address decoder 22 that has received the word address WA20 = "01" via the signal line 20 decodes "01". as a result,
The word address decoder 22 sends the selection signal SS24 by setting the potential of the signal line 24 to "H". At time T0, the word address decoder 32 that has received the word address WA30 = “10” via the signal line 30 decodes “10”. As a result, the word address decoder 32 sets the potential of the signal line 35 to “H”.
By setting to, the selection signal SS35 is transmitted.

At time T0, the operation mode signal AM changes to the logical sum mode, so that the word line control circuit 40 starts the timer operation, and the left word line WL1, the right word line WR1, the word power supply line WV1 and the word ground. Line W
Control the potential of G1. Referring to FIG. 14, in this case, the operation mode is the logical sum mode, and the potential of the signal line 13 is “H”. Therefore, the left word line WL1, the right word line WR1, the word power supply line WV1, and the word ground line W.
The potential of G1 is controlled at the timing of 14-g.

At time T0, the operation mode signal AM changes to the logical sum mode, so that the word line control circuit 50 starts the timer operation, and the left word line WL2, the right word line WR2, the word power supply line WV2 and the word ground. Line W
Control the potential of G2. Referring to FIG. 14, in this case, the operation mode is the logical sum mode, and the potential of the signal line 24 is “H”. Therefore, the left word line WL2, the right word line WR2, the word power supply line WV2, and the word ground line W.
The potential of G2 is controlled at the timing of 14-h.

At time T0, the operation mode signal AM changes to the logical sum mode, so that the word line control circuit 60 starts the timer operation, and the left word line WL3, the right word line WR3, the word power supply line WV3 and the word ground. Line W
Control the potential of G3. Referring to FIG. 14, in this case, the operation mode is the logical sum mode and the potential of the signal line 35 is “H”. Therefore, the left word line WL3, the right word line WR3, the word power supply line WV3, and the word ground line W.
The potential of G3 is controlled at the timing of 14-i.

Referring to FIGS. 2 and 6, at time T1, word line control circuit 40 sets the potential of right word line WR1 to "H". As a result, the potential GND of the right node NR11 of the memory cell C11 is transmitted to the right bit line BR1.

At time T1, the word line control circuit 50
Sets the voltage of the word power supply line WV2 to 1.5 Vcc and the voltage of the word ground line WG2 to 0.5 Vcc.
As a result, the potential of the left node NL12 of the memory cell C21 changes from "L" = GND to 0.5 Vcc, and the potential of the right node N21.
The potential of R21 rises from "H" = Vcc to 1.5 Vcc. Further, at time T1, the word line control circuit 50
Sets the potential of the left word line WL2 to "H". As a result, 0.5 Vcc, which is the potential of the left node NL21 of the memory cell C21, is transmitted to the left bit line BL1.

At time T1, the word line control circuit 60.
Sets the potentials of the word power supply line WV3 and the word ground line WG3 to 0.5 Vcc. As a result, the memory cell C31 is inactivated, and the contents stored before the time T1 are erased.

At time T3, the word line control circuit 60
Sets the potential of the left word line WL3 to "H". As a result, the potential Vcc of the left bit line BL1 is transmitted to the left word line WL31 of the memory cell C31. Further, at time T3, the word line control circuit 60 sets the potential of the right word line WR3 to “H”. As a result, the potential GND of the right bit line BR1 is transmitted to the right word line WR31 of the memory cell C31.

At time T5, the word line control circuit 60
Is the word power supply line WV3 and the word ground line WG3.
Potentials of Vcc and GND are returned to Vcc and GND, respectively. At this time, the potentials of the left node NL31 and the right node NR31 are Vcc and GND, respectively.
Since the potential of the right node NR31 is higher than the potential of the right node NR31, the potential of the left node NL31 becomes Vcc = “H” and the potential of the right node NR31 becomes GND = “L”.

At time T10, the word line control circuit 6
0 returns the potentials of the left word line WL3 and the right word line WR3 to "L". Since the potential of the left node NL31 is “H” and the potential of the right node NR31 is “L”, the memory cell C31 has the stored content “1” of the memory cell C11.
And "1" which is the logical sum of the storage contents "0" of the memory cell C21 are stored.

At time T10, operation mode signal AM
Is ready mode "100", signal line 13, signal line 1
4, signal line 35, right word line WR1, left word line WL
2. The potentials of the left word line WL3 and the right word line WR3 are returned to "L", the potential of the word power supply line WV2 is returned to Vcc, and the potential of the word ground line WG2 is returned to GND. This completes the OR operation.

Although the case where the memory cell C11 = "1" and the memory cell C21 = "0" has been described above, the memory device of this embodiment can be used even when the memory cell C11 and the memory cell C21 have other values. Can perform an exact OR operation. A time chart when the memory cell C11 is not "1" and the memory cell C21 is not "0" is shown in FIG. In either case, the left node NL3
Of the 1 and the right node NR31, the one having a higher potential than the others at time T5 is set to "H" at time T10, and the correct logical sum operation is thereby performed. For example,
The case of C11 = “0” and C21 = “1” will be described. At time T5, the potential of the left node NL31 is 1.5 Vcc which is the potential of the left node NL21, and the potential of the right node NR31 is the right node NR11. The potential of V
It is cc. At this time, since the potential of the left node NL31 is higher than the potential of the right node NR31, at time T6, the potential of the left node NL31 becomes “H”, the potential of the right node NR31 becomes “L”, and the memory cell C31 becomes “L”. 1 ”is written. This is equal to the logical sum "1" of the stored content "0" of the memory cell C11 and the stored content "1" of the memory cell C21.

Further, the above-mentioned operation is performed by the memory cell array C.
Not only the first column of A but also the second column is simultaneously performed. That is, when the above operation is completed, the logical sum of the storage content of the memory cell C12 and the storage content of the memory cell C22 is written in the memory cell C32. Therefore, according to the above-described operation, the logical sum of the storage contents of the first row and the storage contents of the second row of the memory cell array CA is operated in parallel, and the cells of the third row of the memory cell array CA are simultaneously operated. Will be written.

Next, the operation of the memory device of the present invention in the inversion shift mode will be described with reference to FIGS.
When “1” is stored in the memory cell C11 in advance,
Invert "0" of the data stored in the memory cell C11 to 1
A case of inverting and shifting to the right to the bit and storing it in the memory cell C23 will be described.

Referring to FIGS. 2 and 8, before the operation is started, the operation mode signal AM = “100” indicating the ready mode is sent to the signal line 73. At time T0, the operation mode signal AM is ready mode = “100”
To inversion shift mode = "011".

At time T0, the row in which the data to be inverted shifted is stored is designated by word address WA10, and the row in which the data after the inverted shift is stored is designated by word address WA30. In this case, the word address WA10 = “00” designating the first row is sent to the signal line 10, and the word address WA30 = “10” designating the third row is sent to the signal line 30.

Referring to FIG. 9, the bit line selection circuit 721 in the bit control circuit 70 connects the transfer gates 731 to 743 since the operation mode signal AM specifies the inversion mode "001". Referring to FIG. 11, in this case, since the potential of the signal line 725 is set to “H”, the right bit line BR1 and the left bit line BL2 are connected.

Referring again to FIGS. 2 and 8, time T
At 0, the word address WA1 is transmitted via the signal line 10.
0 = “00” received word address decoder 12
Decodes "00". As a result, the word address decoder 12 sends the selection signal SS13 by setting the potential of the signal line 13 to "H". At time T0, the word address WA is transmitted via the signal line 30.
30 = “10” received word address decoder 32
Decodes "10". As a result, the word address decoder 32 sends the selection signal SS35 by setting the potential of the signal line 35 to "H".

At time T0, the operation mode signal AM changes to the logical sum mode, so that the word line control circuit 40 starts the timer operation, and the left word line WL1, the right word line WR1, the word power supply line WV1 and the word ground. Line W
Control the potential of G1. Referring to FIG. 14, in this case, the operation mode is the inversion shift mode, and the signal line 13
Potential of "H" is high, the potentials of the left word line WL1, the right word line WR1, the word power supply line WV1 and the word ground line WG1 are controlled at the timing of 14-j.

At time T0, the operation mode signal AM is changed to the logical sum mode, so that the word line control circuit 60 starts the timer operation, and the left word line WL3, the right word line WR3, the word power supply line WV3 and the word ground line. Line W
Control the potential of G3. Referring to FIG. 14, in this case, the operation mode is the inversion shift mode, and the signal line 35
Potential is high, the potentials of the left word line WL3, right word line WR3, word power supply line WV3, and word ground line WG3 are controlled at a timing of 14-1.

Referring to FIGS. 2 and 8, at time T1, word line control circuit 40 sets the potential of right word line WR1 to "H". As a result, the potential "L" of the right node NR11 of the memory cell C11 is transmitted to the right bit line BR1 and the left bit line BL2. The bit control circuit 70 changes the potential of the right bit line BR2 as well as the potential of the right bit line BR1.
This is because 1 and the right bit line BR2 are connected.

At time T1, the word line control circuit 60 changes the potential of the word power supply line WV3 and the potential of the word ground line WG3 to 0.5 Vcc, and the word power supply line WV3 and the word ground line WG3 are equalized. The potential. As a result, the memory cell C11 is inactivated and the previously stored contents are erased.

At time T3, the word line control circuit 60
Sets the potential of the left word line WL3 to "H". As a result, the potential "L" of the left bit line BL2 is transmitted to the left node NL32 of the memory cell C32. That is,
The potential of the right node NR11 of the memory cell C11 is transmitted to the left node NL32 of the memory cell C32. In other words, the inverted potential of the left node NL11 of the memory cell C11 becomes the potential of the left node NL32 of the memory cell C32.

At time T5, the word line control circuit 60.
Resets the potential of the word power supply line WV3 to Vcc and the potential of the word ground line WG3 to GND. At this time,
Since the potential of the left node NL32 of the memory cell C32 is lower than the potential of the right node NR32, “0” is held in the memory cell C32.

At time T10, the word line control circuit 4
0 returns the potential of the right word line WR1 and the word line control circuit 60 returns the potential of the left word line WL3 to "L". As a result, the memory cell C32 is left bit line B
Separated from L2 and the right bit line BR2, "0" which is a value obtained by inverting the stored content "1" of the memory cell C11 is stored in the memory cell C32. That is, a value obtained by inverting the stored value of the first row and shifting it to the right by one is written in the third row of memory cell array CA.

At time T10, operation mode signal AM
Is in the ready mode = “100”, and the signal line 13,
Signal line 35, right word line WR1 and left word line WL3
Is also returned to "L". This ends the operation in the inversion shift mode.

In this embodiment, the memory cell array CA
Although the description has been given for the case where there are two columns, the memory cell array C
When A has two or more columns, the above operation is performed in the memory cell array C.
The same is done not only for the first column of A but for the second and subsequent columns. Therefore, according to the above-described operation, the inversion of the memory content of the first row of the memory cell array CA is shifted to the right by 1 bit and simultaneously written in the cells of the third row of the memory cell array CA. .

In the present embodiment, the case of the right inversion shift has been described. However, if the word address WA30 designates the first row and the word address WA10 designates the third row,
Invert the stored contents of the third row of the memory cell array CA to 1
It is possible to write the data that has been left-shifted to the left by one in each cell in the first row of the memory cell array CA.

In the above embodiment, the word address WA1
0 for signal line 10 and word address WA20 for signal line 2
When the word address WA30 is 0, the word address WA30 is transmitted through the signal line 30, respectively. However, the number of signal lines can be reduced by using one of these three signal lines and the signal line 71 for transmitting the bit address BA.

Further, in the above embodiment, each arithmetic operation is started by the change of the arithmetic mode signal AM, but a signal instructing the start of each arithmetic operation may be supplied from the outside. Further, the timing control signal lines 451, 452 and 453 sent out by the timing control circuit 45 may be supplied from the outside.

In the present embodiment, for convenience of explanation, the case where the memory cells CA are 3 rows and 2 columns has been described, but the number of columns and the number of rows of the memory cell array CA may be arbitrary. In addition, the memory cell array CA has 1000 rows and 400 rows.
In the case of 0 column, 400 in any column of the memory cell array CA
The operation of the contents of 0 cells is executed in parallel and can be simultaneously written in each cell of other columns of the memory cell array CA. That is, 4000 logical operations are executed in parallel.
Further, by arranging a plurality of memory devices in parallel, it is possible to increase the number of operations executed at one time.

[0112]

According to the memory cell of the present invention described above, the following operation can be performed in addition to the normal read / write operation. First, in the SRAM memory cell described above, only the potential of the left node of the memory cell can be referred to by setting only the left word line to the high level. Secondly, in the SRAM memory cell described above, by setting only the right word line to the high level, it is possible to refer only to the potential of the right node of the memory cell. Thirdly, by setting the potential of the power supply terminal and the potential of the ground terminal to be the same potential, the stored contents in the memory cell can be erased and the memory cell can be initialized.

Further, according to the above-described memory device of the present invention, the contents stored in any row of the memory cell array CA are subjected to the inversion operation, the logical sum operation, or the inversion shift operation to perform any operation of the memory cell array CA. You can write in a line. Therefore, by combining these operations, it is possible to execute an arbitrary operation between arbitrary cells. Further, in the normal mode, the memory device of this embodiment can perform the read and write operations similar to those of the conventional SRAM device.

Further, in the memory device of the present invention, the logical operation between memory cells and the operation of writing the operation result are performed only in the memory cell array CA. Therefore, it is not necessary to provide a holding means for temporarily holding the content of the memory cell outside. Further, in the present embodiment, it is not necessary to move the contents of the memory cell to the outside, so that the operation can be executed at high speed.

Further, in the memory device of the present invention, only one word line control circuit and one word address decoder need be installed in each row of the memory cell array CA, and it is not necessary to provide a logical operation element in each cell. Therefore, the memory device according to the present embodiment can be configured with a smaller number of elements as compared with the conventional logic-in memory. Therefore, when the memory device according to this embodiment is integrated into an IC, the area of the IC chip can be reduced. Also, if you compare in the chip of the same area,
It can have more storage capacity than a logic-in-memory chip.

Further, in the memory device of the present invention, three types of operations of inversion, logical sum and inversion shift can be executed with the same configuration. Therefore, in this embodiment, the required number of elements is small and the degree of integration is high. Therefore, when the memory device of this embodiment is implemented as an LSI, the number of memory cells incorporated in the same area is large.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an example of a memory cell of an SRAM of the present invention.

FIG. 2 is a block diagram showing an example of a memory device of the present invention.

FIG. 3 is a time chart showing a read operation in a normal mode according to the first embodiment of the present invention.

FIG. 4 is a time chart showing a write operation in a normal mode according to the first embodiment of the present invention.

FIG. 5 is a time chart showing the operation of the first embodiment of the present invention in the reverse mode.

FIG. 6 is a time chart showing the operation in the logical sum mode of the first embodiment of the present invention.

FIG. 7 is a time chart showing an operation in a logical sum mode according to the first embodiment of the present invention.

FIG. 8 is a time chart showing the operation in the reverse shift mode of the first embodiment of the present invention.

FIG. 9 is a bit control circuit 70 according to the first embodiment of the present invention.
Block diagram showing the configuration of FIG.

FIG. 10 is a block diagram showing the configuration of a transfer gate according to the first embodiment of the present invention.

FIG. 11 is a bit control circuit 7 according to the first embodiment of the present invention.
The figure which shows the truth value of 0.

FIG. 12 is a diagram showing an operation of the word line control circuit 40 according to the first embodiment of the present invention.

FIG. 13 is a block diagram showing the configuration of a word line control circuit 40 according to the first embodiment of the present invention.

FIG. 14 is a time chart showing the operation of the timing control circuit 45 according to the first embodiment of the present invention.

FIG. 15 is a circuit diagram showing a configuration of a right word line control circuit 46 according to the first embodiment of the present invention.

FIG. 16 is a circuit diagram showing a configuration of a left word line control circuit 47 according to the first embodiment of the present invention.

FIG. 17 is a power supply control circuit 48 according to the first embodiment of the present invention.
Block diagram showing the configuration of FIG.

FIG. 18 is a power supply control circuit 48 according to the first embodiment of the present invention.
FIG.

FIG. 19 is a power supply switching circuit 48 according to the first embodiment of the present invention.
2 is a circuit diagram showing the configuration of FIG.

FIG. 20 is a circuit diagram showing a configuration of a ground switching circuit 482 according to the first embodiment of the present invention.

FIG. 21 is a circuit diagram showing a configuration of a conventional memory cell.

FIG. 22 is a circuit diagram showing a configuration of a memory cell in a conventional CAM.

[Explanation of symbols]

1 FET 2 FET 3 Gate FET 4 Gate FET 5 Drain load 6 Drain load 12, 22, 32 Word address decoder 40, 50, 60 Word line control circuit 70 bit control circuit 44 Decoder 45 Timing control circuit 46 Right word line control circuit 47 Left word line control circuit 48 power supply control circuit 451-453 timing control signal line 481 power supply switching circuit 482 ground switching circuit 483 transfer gate 486 deactivation signal line 487 bias signal line 461, 462 AND circuit 463 OR circuit 471, 472, 473 AND circuit 474 OR circuit 484, 485 AND circuit 4811, 4812 Transfer gate 4813 NOR circuit 4821, 4822 Transfer gate 4823 NOR circuit 4824 OR Road 711 I / O circuit 721 bit line selection circuit 722 to 725 connection instruction signal 731 to 734 transfer gate 741 to 743 transfer gate 10,20,30,13,14,15,23,24,2
5, 33, 34, 35, 71, 72, 73 Signal line 712, 713 Signal line 441-444 Signal line 488 Signal line 4814 Signal line 4825, 4826 Signal line AM operation mode signal BA bit address BL left bit line BR right bit Lines BL1, BL2 Left bit line BR1, BR2 Right bit line C Memory cell CA Memory cell array C11 to C32 Memory cell CS Control signal D Data signal NL Left node NR Right node SS13 to SS35 Select signal TG Transfer gate TG1, TG2, TG3 Terminal WL left word line WL11 to WL32 left word line WR right word line WR11 to WR32 right word line WV word power supply line WV1 to WV3 word power supply line WG word ground line WG1 to WG3 word ground line WA10 to WA30 word Address SUM Signal line T1 to T9 Transistors TL1 and TL2 Load (0) bit, (1) bit Bit line

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yoshihiko Kawano 3-20-4 Nishishimbashi, Minato-ku, Tokyo Inside NEC Engineering Co., Ltd.

Claims (7)

[Claims] 1. In a memory cell of a static random access memory, a transistor which receives a potential of a left word line at its gate and connects a left bit line and a memory cell, and a right word which is controlled independently of the left word line. Static random access having a transistor that receives the potential of a line at its gate and connects the right bit line to the memory cell, a power supply terminal that receives a power supply voltage from another circuit, and a ground terminal that receives a ground voltage from another circuit Memory cells of memory. 2. A left word line having the same horizontal row,
2. A group of memory cells according to claim 1, which are connected to a right word line, a word power line and a word ground line, and are connected to the same left bit line and right bit line in a vertical direction, respectively, and to the memory cells. And a bit line control circuit for controlling the potential of the bit line and one for each of the memory cells in the horizontal direction, and controlling the potentials of the left word line, the right word line, the word power supply line and the word ground line in the column. And a memory device having a word line control circuit. 3. A left word line having the same horizontal row,
2. A group of memory cells according to claim 1, which are connected to a right word line, a word power supply line and a word ground line, and are connected in the vertical direction to the same left bit line and right bit line, respectively, and a mode control signal. And a bit line control circuit for controlling the potential of a bit line connected to the memory cell, and one each in a row in the horizontal direction of the memory cell. A word line control circuit for controlling the potentials of the word line, the word power line and the word ground line, and a first word address for receiving a first word address and outputting a first selection signal to one of the word control circuits. A memory device having a decoder and a second word address decoder which receives a second word address and outputs a second selection signal to one of the word control circuits. 4. A left word line having the same horizontal row,
2. A group of memory cells according to claim 1, which are connected to a right word line, a word power supply line and a word ground line, and are connected in the vertical direction to the same left bit line and right bit line, respectively, and a word control signal. Bit line control circuit for controlling the bit line connected to the memory cell, and one bit line control circuit in the lateral direction of the memory cell, which receives the mode control signal and receives the left word line and the right word line of the column. A word line control circuit for controlling the potentials of the word power supply line and the word ground line, and a first word address decoder for receiving a first word address and outputting a first selection signal to one of the word control circuits. A second selection signal is output to the one of the word control circuits in response to the second word address.
And a third word address decoder for receiving a third word address and outputting a third selection signal to one of the word control circuits. 5. A left word line having the same horizontal row,
2. A group of memory cells according to claim 1, which are connected to a right word line, a word power supply line and a word ground line, and are connected in the vertical direction to the same left bit line and right bit line, respectively, and a mode control signal. And a bit line control circuit for controlling the potential of a bit line connected to the memory cell, and one each in a row in the horizontal direction of the memory cell. A word line control circuit for controlling the potentials of the word line, the word power line and the word ground line, and a first word address for receiving a first word address and outputting a first selection signal to one of the word control circuits. In a memory device having a decoder and a second word address decoder for receiving a second word address and outputting a second selection signal to one of the word control circuits, When an inversion operation is received as a control signal, the bit line control circuit causes the right bit line and the left bit line of at least one vertical column of the memory cell group to conduct, and the first word address decoder The selected first word line control circuit sets the potential of the left word line to the high level, and the second word line control circuit selected by the second word address decoder sets the potential of the right word line to the high level. A second step, and a third step in which the second word line control circuit temporarily sets the potential of the word power supply line and the potential of the word ground line to the same potential.
4. The method of controlling a memory device according to claim 3, further comprising: 6. A left word line having the same horizontal row,
2. A group of memory cells according to claim 1, which are connected to a right word line, a word power supply line and a word ground line, and are connected in the vertical direction to the same left bit line and right bit line, respectively, and a mode control signal. And a bit line control circuit for controlling the potential of a bit line connected to the memory cell, and one each in a row in the horizontal direction of the memory cell. A word line control circuit for controlling the potentials of the word line, the word power line and the word ground line, and a first word address for receiving a first word address and outputting a first selection signal to one of the word control circuits. In a memory device having a decoder and a second word address decoder for receiving a second word address and outputting a second selection signal to one of the word control circuits, A first step of making the right bit line of at least one column of the memory cell group and the left bit line of the column adjacent on the right side of the column by the bit line control circuit when receiving an inversion shift operation as a control signal; , The first word line control circuit selected by the first word address decoder sets the potential of the left word line to a high level, and the second word line control circuit selected by the second word address decoder is on the right side. It has a second step of setting the potential of the word line to a high level, and a third step of causing the second word line control circuit to temporarily make the potential of the word power supply line and the potential of the word ground line equal. 4. The method of controlling a memory device according to claim 3, wherein 7. A left word line having the same horizontal row,
2. A group of memory cells according to claim 1, which are connected to a right word line, a word power supply line and a word ground line, and are connected in the vertical direction to the same left bit line and right bit line, respectively, and a word control signal. And a bit line control circuit for controlling the potential of a bit line connected to the memory cell, and one each in a row in the horizontal direction of the memory cell. A word line control circuit for controlling the potentials of the word line, the word power line and the word ground line, and a first word address for receiving a first word address and outputting a first selection signal to one of the word control circuits. A decoder, a second word address decoder that receives a second word address and outputs a second selection signal to one of the word control circuits, and a third word address decoder that receives the third word address. In a memory device having a third word address decoder for outputting a third selection signal to one of the mode control circuits, the bit line control circuit causes the memory cell to operate when a logical sum operation is received as the mode control signal. The first step of bringing the right bit line and the left bit line of the group into the non-conduction state, and the first word line control circuit selected by the first word address decoder sets the potential of the right word line to the high level. And a second step in which the second word line control circuit selected by the second word address decoder sets the potential of the left word line to a high level, and the second word line control circuit causes the potential of the word power supply line. And the potential of the word ground line are temporarily raised, and the third word line control circuit selected by the third word address decoder causes the right word line and the left word line to operate. 5. The method of controlling a memory device according to claim 4, further comprising a third step of setting the potential of the word line to a high level and temporarily setting the potential of the word power line and the potential of the word ground line to the same potential. .