JPH07248360A - Formation of testing vector for vlsi circuit - Google Patents

Abstract

PURPOSE: To generate the test vector capable of efficiency carrying out the test by generating a composite circuit of a failure circuit and a failure-free circuit, separating and extracting the energy function in the binary and ternary terms, preparing the implication graph, obtaining the transition envelope to perform the logical judgment and processing, and repeating it to obtain the literal test. CONSTITUTION: A composite circuit is formed by extracting a failure circuit, and combining it with a failure-free circuit, and its energy function is extracted as the binary and ternary terms based on the functional and structural restrictions. An implication graph is prepared for the binary term, and the transition enclosure is obtained to derive the logical conclusion such as contradiction, identification, fixation, exclusion, etc., and the reduction of the ternary term into the binary term is advanced until the determined signal value satisfies all energy functions of the composite circuit. The work is repeated by using a new binary term and continued until the ternary term disappears. The input vector set capable of efficiently testing a VLSI logical circuit is generated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a VLSI (Very).
Large Scale Integration) circuit testing, and more particularly, to generating a set of input vectors suitable for efficiently testing a particular VLSI logic circuit that contains binary values for finding faults and eliminating redundancy. .

[0002]

2. Description of the Related Art As the number of VLSI circuit elements increases, the test becomes more complicated. This is because it is not practical to hit the internal node of the circuit with a probe. Therefore, usually, an input vector set is applied to the input terminal, and for each input vector, the output vector at the output terminal is observed to determine whether or not this is the expected output vector. Each input vector is chosen to find a particular fault that is believed to occur in the circuit. Since the number of failures tends to increase as the circuit becomes complicated, a large number of VLSI test vector sets are required. It is therefore important to create an input vector set that will give the maximum amount of relevant information in the shortest amount of time. In general, testing is done as follows. Automatically by an instrument designed to give a specified set of input vectors to the sample circuit under test, in order to check for output vectors that match the expected output vector and reject samples that do not match. To be done.

Selection of a set of test vectors is usually part of the integrated circuit design process. Usually, even before the desired integrated circuit prototype chip is made, an appropriate vector set is developed for use in testing the production chip. This process involves identifying the various faults that may occur in the circuit, and developing a vector set to test all or most such potential faults.

There is room for improvement in the development of such a test vector set. Traditionally, we have not guaranteed the identification of all logical consequences of signal assignment, or a subset of signal assignments. It is desirable to match all such results so that the branch and bound method can effectively avoid signal assignments that do not result in test vectors. Also, conventional techniques generally do not establish the computational complexity that determines their logical outcome, and it is unclear whether it is possible to determine all outcomes using at least a reasonable amount of resources. Finally, such techniques tend not to be easily adaptable.

[0005]

A feature of the invention is the use of transitive closure (TC) to solve the test generation problem. Basically, transitive closure (TC) is the result of adding to a directed graph a new arc implied by its original arc. Essentially, this involves adding an arc between the parent and all its descendants, ie, children, children of that child, and so on. Often, the results are presented in matrix form, as is usually done in their urgent applications. In particular, the invention includes a complete test generation algorithm based on the use of TC. Parallel computing for TC has been extensively studied. Computing TC is an important step in many parallel algorithms associated with directed graphs. In a particular application of the principles of the present invention, a composite circuit is first formed from a version of the circuit under test for which a particular test for detection is with or without an intended fault, where applicable constraints are applied. The energy function based on the set of
A set of test signal values that gives a minimum in the energy function corresponds to the test vector for the fault and is derived for the composite circuit. Such energy functions usually include both binary and ternary potential terms, and for the use of TC it is generally necessary to reduce the ternary terms to binary terms.

A feature of the invention is the process by which ternary terms are reduced to binary terms. In particular, this process first finds an entailment set based on a binary relation in the energy function, then obtains a transitive closure of the entailment set, and uses the transitive closure to detect inconsistencies, fixations, and eliminations in complex circuits Or to obtain a logical conclusion, such as the existence of an identity, and finally, using any of the reached conclusions, reduce the ternary term of the energy function to a binary term and from the updated set of binary terms Includes getting an updated implication set. This process is repeated until as many ternary terms have been reduced to binary terms. In this regard, if 3
If a binary term remains, the selected node of the circuit is assigned a specific signal value, the implication graph of the circuit so fixed is derived, and 3
The process for reducing a binary term to a binary term is repeated on it until there are no more ternary terms. If the assignment of a particular signal value is found to be inconsistent, the opposite value is assigned and the process is repeated. Ultimately, this leads to the removal of all ternary terms from the energy function. At this point, the set of signal values that minimizes its energy function is easily found, and such signal values form the desired test vector for the original circuit. The transitive closure of the circuit is calculated from the implication graph, whose vertices are the true and negated states of the signal expected to be found at various internal nodes. In this graph

[0007]

[Equation 1]

From x, also expressed as

[0009]

[Equation 2]

The directed edge to represents the control action of the true state of the signal x on the pseudo state of the signal y. The variables x and y are associated with the same gate or signal net in the circuit. Since the implication graph contains only pairwise relationships, it is a partial representation of the netlist. The implication graph as the term used here is a directed graph in which the edge from the vertex at a to the vertex at b indicates that the truth of a means the truth of b. The transitive closure of the implication graph contains a pairwise logical relationship between all signal states. All signals take only binary values, 0 or 1. If the implication graph contains signaling relationships that describe fault activation and path activation,
Transitive closure determines the signal relationships that lead to logical inconsistencies that match many redundancies directly. Physical and logical dominator activations, multiple backlaces, unique path activations, static and dynamic learning and other techniques that are useful in determining the required signal allocation are inherent in the process . If the signal thus determined meets the minimum energy function, we will have a test. The energy function consists of paired, higher order signal relationships in the netlist. Otherwise, we enter the discriminating phase, determine the unassigned signals, and update the transitive closure to determine all the logical consequences of this decision. Transitive closure computations are similar to matrix multiplications, from which they can be easily parallelized. For example, 10 October 1990
Moon, IEEE Trans. on Parallela
nd Distributed System, Vo
l. 1, pages 500-507, "reconfigurable bus
See the paper entitled "Constant Time Algorithms for Transitive Closure and Related Graph Problems for Processor Arrays with Systems".

Basically, the process of the present invention can be summarized as follows. That is: 1. First, the faulty circuit is extracted and combined with the fault-free circuit to form a composite circuit. 2. The energy function of a composite circuit is based on functional constraints that depend on the function of the gates in the circuit, as well as structural constraints that depend on the particular interconnection topology of the gates but not on the type of gate in the circuit. Extracted as binary and ternary potential terms. Various techniques for doing this are described in September 1990, IEEE Transact.
ion on Computer-Aided Des
ign, Vol. 9, pages 981-994, "About Large Scale Parallel Automatic Test Generation", 19
October 1990, IEEE Design and Te
stof Computers, Vol. 7, page 5
6-57, a paper entitled "Neural Networks and Boolean Satisfiability Models of Logic Circuits", and August 1989, Pr.
oc. of the IEEE International
onal TestConference, page 79
5-801 in the article entitled "Efficient Generation of Test Patterns Using Boolean Differentiation". 3. Determine the implication graph and the TC of the constraints that can be represented as binary terms and match the logical conclusions such as contradiction, identification, fixation and exclusion. If a contradiction is detected, the fault is redundant. If the signal value thus determined satisfies the total energy function of the composite circuit, we have a test. Otherwise, the subset of signal values determined so far will be used to reduce some of its ternary terms to binary terms. These terms are used to update the implication graph as well as to recalculate TC to match further logical conclusions. This process continues until there is no ternary relation that reduces to a binary relation. 4. Select the judgment variables that are not assigned.
This allows some of the ternary terms to become binary terms. 5. Update the implication graph using the new binary terms, calculate the new TC and draw additional logical conclusions, if there is a conflict then return to step 4 and the unassigned decision Make alternative choices for variables. Again, if that signal assignment gives the energy function of the composite circuit a minimum, we have a test. Otherwise, add the ternary term reduced to the binary term by the current signal allocation set to TC and return to step 3.

[0012]

EXAMPLES First, it will be helpful to consider the basic procedure used to develop a test vector set.

FIG. 1 shows the VLS for each of the faults with respect to the list of possible faults that may occur in the circuit.
A diagram illustrating the entire procedure used to develop a vector set for testing I circuits is shown.

The test generator 10 is supplied with a specific fault to be tested from a file in which possible faults are stored, that is, a fault list 11 which is a data set. The test generator 10 also includes a circuit netlist 1
The parameters of the circuit tested in the two forms are also provided. For a given fault and circuit netlist, the test generator provides a particular vector for use in testing the particular fault. Expanded test vector 1
3 is fed to a fault simulator 14, which is designed to recognize the suitability of a particular test vector for testing other faults in the fault list 11. Since such other possible faults are used in the means 15 to update the fault list and delete such other faults from the fault list 11, a separation vector for any such other faults needs to be generated. Absent.

If the fault is a redundant fault (a fault that has no test vector), then such fault is removed from the fault list by using the updated fault list means 15.

Further, as the updated fault list means 15 is updated, the information of the faults remaining on the list 11 is checked by the coverage check means 16 to confirm whether or not the desired coverage of possible faults has been reached. And the answer is yes, the process is stopped. The coverage check determines whether the test vector set detects a prespecified number of faults on the chip.

In this basic system or process, the invention centers on test generation steps or components.

2 and 3 should be viewed as a flow chart of the basic steps for achieving test generation, ie a combination of means for achieving test generation.

The process of generating a suitable test vector set in accordance with an embodiment of the present invention begins with circuit preparation step 100.

This stage involves a series of steps to reach a peak in the generation of an implication graph for the circuit under test as well as the particular fault to be checked. Although various techniques are available for this stage, the ones described below are preferred when the circuit complexity is significant.

In particular, our exemplary process is described in 1990.
September, IEEE Trans. on Compute
r-Aided Design, Vol. 9, No.
9, pages 981-994, whose circuit functions are coded in firing thresholds of neurons or nerve cells and weights at interconnecting links, as described in a paper entitled "About Large-Scale Parallel Automatic Test Generation". Beginning with step 101, which includes representing a digital circuit to be tested formed by combining fault-free and faulty circuit functions as a composite network to be embodied. For this reason, there are 19
June 24, 1990, 27th ACM / IEEE De
sign Automation Conference
As indicated by step 103 in the manner described in the paper entitled "Automatic Test Generation Using Secondary 0-1 Programming" presented in e.
The neural network energy function from which the automatic test generation network is generated is derived. In both of these last two publications we were included as two of the three authors. In the methodology of these two publications,
The relationship between the input and output signal states of a logic gate is
The minimum energy state is represented through the energy function to correspond to the logic function of that gate. This energy function E is divided into two sub-functions, a homogeneous positive form E _H and an inhomogeneous positive form E _I. In this technique, the positive form (positive pseudo-Boolean form) is the monomial plus a positive coefficient. Homogeneous positive forms do not have a constant term and therefore consist only of binary terms.
The non-homogeneous positive form has a constant term and only a ternary potential term. The desired minimum value is the sum of the minimum values of the two subfunctions, each having a minimum value of zero. As described in the last paper, homogeneous positive forms will have many minimizing points exponentially.
To help find the minimum, the homogeneous positive form is first used to derive the implication graph directly. The remaining non-homogeneous positive forms are
As indicated by step 103, it is treated as containing ancillary information that will be used incrementally later in updating the initial implication graph. This two-stage process makes it much easier to find the desired minimum than if the entire energy function were considered together.

As previously indicated, the step 105 of computing the transitive closure of a directed graph is a well known process and is discussed in the book McGraw Hill 1990, "Introduction to Algorithms".
In our particular embodiment, we refer to FIGS.
Using a modification of this process, as will be discussed with reference to. An important application of transitive closure lies in drawing all the logical conclusions implied by the set of binary relations.

From the TC, it is determined if there is a conflict, as indicated by step 106. If there is a contradiction, the fault is redundant and this fault is removed from the fault list as previously described.
If there is no discrepancy detected by TC, we
Check, as in step 107, if there is any fixation, identification and exclusion. If the answer is yes, this information takes the term from E _I , as indicated by step 108, and step 105.
Is used to update the homogeneous positive form E _H by recalculating the transitive closure as shown by, and the process is repeated. If there is no fixation, exclusion and identification, we use the final branch and bound phase of test generation (Figure 3).

As shown at step 121, there is provided an ordered list of included variables from the information received from the initial redundancy identification phase. The next unallocated variable on the ordered list is then pushed onto the stack, as indicated by step 122, and the value (0 or 1), as indicated by step 123. Is assigned to the variable at the top of the stack. This value updates E _H and its current implication graph, as indicated by step 124, after which step 12
It is used to recalculate the transitive closure as shown by 5. Then, in step 126, the existence of a conflict is checked. If there is a contradiction,
In step 127 it is checked whether the top variable on the stack has been tested with the assigned 0's and 1's. If the answer is no, at step 128 some value is assigned to the top variable in the stack and the reallocated variable is taken at step 12
4 and 125. Then, step 126
At, again, the presence or absence of a contradiction is checked. If the answer is yes again, then step 12
The answer at 7 is also Yes, and the literal is popped from that stack, as shown in stack 132.

Next, in step 129, it is checked whether the stack is empty. If the answer is Y
If es, then the fault being tested is redundant. If the answer is no, step 12
Return to 7.

If the answer in step 126 is no, the transitive closure is examined for exclusion, fixation and identification, as indicated by step 130. If there is any, go back to step 124 and E
Update _H and Implication Graph and continue as before.

If the answer to step 130 is no, then step 131 is entered to check if any unassigned variables remain in the list. If the answer is no, it corresponds to a good test being found. If the answer is yes, the variable is still in the list, so return to step 122 to push the next unallocated variable on the list to the top of the stack. This process is repeated until all variables on the list have been cycled.

Now, we will show our method through a simple example. Consider the circuit of FIG. This circuit has a NAND gate 50 with inputs a and b and output c.
And NAND gate 5 with inputs b and c and output d
It consists of 2. We are the NAND gate c
On output, it will bring out a test for a "stuck-at-0" (s-a-0) fault 54.

First, we show in FIG. 6 that a NAND circuit 55 sharing input b and having a new input c'and a new output d'is added to the circuit shown in FIG. To form a composite circuit. Further, there is shown a dotted line of the inverter 56 that assumes a relationship between d and d ′ that simplifies the energy minimization analysis. For this circuit we derive functional and structural constraints. (1) Derivation of functional constraints. These constraints depend on the functionality of the gates used in the circuit. (2) Derivation of structural constraints. These constraints depend on the particular interconnect topology of the gates, but are independent of the gate type used in the circuit.

Functional Constraints: The signals on the path from the fault location to the main output have different values in the fault-free and faulty circuits. Therefore, additional binary variables are assigned to such signals. In our example, signals c and d are on the path from their fault location to the main output,
And we assign two binary variables c'and d ', respectively. Conceptually, this is visualized as the configuration of a faulty circuit copy by the addition of NAND gate 55, as shown in FIG. The energy function for the modified circuit is given by the sum of the energy functions for gates c, d and d '(the gate is addressed by the name of its output signal). Furthermore, the signals c and c'are constrained to take the logical values 1 and 0 respectively. All functional constraints are determined from the circuit's netlist in a time complexity that is linear in many signals.

Structural Constraints: We assign a binary variable S _x , called the path variable, to every signal x on the path from the fault location to the main output. This variable takes a logical 1 only when a fault on x is observable at its primary output. In our example, the signals c and _d are assigned the binary variables S _c and S _d . There are two types of structural constraints here. Both are derived from the circuit's netlist in a time complexity that is linear in many signals. First, the input fault on the gate is observable only when the gate output fault can be observed. Note that the reverse need not be the truth.
In our example, if S _c = 1 then S _d
Must take the value 1. This constraint is as follows:

[0032]

[Equation 3]

It is expressed as follows. For a trunk fault to become observable, the fault must propagate through one or more branches. This case cannot be applied to the example here. Second, if the path variable associated with signal x is true, then signal x must take different values in the fault-free and faulty circuits. If the value of the faulty circuit is x ', then this constraint is

[0034]

[Equation 4]

It is expressed as an energy function of This condition cannot be expressed as a binary relation. For a fault to become observable, the path variables associated with the fault location and its primary output are constrained to be one. So in our example,
S _c = S _d = 1.

In summary, the functional constraints are as follows:

[0037]

[Equation 5]

Denoted as Structural constraints are

[0039]

[Equation 6]

It becomes

The sum of the functional and structural constraints is the energy function for the faulty circuit. The energy function of a digital circuit is the sum of energy functions for all gates. The test generation procedure consists of the following steps. That is, 1. Bring out functional and structural constraints on failures. 2. The TC of constraints that can be expressed in the implication graph is determined as a binary relation, and contradiction, identification,
Match locks and exclusions (the derivation of logical conclusions from TC is described later). If a conflict is detected,
The failure is redundant. If the signal value thus determined satisfies the energy function, we have a test. Otherwise, the subset of signal values determined up to that point will have some of the ternary terms as 2 because the ternary term becomes a binary term when any one of its variables has a known value. Reduce to a base. We include these terms in the TC and recalculate the logical conclusions. This process continues until there are no ternary terms that reduce to binary terms. 3. Make selections regarding unassigned decision variables.
This allows some of the ternary terms to become binary terms. 4. Include the new binary term in the TC and observe any discrepancies, identifications, fixations and exclusions. If there is a contradiction, we return to step 3 and make a binary choice. If the signal assignment satisfies the energy function, we have a test and stop. Otherwise, the ternary terms reduced to binary terms by signal assignment in the current combination are added to the transitive closure. We reduce this process to binary terms 3
Continue until there are no more binaries, then go to step 3.

Since we derive a test for an s-a-0 (stuck-at-0) fault on signal c, c = 1, c '
= 0, S _c = S _d = 1 and our constraint set is

[0043]

[Equation 7]

It becomes All terms are expressed as binary terms.

The resulting implication graph is shown in FIG. It consists of vertices for variables and their complements. Where the vertex set is

[0046]

[Equation 8]

It is The constraint ab = 0 is an arc

[0048]

[Equation 9]

A pair of binary relations, each represented as

[0050]

[Equation 10]

Can be expressed as Arcs from other terms are similarly derived.

FIG. 8 shows the transitive closure in the matrix form of the implication graph. This is calculated using standard graph-theoretical techniques or the preferred techniques shown in Figures 22-24. The following types of logical conclusions are indicated by binary terms, which are determined from TC as follows: That is: 1. Contradiction: Variable x is TC arc

[0053]

[Equation 11]

When consisting of, the values 0 and 1 must be taken at the same time. If this situation occurs before the start of the search process or after the search space has been implicitly exhausted, then the fault is redundant. If inconsistencies arise during the search process, we must return to our previous choice. 2. Fixed: TC is an arc for the variable x

[0055]

[Equation 12]

Not an arc

[0057]

[Equation 13]

It is fixed to the value c on condition that it consists of Similarly, if TC is an arc

[0059]

[Equation 14]

Instead of

[0061]

[Equation 15]

The variable x is fixed at 1 if it consists of 3. Identification: If TC consists of arcs (x, y) and (y, x), then a pair of literals must take the same value. 19-21 show a circuit 60 useful as an example of identification and how this property is used. It is an exclusive OR gate 61 having inputs a and b and output c, an exclusive NOR circuit 62 having inputs a and b and output d, and an OR gate having inputs c (c = 0) and d and output e. It consists of 63 and.

FIG. 20 is an implication graph of only a partial representation of the circuit. The rest of the circuit information is contained in inhomogeneous terms that are not eligible for inclusion in the implication graph because they are not binary related. The non-homogeneous term is

[0064]

[Equation 16]

It is From the implication graph, a = b and e = d, so the second of the two terms not included is

[0066]

[Equation 17]

And such terms are added to its implication graph, as shown in FIG. This graph is fixed

[0068]

[Equation 18]

Which requires that c equals 1. 4. Exclusion: This is a global dependency in which a pair of variables cannot take a value in a combination. If transitive closure is an arc

[0070]

[Formula 19]

If there are no other arcs between the variables x and y, then the combination x = 1 and y = 0 is eliminated. This is because such an arc

[0072]

[Equation 20]

This is because the above-mentioned combination does not satisfy this relationship.

As an example, the circuit 20 shown in FIG.
Consider the 0 part. This circuit includes a NAND gate 201 having inputs a and b and output d, and a NAND gate 202 having inputs a and c and output e. The outputs d and e are inputs to the OR gate 203, and the OR gate 203 has an output g. Input b
And c are inputs to the exclusive OR gate 204,
Its output is f. During test generation for a fault,
It is assumed that the signals g and f have been assigned the values 1 and 0, respectively, as shown. Due to such signal allocation, the functional constraint of the gates g and f is

[0075]

[Equation 21]

It is simplified to Functional constraints on gates d and e are:

[0077]

[Equation 22]

It is The implication graph for a binary term with these functional constraints is shown in FIG. If we compute the transitive closure of the implication graph, we will notice that the signals b and c form the identity or they must take the same value. Moreover, its transitive closure is a constraint

[0079]

[Equation 23]

An arc that means

[0081]

[Equation 24]

It consists of: Therefore, d + e = 1. Using the identification of the signals b and c and the condition of d + e = 1, the ternary terms abd = 0 and ace = 0 are simplified to ab = 0.

We include the constraint ab = 0 in the implication graph. The updated implication graph is shown in FIG. If we compute the transitive closure of the updated implication graph, we observe that the signals d and e are fixed at the value 1.

In general, if the transitive closure is a variable

[0085]

[Equation 25]

Arcs, not other arcs between

[0087]

[Equation 26]

The constraint between the variables x and x, if

[0089]

[Equation 27]

It is Therefore, x and y can take the values of any combination except the combination x = 1 and y = 0. this is,

[0091]

[Equation 28]

Which means that the ternary term is further simplified.

Continuing the test generation process for the s-a-0 fault on signal c in FIG. 5, the transitive closure shown in FIG.

[0094]

[Equation 29]

, We therefore have a fixed a = 0. Similarly, b = d '= 1 and d = 0. Since all major input signals have been determined, there is no need for a search phase. Vectors a = 0 and b = 1 are tests for fault c s-a-0 in the circuit shown in FIG.

The techniques of implications, justification, static learning, dynamic learning and dominator activation are implicitly included in the TC method.
As will be explained later, the logical dominator, that is, the dominant factor, is implicitly activated. Furthermore, it is possible to detect difficult redundancies that cannot be detected by other techniques.

Implicit Implications and Justification Consider the circuit shown in FIG. This is NA
It includes ND circuits 30, 31 and 32. NAND circuit 30 has inputs a and b and output d, NAND circuit 31 has inputs b and c and output e, and NA
The ND circuit 32 has inputs d and e and an output f. The energy function for this circuit, which is the sum of the energy functions for gates d, e and f, is the following binary term:

[0098]

[Equation 30]

It consists of:

Those binary terms are the IG shown in FIG.
It is represented in. Also, this graph occurs to have its own TC. The TC adjacency matrix is shown in FIG.

Assume d = 0. The forward implication is f = 1 and the justification is a = b = 1. This is implicitly determined in the TC method. That is: 1. Arc

[0102]

[Equation 31]

The relationship d to the IG of FIG.
= 0 is included. The updated IG is shown in FIG. 2. Construct the TC of the updated implication graph. The updated TC in matrix form is shown in FIG.
3 is shown. We can directly derive the updated transitive closure from the TC shown in FIG. 11 as follows. Arc

[0104]

[Equation 32]

The addition of is the ancestor of d

[0106]

[Expression 33]

Allows to reach all descendants of. d
The ancestor or vertex of

[0108]

[Equation 34]

Is the vertex with 1 in column d in FIG. 11, and

[0110]

[Equation 35]

The descendants of vertices a, b and f are columns

[0112]

[Equation 36]

It is a vertex having 1 in 1. For example, in FIG.
And a vertex that can reach only d and e

[0114]

[Equation 37]

Is now the vertex

[0116]

[Equation 38]

Can also be reached (see FIG. 13). 3. Draw logical conclusions from the updated TC of FIG. There is an arc

[0118]

[Formula 39]

There is an arc

[0120]

[Formula 40]

There is no. Thus, fixed a = 1 is an arc

[0122]

[Formula 41]

(This arc is related

[0124]

[Equation 42]

It is the only value that can satisfy the above). Similarly, we have b = f
It can be concluded that = 1.

Implications and Transitive Closure Over Justification Consider the case where the signal f in the circuit of FIG. 9 is assigned the value 1. This is the arc for IG leading to FIG.

[0127]

[Equation 43]

[0128] is added. Transitive closure fixes the signal b to a logical 1 as described below. Of particular note is that, for f = 1, the conventional implication and justification procedure cannot conclude that the signal b should be fixed at 1.

If f = 1, the three variable term dcf in the failure function of the gate f becomes dc. Relationship

[0130]

[Equation 44]

The inclusion of is the next arc for IG in FIG.

[0132]

[Equation 45]

[0133] is added. The updated IG is shown in FIG. 14 and given in FIG. 15 the corresponding TC adjacency matrix. As explained previously, we can also construct an updated TC by incrementally changing the TC shown in FIG.

The updated TC (FIG. 15) is

[0135]

[Equation 46]

It has 1 in. Thus,

[0137]

[Equation 47]

Means b. But b

[0139]

[Equation 48]

Does not mean. Hence the arc

[0141]

[Equation 49]

Is the relationship

[0143]

[Equation 50]

Is shown. From here, b must be fixed at 1 as a result of the initial fixation of f = 1.

Implicit Activation of Physical and Theoretical Dominators Dominators are gates that propagate through a fault so that it can be observed. We call such a gate a physical dominator. As an example, consider the stuck-at-0 fault b in the circuit of FIG. It is easy to see that the fault must propagate through the gate to be observable at the output of the circuit, thus f is matched as a physical dominator. If signal a is assigned the value 0, then the fault must propagate through gate c to reach the output. Here, the gate c is a logical dominator.

The TC method implicitly matches and activates many physical and logical dominators. We demonstrate these features through examples. The physical dominator of the fault b s-a-0 is such a path variable:

[0147]

[Equation 51]

It is purely determined from its structural constraints, as represented by: The last constraint ensures that the trunk fault on b propagates to either or both of the signals d, e in order to be observable at its primary output. Here, S _b is initially set to 1 since it is assumed that the fault on trunk b is observable. This is a ternary term

[0149]

[Equation 52]

Binary relation

[0151]

[Equation 53]

We reduce to Such a binary TC fixes S _f to 1. Therefore, the gate f is a dominator. Even if this circuit is embedded in a large circuit, f will be matched as a fault dominator.

As an example of identifying and activating a logical dominator, consider the case where signal a is set to a logical value of zero.
Since the failure on trunk b cannot propagate to gate d,
The gate e becomes a logical dominator. Furthermore, the signal c must be set to 1 to activate the logical dominator e. The identification of e as a logical dominator and the assignment e = 1 implies that by the TC method even if the circuit is part of a large circuit and there is a multipath from signal f to the main output. It will be decided at home.
To see this, we construct the energy function for the faulty circuit. Conceptually, we can visualize the faulty circuit as the modified circuit shown in FIG. The circuit shown in FIG. 16 has a NAND gate 41.
~ 46, various inputs and outputs, and failure bs-a-0
And where b is an input to NAND gates 41 and 42. Include functional and structural constraints in the energy function of the fault circuit to
By calculating the graph and TC, S _e = 1 and c
= 1 is obtained.

Redundancy Identification Now consider the circuit shown in FIG. 17 with a stuck-at-1 fault k. The circuit here consists of two inverters 60 with inputs a and b and outputs c and d respectively.
And 61 and NAND gates 62, 63, 64 and 65.
, Of which NAND gate 62 has inputs a and b and output e, NAND gate 63 has inputs a and d and output f, and NAND gate 64 has input c.
And b and output g, and NAND gate 65
Has inputs c and d and output h. It also
NAND gate 67 with inputs e and f and output i
And NAND gate 6 with inputs g and h and output j
Including 8 and. Finally, it includes a NAND gate 69 with inputs i and j and output k. By simulating the circuit for all possible combinations of a and b, the fault k s-a-1 is verified to be redundant. Since the fault is on the main output, we simply have to justify the value 0 on signal k. The binary term derived from the energy function of the circuit is shown in FIG. The energy function for gate k is k = 0, so

[0155]

[Equation 54]

It is Therefore, the gate k contributes the terms i = 0 and j = 0 to the energy function of the whole circuit. Binary terms contributed by other gates are similarly derived.

If we represent such terms as IG and calculate TC, then both arcs

[0158]

[Equation 55]

Is given to TC. This shows a contradiction,
Therefore, the assignment of signal values does not satisfy the energy function for the circuit with k = 0. It can be concluded that this fault is redundant.

As another feature of the invention, we have developed a novel procedure for computing transitive closure, shown as step 105 in FIG. 2, which is preferred for the known procedure. The basic steps of this procedure are shown in the flow chart of FIG.

The flowchart of FIG. 22 includes three basic steps. The first step 140 involves computing the strongly connected components or components of the implication graph derived in the preceding step 103. In strongly connected components, each vertex in this set is reachable from each other vertex in the set. Step 140 will be discussed in more detail later. Once the strongly coupled components have been determined, a directed graph (DAG) that does not include closed cycles is constructed therein, as shown by step 141, and then as shown in step 142. Any fixation or exclusion is decided. The operations included in step 141 are performed by Addison-Wesley Publishing Co., Reading, MA (197).
4), A. V. It is described in the book entitled "Computer Algorithm Design and Analysis" by AHO et al. Step 142 has been previously described.

An exemplary process for determining strongly bound components is described with reference to the flow chart of FIG.

This process begins at step 155 by initializing the workspace to form three arrays of size n, the number of vertices in the implication graph, each of its transitive closures are to be calculated. Start with The array is a visited array for the visited vertices,
Another thing called a low link array, Dfs-no
All of them are initially set to zero, including the third one, which is the (depth-first search) number.

Then, in step 156, one is selected as a vertex that has not yet been visited, and in step 157,
Update the workspace, mark the vertices being traversed as true, set V's lowlink and V's Dfs-no to Df
Set to be equal to the s number.

In step 158, vertex V is pushed onto two separate stacks called the dfs stack and the recursive stack.

Then, in step 159, the vertex child on the top of the induction stack is chosen. In step 160, if the top of this stack has already been cycled, we update the rowlink value appropriately, as indicated by step 161. If not, the vertex V is reclassified as ω in step 162, after which we return to step 157.

After step 161, if there is another child of the vertex on top of the induction stack, step 162
We return to step 159, as indicated by. If there are more children, we are dfs
Process the stack. For this step 163,
More details will be described with reference to the flow chart of FIG.

After such processing at step 163, we pop the induction stack at step 164. If it is already empty (step 165),
The process stops. Otherwise, the process returns to step 159.

Details of the steps for processing the dfs stack are shown in the flow chart of FIG. fundamentally,
The function of step 163 separates all the strongly connected vertices and stores them in a file called the SCI list (hereinafter referred to as the scc list), from which it feeds to step 164. To be done.

In step 170, it is determined whether the low link at vertex V is equal to a number greater than n. If so, in step 171, we use dfs until vertex V is removed from this stack.
Pop the stack. In step 172 we determine whether the low link of vertex V is equal to Dfs-no of vertex V. If so, proceed to step 173 and set the scc list to empty. next,
In step 174, pop the dfs stack until vertex V is at the top of the dfs stack. All vertices leaving the dfs stack are step 174,175,
Form a subset of vertices that are strongly connected, as given by 176, 177 and 178. These steps use the property that if a vertex is popped from the stack and it is not equal to V, it is included in the scc list. More specifically, in step 172, we determine if the rowlink of vertex V is equal to its Dfs-no. If so, steps 174, 175 and 1
At 76, we process the vertices on the top of the dfs stack. At step 174, we pop vertex x from the top of the dfs stack. Then we rollin and D of the vertex x and its complement
Reassign fs-no to a number greater than n. Here we choose MAXINT to be a number greater than n. In step 175 we mark vertex x as cycled and include vertex x in the list of vertices forming a strongly connected component that includes vertex V. Then, in step 177,
If a vertex on top of the dfs stack (step 17
Given 6) equal to vertex V, we determine as vertex V all vertices in that same strongly connected component. If not, we return to step 176 and repeat steps 175, 176 and 177.

The particular examples described herein are merely illustrative of the basic principles of the invention and various other embodiments are conceivable consistent with the basic principles of the invention.

[0172]

According to the present invention, in the VLSI circuit test, an input vector set suitable for efficiently testing a specific VLSI logic circuit including a binary value for finding a fault and eliminating redundancy is provided. The method to generate was realized.

[Brief description of drawings]

FIG. 1 illustrates the basic procedure currently in widespread use for developing a vector set to test a list of the most anticipated faults in a VLSI circuit.

FIG. 2 is a flow chart of an exemplary embodiment of the method of the present invention used to generate a vector for testing a particular fault.

FIG. 3 is a flow chart of an exemplary embodiment of the method of the present invention used to generate a vector for testing a particular fault.

FIG. 4 is a diagram showing a positional relationship between FIGS. 2 and 3;

FIG. 5 shows a circuit containing a fault for which a test vector is drawn.

FIG. 6 shows a modified version of the circuit of FIG. 5 useful in deriving test vectors in a complex circuit for a given fault.

FIG. 7 shows an implication graph for the circuit of FIG.

8 shows the transitive closure of the implication graph of FIG. 7.

FIG. 9 is a diagram showing another circuit example.

10 is a diagram showing an implication graph of the circuit of FIG. 9. FIG.

11 is a diagram showing the transitive closure of the implication graph of FIG.

12 shows an implication graph of a modified version of the circuit of FIG.

13 shows the transitive closure of the implication graph of the modified version of FIG.

14 shows an implication graph for the circuit of FIG. 9 with allocated outputs.

15 is a diagram showing the transitive closure of the implication graph of FIG.

FIG. 16 shows a modification of the circuit shown in FIG.

FIG. 17 is a diagram showing an example of a circuit having a redundancy fault.

FIG. 18 shows a table of binary terms obtained for the special case of the circuit in FIG.

FIG. 19 is a diagram for explaining the concepts of identification and fixation.

FIG. 20 is a diagram for explaining the concepts of identification and fixation.

FIG. 21 is a diagram for explaining the concepts of identification and fixation.

FIG. 22 is a flow diagram of a preferred technique for transitive closure computation for use in the processes described in FIGS. 2 and 3.

FIG. 23 is a flow diagram of a preferred technique for computing transitive closure for use in the processes described in FIGS. 2 and 3.

FIG. 24 is a flowchart of a preferred technique for computing transitive closure for use in the processes described in FIGS. 2 and 3.

FIG. 25 is a diagram showing exclusionary logical conclusions.

26 is a diagram showing an implication graph of the circuit of FIG. 25. FIG.

FIG. 27 shows an updated implication graph after inclusion of basic constraints.

[Explanation of symbols]

 10 Test Generator 11 Fault List 12 Circuit Netlist 13 Test Vector 14 Fault Simulator 15 Update Fault List Means

Front Page Continuation (72) Inventor Biswani Agrawal United States 07974 Murray Hill, New Jersey Colchester Road 40

Claims (8)

[Claims] 1. A method of processing a current potential term of an energy function to determine a test vector for detecting a fault in a logic circuit, the identification of a composite circuit representing a logic circuit with and without a fault. Finding the implication set based on the relation of terms containing the potential terms of, i.e., the relations resulting from the assignment of potential values to the variables in the potential terms, and obtaining the transitive closure of the implication set. A step of using the transitive closure to make a logical inference on the composite circuit; updating the implication set to reflect the logical inference; and the implication set includes inconsistent implications. Until there is no further logical inference, and the step of obtaining the transitive closure and its inference. Method characterized by comprising the step of using the closure, and a step of repeating the steps of updating the implications set, the. 2. The assigned potential value is one of two possible values, and further maintaining a track of potential values assigned to previously processed potential terms, and For each of the potential terms of and the previously processed potential term, determine whether the potential term already had both of the two possible values assigned to it, and if not, claim Repeat step 1 to assign the other of the two values, and if no potential term is found for it, repeat the steps of claim 1 to ensure that the other of the two values is inconsistent. Conditionally determining that the fault is redundant. 3. The step of using transitive closure to make a further logical inference further comprises the steps of making a logical inference about fixation, making a logical inference about exclusion, and making a logical inference about identification. The method of claim 1, further comprising: 4. The step of updating the implication set comprises applying the logical inference to a non-homogeneous positive-form quasi-function of an energy function, and the logical inference of the non-homogeneous positive-form quasi-function. Updating the homogeneous positive-form quasi-function as indicated in the application, updating the implication set as indicated in updating the homogeneous positive-form quasi-function of the energy function,
The method of claim 1, comprising: 5. Prior to assigning any potential value to the term of the composite circuit, based on the relation of the term,
A step of finding the previous implication set, a step of obtaining the previous transitive closure of the previous implication set, and a step of using the previous implication set to reflect the logical inference of the previous , Or more, the steps of using the previous transitive closure, updating the previous implication set, and updating the previous transitive closure until no further logical inference is made. The method further comprising the step of: if the inconsistency is reached, the failure is determined to be redundant and the process is terminated, or the step of claim 1 is continued. The method according to item 1. 6. A method for generating a test vector consisting of a set of signal values for detecting a given fault in a logic circuit, wherein the decision regarding the signal value is a transition related to an implication graph model of the circuit. A method in which the closure computation indicates that the decision is to be made from a class that includes fixed, identified, excluded or inconsistent, Combining with a version to form a composite function version of the digital circuit; (b) deriving an energy function of the composite function version and separating it into binary and ternary terms; (c) the energy. Forming a binary term implication graph of the function, and (d) implementing the Calculating a transitive closure of the application graph, and (e) determining some fixation, identification, exclusion and contradiction from the transitive closure and using any found one,
Reducing some ternary terms of the energy function to new binary terms, and (f) forming the new implication graph by adding the new binary terms to the previous implication graph; g) calculating a new transitive closure based on the new implication graph, and (h) as long as ternary terms can be removed from the energy function,
If steps (e), (f) and (g) are repeated, (i) if there are no ternary terms remaining, then a list of literals is retrieved, and (j) if there are ternary terms remaining, The unassigned signal is fixed to a specific value, and steps (c), (d), (e), (f), (g), (h) and (i) are repeated, while the ternary term is removed. Repeat any redundancy fixation, identification, elimination and inconsistency determination for as long as it is followed by the step of deriving a list of variables, and (k) the unassigned signal if ternary terms remain. Fixed to opposite values and repeating steps (c), (d), (e), (f), (g), (h) and (i), and (l) from the list of literals , Pull the test vector for that fault A step of issuing. 7. The method of claim 6, wherein the method derives a set of test vectors each designed to detect different faults in a given fault set, and is repeated for each different fault in the fault set. A method comprising: 8. A method of testing a digital integrated circuit for a given fault set, wherein each test vector of a test vector set derived in accordance with the method of claim 7 for the given fault set is in turn. Applying to the input of the.