JPH07245765A - Reproducing device for magnetically recorded video signal - Google Patents

Abstract

PURPOSE:To realize high speed fast forward reproduction or the like at low cost with high image quality without any disturbance in a color signal by interpolating or interleaving horizontal scanning lines so as to correct the number of the scanning lines thereby correcting the phase of the color signal. CONSTITUTION:The reproducing device for a video signal recorded magnetically is provided with means 114, 115 using memories (line memories) 113A, 113B storing video signals by nearly two horizontal scanning lines to implement time base conversion and interleaving or interpolation of scanning lines, a means detecting phase disturbance of a color signal of an input signal to correct the disturbance, and means 121, 122, 126, 127 calculating and correcting the phase disturbance of the color signal resulting from the scanning line interleaving or interpolation. Thus, a deviation in the frequency and number of scanning lines of a reproduced video signal caused in the case of fast feeding reproduction or rewinding reproduction at a high speed is corrected, a track jump and the disturbance of phase due to the scanning line interleaving or interpolation are corrected, then the fast feeding reproduction or rewinding reproduction at a high speed without disturbance in the color signal is implemented at a low cost.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reproducing apparatus of a magnetically recorded video signal, and particularly to a monitor of a reproduced video signal without disturbing a color signal at the time of high speed reproduction of tens or hundreds of times of recording. The present invention relates to a video signal reproducing device that enables the above.

[0002]

2. Description of the Related Art As an example of the prior art similar to such an apparatus, Japanese Patent Publication No. 63-51592 or Japanese Patent Laid-Open No.
For example, the method described in JP-A 1-21075 is available. The outline of these conventional techniques will be described with reference to FIGS. 15 and 16. FIG. 15 and FIG. 16 are explanatory diagrams each showing an example of a head locus when a rotary head scans and reproduces a video track recorded obliquely with respect to the traveling direction of the magnetic tape.

In FIGS. 15 and 16, 1501,
1601 is a magnetic tape, 1502, 1503, 160
2, 1603 are track patterns recorded on the magnetic tape, 1504, 1505, 1604, 1605 are loci scanned by the head during reproduction, and 1506, 1606 are differences generated between these head scanning loci.

The scanning locus at the time of recording is 1 in FIG. 15 and FIG.
504 and 1604. In FIG. 15, for example, when the tape 1501 is stopped during reproduction, the scanning locus of the head becomes a locus 1505, and the portion (trajectory length) scanned by the head increases by the difference 1506. Conversely, in FIG.
When the tape 1601 is run at twice the speed, the scanning locus of the head becomes the locus 1605, and the portion (trajectory length) scanned by the head is reduced by the difference 1606.

As described above, in general, when reproducing at the double speed number N, one track corresponds to one field,
Since the track length (scanning locus of the head) increases or decreases, the number of horizontal scanning lines forming one field increases or decreases. This increase / decrease is α × (N−1), where α is the number of horizontal scanning lines corresponding to the differences 1506 and 1606.
Indicated by. When N is larger than 2, that is, in the case of fast-forward reproduction, the number of horizontal scanning lines forming one field decreases and the horizontal synchronizing frequency decreases. On the other hand, when N is smaller than 0, that is, in the case of rewinding reproduction, the number of horizontal scanning lines forming one field increases and the horizontal synchronizing frequency increases.

Therefore, the method described in Japanese Patent Publication No. 63-51592 is adapted to match the horizontal synchronizing frequency of the reproduced signal with that at the time of recording by changing the rotational speed of the rotary head during high speed reproduction.

Further, in the method disclosed in Japanese Patent Laid-Open No. 01-221075, the reproduction signal is temporarily stored in the field memory, and then the horizontal scanning line is interpolated or thinned to correct the increase or decrease of the horizontal scanning line to reproduce the reproduction signal. The horizontal and vertical sync frequencies are matched to those at the time of recording.

[0008]

When performing high-speed reproduction by these conventional techniques, one field is constituted by a method of correcting the rotational speed of the rotary head and reproducing so that the horizontal synchronizing frequency matches that at the time of recording. The vertical synchronizing frequency changes as the number of horizontal scanning lines increases or decreases, but due to the limit of the sync pull-in performance of the current television, the maximum speed can be increased to about 20 times.

In addition, the method of interpolating and thinning out horizontal scanning lines by the field memory requires a large capacity memory device, which makes the system very expensive.

In addition, the azimuth angle of the head is changed for each track in order to increase the recording density, and the phase of the color signal is changed for each horizontal scanning line in order to remove the interference of the adjacent tracks. In the reproducing apparatus, since a rotary head reproduces across a track during high-speed reproduction, a phenomenon occurs in which the reproduced signal is not colored correctly.

An object of the present invention is to overcome the above-mentioned problems of the prior art, to monitor an image even at a high speed reproduction of about 20 times or more, the system cost is low, and the reproduced signal has a correct color. Another object of the present invention is to provide a reproducing apparatus for a magnetically recorded video signal that enables the user to play the video signal.

[0012]

To achieve the above object, according to the present invention, a memory (line memory) capable of storing video signals of about two horizontal scanning lines is used for time axis conversion and thinning or interpolation of scanning lines. A means for performing, a means for detecting and correcting the phase disturbance of the color signal of the input signal, and a means for calculating and correcting the phase disturbance of the color signal by thinning out or interpolating the scanning lines described above are used to reproduce the magnetically recorded video signal. Installed in the device.

[0013]

By the above means, it is possible to correct the deviation of the frequency and the number of scanning lines of the reproduced video signal, which occurs when fast-forward reproduction or rewinding reproduction is performed at high speed, and track jump and disturbance of the color phase due to scanning line thinning or interpolation. Since high-speed fast-forward reproduction or rewind reproduction with high image quality without color distortion can be performed at low cost (compared to field memory, line memory is less expensive because it requires less memory capacity). You can

[0014]

First, the principle of time axis conversion in the present invention will be described. When playing back the magnetic tape faster or slower than during normal recording and playback while the magnetic head is rotated at the same speed as during normal recording and playback,
The magnetic head draws a locus over a plurality of tracks recorded on the magnetic tape.

The frequency of the vertical synchronizing signal of the video signal reproduced in this manner is the same as that during normal recording and reproducing, but the number of horizontal scanning lines included in one vertical synchronizing period increases or decreases, that is, the horizontal scanning line. The frequency of the sync signal changes. Specifically, in the case of rewinding reproduction, the locus scanned by the head becomes long as shown in FIG. 15, so that the number of horizontal scanning lines increases and the frequency of the horizontal synchronizing signal increases. On the contrary, in the case of fast-forward reproduction, the locus of scanning by the head becomes short as shown in FIG. 16, so that the number of horizontal scanning lines is reduced and the frequency of the horizontal synchronizing signal is lowered.

When the fast-forwarding or rewinding speed increases, the change in the frequency of the horizontal synchronizing signal also increases. Therefore, when the change exceeds the pull-in range of the monitor for displaying the image, the image can be displayed. It's gone.

According to the present invention, a memory capable of storing video signals for several horizontal scanning lines is used to perform frequency conversion of a video signal reproduced by high-speed fast-forward or high-speed rewind as described above, and a horizontal synchronizing signal It corrects the amount of change in frequency. At the same time, the number of scanning lines is corrected by performing interpolation or thinning of horizontal scanning lines. Further, the phase of the color signal is corrected to solve the problem such as color disappearance on the display screen.

In the frequency conversion of the video signal, the video signal reproduced from the magnetic tape is written in the memory in synchronization with the reproduced synchronization signal and is read in accordance with a clock from an oscillator which oscillates at a constant stable frequency. Do that. Specifically, in the case of fast-forward playback, the frequency of the horizontal synchronizing signal of the video signal to be played back has dropped, so writing to the memory is performed in accordance with the low-frequency clock corresponding to the change, and this is kept constant. Read according to the frequency clock. Since the number of horizontal scanning lines is reduced, the scanning lines are interpolated.

On the other hand, in the case of rewinding reproduction, since the frequency of the horizontal synchronizing signal of the reproduced video signal is increased, writing to the memory is performed in accordance with the high frequency clock corresponding to the change, and this is changed. Reading is performed according to a clock having a constant frequency. Since the number of horizontal scanning lines is increasing, the scanning lines are thinned out.

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit block diagram showing one embodiment of the present invention. In FIG. 1, 141, 142, 143,
144 magnetic heads, 102 a rotary cylinder, 1
Reference numeral 03 is a head switching circuit, 104 is a reproduction amplifier, 105 is a synchronization signal demodulation circuit, 106 is a phase comparison circuit, 107 is a filter circuit, 108 is an addition circuit, 109 is a voltage controlled oscillator, 110 is a frequency dividing circuit, and 111 is A / A D (analog / digital) converter, 112 is a delay circuit, 113A and 113B are memories, 114 is a write control circuit, and 115 is a read control circuit.

In addition, 116 is a fixed oscillator circuit and 117
Is a multiplexer, 118 is a D / A (digital / analog) converter, 137 is a dropout correction circuit, 11
9 is a luminance signal processing circuit, 120 is a color signal extraction circuit, 12
1 is a color phase shift control circuit, 122 is a phase shift and frequency conversion circuit, 123 is an adjacent interference removal filter circuit,
Reference numeral 124 is an adder circuit, 125 is a monitor device, and 126 is a track jump phase detection circuit.

Further, 127 is a memory control phase shift calculation circuit, 130 is a reel control circuit, 131 and 132 are reel drivers, 133 is a tape supply reel, 134 is a tape take-up reel, 135 is a voltage generation circuit, and 136 is a magnetic tape. Is. Furthermore, 150-167, 309-31
2, 409 to 412 are electric signals. The outline of the operation will be described below.

Rotating cylinder 1 in contact with magnetic tape 136
Magnetic heads 141 and 14 mounted on the head and rotating
2, 143 and 144 pick up a reproduction signal from the magnetic tape 136. This is switched by the head switching circuit 103 and amplified by the reproduction amplifier 104 to obtain a reproduction signal which is temporally continuous. Here, the head switching circuit 10
The operation of No. 3 will be described with reference to FIG.

FIG. 10 shows the magnetic head 141 shown in FIG.
1 to 144 and a head switching circuit 103. FIG. In FIG. 10, 1001, 1002,
1003 is a switch circuit, 1004 is a comparison circuit, 100
A switch control circuit 5 controls the switch circuit 1003. Other parts and electric signals which are the same as those in the embodiment of FIG. 1 are designated by the same reference numerals.

The magnetic heads 142 and 143 are wide magnetic heads for reproducing a video signal recorded in the standard recording mode, and have different azimuth angles (indicated by + and-in FIG. 10). On the other hand, the magnetic heads 141 and 1
Reference numeral 44 denotes a narrow magnetic head for reproducing a video signal recorded in the long-time recording mode, and the azimuth angles are also different from each other (indicated by + and − in FIG. 10).
The magnetic heads 14 having different azimuth angles and widths are provided.
The set of 1 and 142 and the set of magnetic heads 143 and 144 are mounted on the rotary cylinder 102 at positions separated by about 180 degrees.

The switch circuits 1001 and 1002 operate in conjunction with each other, and depending on which one of the above-mentioned two magnetic heads is in contact with the magnetic tape 136, the reproduction signal on the contacting side is selected. One cylinder 102
It switches every time it rotates 80 degrees. This switching signal 156 is a magnet (not shown) attached to the rotary cylinder 102.
It is generally obtained by detecting the magnetic field generated by the sensor with a sensor (not shown).

The switch circuit 1003 is controlled by the signal 158 from the switch control circuit 1005. Signal 15
Reference numeral 9 is a signal indicating the running state of the tape, and signal 160 is a signal indicating whether the recording of the tape being reproduced is in the standard mode or the long time mode. During normal tape reproduction, the magnetic heads 142 and 14 having a wide width according to the recording mode are used.
The switch circuit 1003 is controlled by selecting either 3 or the narrow magnetic heads 141 and 144.

In the fast-forward reproduction or the rewind reproduction which is the object of the present invention, since the reproduction is performed across a plurality of tracks having different azimuth angles, the four magnetic heads 1 are used.
Playback is performed using all 41 to 144. For example, when the magnetic heads 141 and 142 are in contact with the magnetic tape 136, the switch circuits 1001 and 1002 select signals from the upper side of the drawing, that is, the magnetic heads 141 and 142.

The comparison circuit 1004 outputs the result of comparing the levels of these two signals to the switch control circuit 1005, and controls the signal with the higher level as the switch circuit 1003 selects. The transition of the control signal 158 is performed in synchronization with the timing pulse signal 157. The signal 157 is a signal generated by the write control circuit 114 described later, but it is preferable that the timing is slightly before the horizontal synchronizing pulse.

Discontinuity of the modulation phase due to head switching causes a demodulation error in the demodulator in the subsequent stage, and it takes some time to recover. When the discontinuity of the modulation phase is applied to the horizontal sync pulse, the sync demodulation circuit 105 in the subsequent stage cannot correctly demodulate the sync signal and the circuit of this embodiment malfunctions or the sync circuit of the monitor device 125 malfunctions. Sometimes.

In normal reproduction, switching of the head is performed only once in one vertical period, so there is no problem. However, in fast-forward reproduction or rewind reproduction, which is a target of the present invention, the head crosses a plurality of recording tracks. Since track jumps occur frequently, it is preferable to switch the heads before the horizontal synchronizing signal and in a period when there is no video signal.
Although not shown in FIG. 1, if a timing pulse including this head switching period is generated and this period is replaced by a signal one horizontal scanning line before in the dropout correction circuit 137 in the subsequent stage, the modulation error is completely eliminated. Can be turned off.

Description will be returned to FIG. The reproduction signal 155 thus obtained is amplified by the reproduction amplifier 104 and then applied to the synchronization signal demodulation circuit 105 to extract the synchronization signal. On the other hand, after being input to the A / D converter 111 and converted into a digital signal, the time axis conversion is performed by passing through a memory circuit.

First, the former synchronization signal demodulation circuit 105
The sync signals extracted in step 106 are elements 106, 107, 10
It becomes the reference signal of the phase locked loop composed of 8, 109 and 110. That is, the high frequency clock signal oscillated by the voltage controlled oscillator 109 is frequency-divided by the frequency dividing circuit 110, and the frequency and phase are controlled by the phase comparison circuit 106 so as to have a constant phase with the extracted synchronizing signal.

At this time, the signal band-limited by the filter circuit 107 is added by the adder circuit 108 to the voltage generation circuit 135.
The voltage-controlled oscillator 109 is added with the signal generated from
Of the phase comparator circuit 106 so that the two inputs of the phase comparator circuit 106 are in a phase locked state.

As described above, a signal that locks the phase of the synchronizing signal recorded on the magnetic tape 136, that is, a signal that changes in frequency in the same manner as the frequency of the synchronizing signal can be obtained. Since the reproduction speed targeted by the present invention is extremely high, a voltage that roughly changes the applied voltage of the voltage controlled oscillator 109 according to the tape speed is generated in the voltage generation circuit 135, and this is added to the phase lock voltage of the synchronization signal. Voltage-controlled oscillator 1 added by circuit 108
By assigning it to 09, a desired time axis conversion operation can be performed in a very wide range.

Here, a description will be given of the portion that drives the magnetic tape. As a drive system, there are a capstan drive system in which a tape is driven between a pinch roller and a capstan (not shown) and a reel drive system in which a reel stand is driven. Here, the reel drive system will be described.

In the reel drive system, the supply or take-up reel is directly driven by a separate or single motor, so that the driving force is high and it is suitable for high speed tape running such as rewinding and fast feeding. In the case of a single motor, which reel the driving force is transmitted to is mechanically switched. Although each drive source is often provided as in this example, it does not matter which is the essence of the present case, so either one may be used. What is needed is a control system that can obtain a stable head touch in order to see the playback screen at high speed.

Such an example already exists as a known technique (for example, Technical Report of the Institute of Television Engineers of Japan, August 1990).
Moon, vol. 14, No. 41, pp. 7-12, tape drive system for composite digital VTR (D2)). These controls are often performed by a microcomputer, but in the present example, they are collectively referred to as the reel control circuit 130.

The reel control circuit 130 controls the voltage generation circuit 135 according to the number of rotations of the reel, and in the case of fast-forward reproduction, the frequency of the horizontal synchronizing signal to be reproduced is lowered, so that it is generated so as to follow it. The voltage is lowered and the oscillation frequency of the voltage controlled oscillator 109 is lowered. In the case of rewinding playback, the frequency of the horizontal sync signal that is played back increases, so
The generated voltage is increased so as to follow this, and the oscillation frequency is increased. By these operations, the horizontal synchronizing frequency and the oscillating frequency are always kept at a constant ratio according to the reproduction speed.

On the other hand, the video signal converted into a digital signal is delayed by the delay circuit 112 for a predetermined time. This is to make the break (timing of the head address of the memory) of the video signal when writing the video signal in the subsequent memories 113A and 113B in units of horizontal scanning lines before the horizontal synchronizing pulse. This delay time depends on the synchronous demodulation circuit 1.
It is determined in consideration of the time required to demodulate the synchronization signal in 05. Further, if the delay time is configured to be adjustable, it is possible to adjust the break of the video signal outside the display area according to the variation of the display area of the monitor device 125.

The video signal delayed by the memory 112 is selectively written to the memory 113A or B.
The write control circuit 114 generates a control signal necessary for writing to the memory, such as a write address signal, in synchronization with a clock signal whose frequency changes according to the reproduced synchronization signal.

The read control circuit 115 generates a control signal necessary for reading the memory, such as a read address signal, in synchronization with a clock signal of a constant frequency generated by the oscillator 116, and supplies the control signal to the memory 113A or 113B and a multiplexer. By controlling the circuit 117, data is selectively read from the memory 113A or 113B.

Memory 1 in writing and reading by the write control circuit 114 and the read control circuit 115 described above.
By the control of the selection operation of 13A and 13B, the above-mentioned interpolation and thinning of the horizontal scanning line are performed. This operation will be described below.

First, the memories 113A and 113B will be described. Each of these memories has a storage capacity capable of storing a video signal for one horizontal scanning line, and is of a type capable of independently writing and reading data asynchronously. In this embodiment, the address signal is given from the outside. Some memories that serially access data do not need to be provided with an address signal if a timing signal for accessing the start address is given. Supplies the address to the memory means, which is substantially the same as the present embodiment.

In this embodiment, the memories 113A and 113B basically operate as so-called time base collectors. That is, two memories have one horizontal scanning line (1H).
It is accessed alternately every time. FIG. 2 is a diagram schematically showing this state. That is, FIG. 2 is an explanatory diagram showing a state in which two memories are accessed alternately for each horizontal scanning line (1H).

In FIG. 2, the number lines 201 and 202
Indicates the addresses of the memories 113A and 113B, respectively, and the left end indicates the start address and the right end indicates the end address. Since the two memories are accessed sequentially and alternately, the entire address can be represented as a circle 205 connecting the number lines 201 and 202 with the dotted portions 203 and 204.

Here, the upper half of the circle 205 is the memory 113.
The address of A is shown, and the lower half shows the address of the memory 113B. A white arrow 206 indicates a write address at a certain point in the memory, and a black arrow 207 indicates a read address at a certain point in the memory. Therefore, in this embodiment, the write address, that is, the white arrow 206 and the read address, that is, the black arrow 207, can be expressed as moving clockwise on the circumference of the circle 205. .

When fast-forward reproduction or rewinding reproduction is performed, the voltage-controlled oscillator 1 according to the speed as described above.
The frequency of the write clock, which is the output of 09, changes.
Therefore, when the read and write operations of simply accessing the two memories 113A and B sequentially and alternately are performed, the write address of the memory overtakes the read address, or conversely, the read address overtakes the write address. Occur.

When such an overtaking phenomenon occurs, video signals of different horizontal scanning lines are read before and after the overtaking point, so that different video signals are displayed on the same horizontal scanning line on the time axis. Will end up. Further, since this video signal is a signal subjected to frequency modulation, a discontinuity point of the modulation phase is generated, so that an interference phenomenon due to a demodulation error of the demodulator occurs on the display screen.

In order to avoid the interference phenomenon due to this overtaking, in the present invention, the selection control of the writing and reading of the memory is performed in units of horizontal scanning lines before the overtaking occurs, so that the discontinuity point of the video signal is always the video signal. Do not come in the middle of the display period of. This memory control will be described with reference to FIGS. 3 and 4.

FIG. 3 is a circuit block diagram showing details of a specific example of the write control circuit 114. FIG. 4 is a circuit block diagram showing details of a specific example of the read control circuit 115. 3 and 4, 301 and 401 are address counters, 302 and 402 are pulse generation circuits, 303 and 403 are final address detection circuits, and 30.
4 and 404 are 1-bit counters, 305 is an edge detection circuit, 306 and 406 are multiplexers, 30
7 and 407 are inverter circuits, and 308 and 408.
Is an AND circuit, 313 is a counter circuit, 314 is a pulse generation circuit, 315 is an OR circuit, and 316 is a gate circuit.

The upper portion of the write control circuit 114 of FIG.
The read control circuit 115 of FIG. 4 operates symmetrically with each other. First, FIG. 3 will be described.

The horizontal sync signal 153 extracted from the reproduction signal is input to the edge detection circuit 305, and an edge pulse having a width of 1 clock is output in synchronization with the write clock 152. The address counter 301 is a circuit that generates a write address, receives an edge pulse signal from the edge detection circuit 305, resets the address value to the leading address, and starts the counting operation.

The final address detection circuit 303 detects that the address generated by the address counter 301 has reached the final address, and stops the counting operation of the address counter 301. The 1-bit counter 304 is used to select the memories 113A and 113B shown in FIG. 1. When the output signal 311 is at a low level, the memory 1
When 13A is at high level, the memory 113B is activated. The edge signal of the horizontal synchronizing signal from the edge detection circuit 305 is input to the 1-bit counter 304 via the AND circuit 308, and the low level and the high level are repeatedly output every time the edge signal is input, whereby the memory 113 is output.
Alternately activate A and B.

The pulse generation circuit 302 receives the address signal from the address counter 301 and the memory selection signal 311 from the 1-bit counter 304, and the write address is between the head address of the memory 113A and a predetermined fixed address. During the period, a high level is output as the signal 309. Similarly, a high level is output to the signal 310 during the period in which the write address is between the head address of the memory 113B and a predetermined fixed address.

The input signals 409 and 410 are signals generated by the read control circuit 115 described later in FIG. 4, and are signals having the same reference numerals in FIG. Although the generation operation of these signals will be described later, the signal 409 is a signal that is at a high level during a period in which the position of the read address is between the head address of the memory 113A and a predetermined fixed address, and the signal 410 is a read signal. It is a signal that is at a high level during a period in which the address position is between the head address of the memory 113B and a predetermined fixed address.

The multiplexer 306 selects and outputs the signal 401 when the output of the 1-bit counter 304 is low level and the signal 409 when it is high level. The output of the multiplexer 306 is inverted by the inverter circuit 307 and then input to the AND circuit 308.

Therefore, for example, when the output signal 311 of the 1-bit counter 304 is at low level (or high level), writing to the memory 113A (or B) is 1
After the horizontal scanning line segment is performed and after this is completed, normally, at the timing when the writing to the memory 113B (or A) is started next, the read address is set to the memory 113B.
(Or A) signal 410 near the start address
Becomes high level, the output of the AND circuit 308 becomes low level, and therefore the value of the 1-bit counter 304 remains low level (or high level) and is not updated. Therefore, the memory 113A (or B) is again written.

With the above circuit configuration, when the write address is close to the read address by a predetermined value or more when the write of one horizontal scanning line is completed, the memory which is not read, that is, until then. Rewrite to the memory that was used for writing. This operation is shown in FIG.
Will be explained.

FIG. 5 is a timing chart showing memory control when rewinding reproduction is performed. In the case of rewind reproduction, the write frequency is higher than the read frequency, and therefore the write address tries to overtake the read address.

The reference numerals assigned to the respective signal waveforms in FIG. 5 are the same as those assigned to FIGS. 1, 2 and 3. Circles 501 to 506 shown in the upper part of FIG. 5 are schematic diagrams showing the positional relationship between the write address and the read address, as in FIG. In this figure, as indicated by circles 501 to 504, the write address gradually approaches the read address in the case of rewinding reproduction.

At the timing of writing the 3H video signal of writing to the memory of A, and when this is finished and the horizontal synchronizing signal 153 of 4H is input, the difference from the read address becomes within a certain reference value, and the signal 410 is changed. When it overlaps with the high level period, the signal 31 is generated by the circuit configuration described in FIG.
Level 1 does not change. That is, the fourth memory is continuously written in the same memory A where the third memory was written. After that, the space between the write address and the read address is widened as shown by a circle 505.

Therefore, by the above operation, the 3H video signal in the write video signal 155 is overwritten with the 4H video signal before being read from the memory 113A.
In the read video signal 156, the 3H video signal is thinned out. As described above, the video signal rewound and reproduced from the magnetic tape 136 has its frequency lowered and the number of horizontal scanning lines reduced by the control of the time axis conversion by the memory and the thinning-out of horizontal scanning lines. Is converted into a video signal having the same frequency and the same number of horizontal scanning lines.

Next, the lower circuit of FIG. 3 will be described.
The counter circuit 313 is reset by the edge signal of the horizontal synchronizing signal input via the OR circuit 315, and counts the clock for one horizontal scanning period. The pulse signal generation circuit 314 receives the output of the counter 313, generates the pulse signal 350 one horizontal scanning period after the reset of the counter 313, and resets the counter 313 again via the OR circuit 315.

Even if the horizontal synchronizing signal is not input for some reason, a pulse signal having a cycle of approximately one horizontal scanning period is obtained at the output 312 of the OR circuit 315.
The signal 351 is a pulse signal generated by the pulse generation circuit 314 and is at a high level for a certain period after the counter is reset. By outputting this signal to the gate circuit 316, the reset signal from the reproduction synchronization signal 153 is prohibited during this period. This causes signal 35
This prevents the pulse cycle of 1 from becoming extremely short.

Next, memory control during fast-forward reproduction will be described. In FIG. 4, the address counter 401 is shown in FIG.
Is a circuit for counting the clock signal 154 from the fixed frequency oscillator 116 and generating a read address. The final address detection circuit 403 detects that the address generated by the address counter 401 has reached the final address, and resets the count value of the address counter 401 to the start address.

The 1-bit counter 404 is for selecting the memories 113A and B of FIG. 1, and when the output signal 411 is at a low level, the memory 113A is selected.
However, when it is at the high level, the memory 113B is activated. The signal 412 from the final address detection circuit 403 is A
The memory 11 is input to the 1-bit counter 404 via the ND circuit 408 and repeatedly outputs a low level and a high level each time a detection pulse of the final address is input.
3A and B are alternately activated.

The pulse generation circuit 402 receives the address signal from the address counter 401 and the memory selection signal 411 from the 1-bit counter 404, and the read address is from the head address of the memory 113A to a predetermined fixed address, A high level is output to the signal 409. Similarly, the read address is memory 1
A high level is output to the signal 410 during a period from the head address of 13B to a predetermined fixed address.

As the input signals 309 and 310, signals generated by the write control circuit 115 shown in FIG. 3 and having the same reference numerals in FIG. 3 are input. That is, the signal 309 is a signal which is at a high level during a period in which the position of the write address is between the head address of the memory 113A and a predetermined fixed address, and the signal 410
Is a signal that is at a high level during a period in which the position of the write address is between the head address of the memory 113B and a predetermined fixed address. Multiplexer 4
06 is the signal 310 when the output of the 1-bit counter 404 is at the low level, and signal 309 when it is at the high level.
To output. The output of the multiplexer 406 is inverted by the inverter circuit 407, and then the AND circuit 408.
Entered in.

Therefore, for example, when the output of the 1-bit counter 404 is at a low level (or a high level), reading from the memory 113A (or B) is performed for one horizontal scan, and when this is completed, the next memory is normally read. 113
At the timing of starting reading from B (or A), when the write address is near the start address of the memory 113B (or A) and the signal 310 becomes high level, the output of the AND circuit 408 becomes low level. Therefore, the value of the 1-bit counter 404 remains low level (or high level) and is not updated. Therefore, reading from the memory 113A (or B) is continuously performed again.

With the above circuit configuration, when the writing address is approaching a certain value or more at the time when the reading of one horizontal scanning line is completed, the memory in which the writing has not been performed, that is, the reading and writing are performed up to that point. Read again from the memory that was used. This operation will be described with reference to FIG.

FIG. 6 is a timing chart showing memory control when fast-forward reproduction is performed. In the case of fast-forward reproduction, the writing frequency is lower than the reading frequency, so that the reading address catches up with the writing address.

In FIG. 6, the reference numerals assigned to the respective signal waveforms are the same as the reference numerals assigned in FIGS. 1, 2 and 3. Circles 601 to 606 shown in the upper part of FIG. 6 are schematic diagrams showing the positional relationship between the write address and the read address, as in the case of FIG. As indicated by circles 601 to 604 in this figure, in the case of fast-forward reproduction, the read address gradually approaches the write address.

After the timing of the circle 603, the signal is read from the memory A, and at the timing of the circle 604 when the signal is read and the reading of the signal of the next scanning line is started, the difference from the write address is within a certain reference value. When the signal 310 overlaps the high level period, the level of the signal 411 does not change due to the circuit configuration of FIG. 4 described above. That is, reading is continuously performed from the memory A. After that, the space between the write address and the read address is widened as indicated by a circle 605.

Therefore, by the above operation, the same video signal is repeatedly read twice. Thus, the magnetic tape 136
The video signal that is rewound and reproduced from is increased in frequency and the number of horizontal scanning lines is increased by the time axis conversion and repetitive reading operation by the memory described above, so that the same horizontal scanning line is used at the same horizontal synchronizing frequency as the standard signal. Converted into a number of video signals.

Signals 309, 310 and 40 which are signals for determining whether thinning or repeating is performed by memory control.
How much a certain period (pulse width) in which 9 and 410 are high level is set depends on how fast the fast-forward reproduction or the rewind reproduction of the system to which the present invention is applied is targeted. Decided. That is, the pulse width may be determined so that the address overtaking does not occur in the next scanning line when the write and read addresses come close to each other just within the pulse width.

Returning to FIG. The video signal thus time-axis corrected is converted into an analog signal by the D / A converter 118, and then the dropout correction circuit 1 is used.
After being applied to 37 and subjected to correction processing when a signal is missing, the luminance signal processing circuit 119 is subjected to processing such as FM demodulation and converted into a baseband signal. On the other hand, after being applied to the color signal extraction circuit 120 to extract the color signal, it is sent to the phase shift and frequency conversion circuit 122.

Before explaining the color phase shift control of this embodiment, the general VHS system color signal processing will be described first. In the case of a magnetic recording / reproducing apparatus used for home use, azimuth recording in which tracks are adjacently recorded by magnetic heads having different azimuth angles is generally used to increase information recording density. In the signal, the phase when frequency-modulating the color signal is further shifted for each horizontal scanning line by 90 degrees, and the shift direction is further reversed for each track for recording, and signals for adjacent tracks are added during reproduction. The device is designed to remove adjacent interference components.

FIG. 11 shows a color signal processing circuit shown in, for example, the literature (Minori Inazu et al .: Recording and reproduction of images, Corona Publishing Co., Ltd .: pp. 408 to 411). It is explanatory drawing which showed the device which removes an adjacent interference component.

In FIG. 11, reference numeral 1101 is a magnetic tape, 1
102 is a control track, 1103 is an audio track, 1104 and 1105 are video tracks adjacent to each other, 1106 is a magnetic head, 1107 is a phase shift circuit, 1108 is a 1H (H is a horizontal scanning line) delay circuit, 11
Reference numeral 09 is an adder. The arrow shown in the circle indicates the phase of the color signal which is frequency-modulated and recorded. Again 11
10 is the period (1H) of the horizontal synchronizing signal in the recorded signal
Is shown.

As shown in FIG. 11, the phase of the frequency-modulated color signal is shifted by 90 degrees for each horizontal scanning line (1H). The direction of this shift is opposite in adjacent tracks. During reproduction, the phase shift circuit 1107 shifts the phase in the opposite direction to that during recording, and the adder 1109 adds the signal one horizontal scanning line (1H) before from the 1H delay circuit 1108. After the phase shift, the interfering component leaking from the adjacent track has a phase opposite to that of the signal 1H before, and therefore is canceled.

In FIG. 1, a phase shift and frequency conversion circuit 122 is a circuit for converting a color signal which has been low-frequency converted for recording into a sub-carrier band, and its detailed circuit configuration is shown in the block diagram of FIG. . FIG. 12 is a block diagram showing details of the phase shift and frequency conversion circuit 122 in FIG.

In FIG. 12, 1201 and 1209 are frequency conversion circuits, 1202 are burst signal extraction circuits, and 120.
3 is a phase comparison circuit, 1204 is an adder, 1205 is a voltage controlled oscillation circuit, 1206 is a frequency divider circuit, 1208 is a switch circuit, 1207 is a fixed oscillation circuit, and 1210 is a frequency discrimination circuit. The same signals as those shown in FIG. 1 are designated by the same reference numerals.

The fixed oscillating circuit 1207 is an oscillating circuit which oscillates at a fixed frequency of 3.58 MHz which is a color subcarrier. Further, the voltage controlled oscillator circuit 1205 uses a carrier frequency for low frequency conversion of color signals (40 fH, 629 kH in the VHS system).
z. However, fH is the horizontal synchronization frequency. ) Is a voltage controlled oscillator circuit that oscillates at a frequency four times higher than Frequency divider circuit 120
Reference numeral 6 denotes a circuit that obtains a low-frequency-converted carrier frequency signal by dividing the output of the oscillation circuit 1205 into four, and outputs four signals that are different in phase by 90 degrees.

The switch circuit 1208 switches these signals according to the control signal 167 and outputs them. The frequency conversion circuit 1209 performs frequency conversion between the output of the fixed oscillation circuit 1207 and the output of the switch circuit 1208 and outputs the result to the frequency conversion circuit 1201. In the frequency conversion circuit 1202, the low-frequency converted color signal input 164 is converted into a color subcarrier band signal 165 by frequency conversion with the output signal from the element 1209.

The burst signal extraction circuit 1202 extracts a burst signal from the frequency-converted color signal 165 (the output 166 of the element 123 in the embodiment of FIG. 1) and outputs it to the phase comparison circuit 1203. The phase comparison circuit 1203 performs phase comparison between the extracted burst signal and the output from the fixed oscillation circuit 1207, generates a voltage corresponding to the difference, and outputs the voltage to the voltage control circuit 1205 via the adder circuit 1204. Ie elements 1205, 1206, 1208, 1
209, 1201, 1202, 1203, 1204, 1
Reference numeral 207 constitutes a phase locked loop, and the output signal 1
The burst phase of 65 works like locking the output of the fixed oscillator circuit.

Therefore, the frequency fluctuation contained in the input signal 164 is removed by this circuit configuration. Furthermore, in order to prevent the oscillation frequency of the output signal of the oscillation circuit 1205 from being shifted when it is shifted by an integral multiple of the horizontal synchronization frequency,
A frequency discriminating circuit 1210 is provided, and when the oscillation frequency deviates to some extent or more, a correction voltage is given to the adding circuit 1204 to control the oscillation frequency.

The control signal 167 of the switch circuit 1208 is an output signal from the phase shift control circuit 121 of FIG. During normal speed tape reproduction, by sequentially selecting the low frequency conversion carrier frequency signals from the frequency dividing circuit 1206 whose phases are deviated by 90 degrees for each 1H, the color signals of the color signals generated during recording are selected. Correct the phase shift.

Since the directions of the phase shifts are reversed in the adjacent tracks, it is necessary to reverse the selection order in the switch 1208. The switching of the phase shift direction is performed once per field during normal speed reproduction, but in the case of fast-forward reproduction or rewind reproduction, the magnetic head 101 frequently causes track jumps across a plurality of tracks. It is also necessary to change the shift direction frequently. In order to perform this control, the signal 158 from the head switching circuit 103 in FIG. 1 is guided to the phase shift control circuit 121 to control the direction of phase shift. This signal 158 is a control signal for switching heads having different azimuth angles as described above, and also indicates the direction of phase shift.

Further, in the present invention, in order to correct the discontinuity of the color phase generated in the fast-forward reproduction or the rewind reproduction processing,
As seen in FIG. 1, the track jump phase detection circuit 1
26 and a memory control phase shift calculation circuit 127. The amount of phase shift of the color signal before and after the track jump occurs is not uniquely determined. The track jump phase detection circuit 126 is a circuit for detecting the phase difference of the color signals at the time of the track jump, and FIG. 7 is a circuit block diagram showing a detailed concrete example of the track jump phase detection circuit 126.

Further, even when thinning-out or repetitive interpolation in units of horizontal scanning lines is performed by the above memory control, the phase of the color signal becomes discontinuous. The memory control phase shift calculation circuit 127 is a circuit for calculating the phase difference under the memory control, and FIG. 8 is a circuit block diagram showing the details of the memory control phase shift calculation circuit 127.

First, the operation of the track jump phase detection circuit 126 shown in FIG. 7 will be described. In FIG. 7, reference numeral 701 is a color signal extraction circuit, 702 is a burst phase detection circuit, and 70
3 is an up / down counter, 704 is a subtractor, 705 is a line difference detection circuit, 706A, 706B, 711A,
711B is a register, 707 and 712 are multiplexers, 708 is a gate circuit, 709 is an inverter, and 710.
Is a counter and 713 is an inter-line comparison circuit. Again 7
50 to 758 are electric signals. Other signals that are the same as those in other drawings are given the same reference numerals.

In FIG. 7, the digitized video signal 161 is applied to the color signal extraction circuit 701 to extract the color signal. The burst phase detection circuit 702 detects the phase of the burst signal from the extracted color signal, digitizes it, and outputs it.
This can be realized, for example, by generating a reference signal having the same frequency as the modulation frequency of the color signal and detecting the phase difference from the burst signal. Since it is finally for detecting the change in the phase of the burst signal, it is not necessary to specify the absolute phase of this reference signal.

The up / down counter 703 is an up / down counter which uses the signal 312 corresponding to the horizontal synchronizing signal of the writing system as a clock signal, and switches up / down operation according to the direction of the phase shift indicated by the signal 158. The count output 751 represents the four states of the phase of the color signal when the track jump does not occur: 0 °, 90 °, 180 ° and 270 °. Note that the output value 751 of this counter has only a problem of increase / decrease value, and it is not necessary to specify the absolute value.

In the subtractor 704, the output value 750 of the burst phase detection circuit 702 is changed to the up / down counter 7
The output value 751 of 03 is subtracted. If the track jump does not occur, the burst phase detected by the burst phase detection circuit 702 and the phase indicated by the output of the up / down counter 703 always change with a constant difference. Therefore, the output 752 of the subtractor 704 does not change. Does not happen. If a track jump occurs and the phase shift changes, the output 752 of the subtractor 704 changes.

The interline difference detection circuit 705 detects the phase change 753 due to the track jump by taking the difference between the value of the signal 752 and the value one horizontal scanning line before. In this way, the value of the phase change in the reproduced video signal is detected, but it is necessary to output this value in accordance with the reading of the video signal memory. Therefore, according to the memory selection signal 311 from the write control circuit 114 described above, the register 711 is selected in accordance with the selection of writing the video signal to the memories A and B.
Writing is selectively performed to A and 711B.

The signal thus written is written in accordance with the memory selection signal 411 from the read control circuit 115 described above.
In accordance with the selection of reading the video signal from the memories A and B, the signal is selectively read and output via the multiplexer 707. It is necessary to correct the phase change due to the track jump only once when the signal of the scanning line is read for the first time, and when the above-mentioned repeated interpolation by the memory control is performed, the phase correction due to the track jump is performed. You must avoid repeating it. The gate circuit 708 is for inhibiting the repetition of this phase correction.

The counter 710 is a counter that increments the value every time the signal 312 is input. The output value 754 of the counter 710 is selectively written in the register 711A or B as in the case of the above-mentioned phase change signal, and selectively read out via the multiplexer 712, and then, one horizontal scanning line before in the inter-line comparison circuit 713. The comparison is performed by subtracting the value of.

If the value does not increase from the subtraction result 757 (no output), it indicates that the memory is being repeatedly read out.
Reference numeral 13 outputs a high-level gate signal 758 to the gate circuit 708 to forcibly set all the phase correction values of the output 162 to the low level, that is, 0. (Strictly speaking, when the value of the counter 710 returns to 0, the magnitude relation is reversed, so it is necessary to take this into consideration. However, in order to simplify the description, it is simply determined by increase or decrease. With the above control, the phase correction by the track jump is not repeated during the repeated interpolation of the memory.

13 and 14 show timing charts of the phase correction operation at the time of track jump. In FIGS. 13 and 14, the reference numerals given to the respective signal waveforms are the same as the reference numerals given to the signals already described.

FIG. 13 is a timing chart of signals of respective parts when the phase is corrected by the track jump, and l (lowercase L) 4 to l5 of the write signal 155 are shown.
At, a track jump occurs and the signal 158 indicating the phase shift direction changes. Here, the phase shift amount 753 due to the track jump is detected as −90 degrees, and the shift amount is read and output at the timing when the read video signal 15 is read.

FIG. 14 is a timing chart of signals of respective parts when the phase correction by the track jump and the repetitive correction by the memory control occur at the same time. As in FIG. 13, the track jump occurs at l4 to l5 of the write signal 155. , The signal 158 indicating the phase shift direction is changing. Phase shift amount 7 due to track jump
53 is also detected as -90 degrees as in FIG. The read video signal 15 is read twice by the above-mentioned repeated interpolation by the memory control. Therefore, the shift amount due to the track jump is also read twice, but the gate pulse 758 becomes high level in the second read period, The correction value 162 becomes 0 degree. Therefore, the phase shift correction by the track jump is performed only once, and there is no malfunction.

Next, the memory control phase shift calculation circuit shown in FIG. 8 will be described. In FIG. 8, 801 is an up / down counter, 802A and 802B are registers, and 80
3 is a multiplexer, 804 is a line difference detection circuit, 8
Reference numeral 05 is an arithmetic circuit, and 806 is an inverter circuit. 85
Reference numerals 1 to 853 are electrical signals, and the reference numerals of other signals are the same as the reference numerals of the signals already described.

The up / down counter 801 is shown in FIG.
The same as the up / down counter 703 of FIG. This output 851 represents the state of the phase of the color signal, and its change is a problem, and it is not necessary to specify the absolute value, as in FIG. And this signal 85
1 is the memory selection signal 31 from the write control circuit 114.
1 is selectively written to the registers 802A and 802B in accordance with the selection of writing the video signal to the memories A and B.

The signal thus written is written in accordance with the memory selection signal 411 from the read control circuit 115 described above.
In accordance with the selection of reading the video signal from the memories A and B, the signal is selectively read through the multiplexer 803 and output. This output signal 852 is sent to the line difference detection circuit 80.
4 is input and the value one horizontal scanning line before is subtracted, whereby the change in color phase due to repeated interpolation or thinning is calculated.

However, since the calculated value is originally a value including the amount of phase shift for each horizontal scanning line,
You need to deduct that amount. That is, when the original phase shift amount is +90 degrees, a value obtained by subtracting 90 degrees from the calculated value 853 becomes the correction amount, and conversely, when the original phase shift amount is −90 degrees, the calculated value is 90 degrees. The value obtained by adding the degrees is the correction amount. This processing is performed in the arithmetic circuit 805.

The description returns to FIG. The phase shift control circuit 121, in addition to the correction of the color phase shift amount for each horizontal scanning line, also performs the color phase correction value 16 by the track jump.
The total correction value obtained by adding 2 and the phase shift calculation value 163 by memory control is output to the phase shift and frequency conversion circuit 122. A specific example of the circuit configuration is shown in the block diagram of FIG. That is, FIG. 17 is a block diagram showing a specific example of the phase shift control circuit 121 in FIG.

In FIG. 17, 1701 and 1702 are adders, and 1703 is an up / down counter. Further, the reference numerals attached to the signals are the same as those attached to the other drawings.
The output signal 167 controls the switch 1208 of FIG.

The color signal thus phase-shifted is applied to the color signal processing circuit (adjacent interference removal filter) 123. This is a circuit for removing the interference component leaking from the adjacent track described with reference to FIG. After this processing is performed, it is added to the luminance signal in the adder 124 and applied to the monitor device 125 for display. Alternatively, it may be converted into an RF signal and displayed.

By the way, in the very high speed fast-forward reproduction or rewind reproduction as the target of the present invention, it is assumed that the magnetic head does not come into stable contact with the magnetic tape. It is also possible that a sufficient video signal output for demodulation cannot be obtained during a track jump. In such a case, the video signal cannot be obtained and the synchronization signal cannot be detected.

When the sync signal is not input in this way,
In this embodiment, since the count operation of the address counter 301 is stopped in the write control circuit 114 of FIG. 3, the video signal is not written in the memory. Therefore, the video signal last written in the memory is repeatedly output. That is, even if a video signal cannot be obtained, noise is not output to the display screen because the signal of the previous scanning line is repeatedly interpolated.

In addition, the signal 312 of FIG. 3 which continuously outputs pulses at a cycle of almost 1H is used as the synchronizing signal input of the writing system of the circuit blocks 126 and 127 for controlling the phase shift. Therefore, the control of the color phase is continuously performed without the input of the synchronizing signal. Therefore, the video signal output is obtained again, and the correct color phase is maintained even after returning to the normal operation. Alternatively, since the color phase shift that occurs during that time can be reduced, subsequent restoration can be speeded up.

There may be a case where a stable head touch cannot be obtained for a relatively long period of time while the tape is running, or a video signal cannot be obtained for more than ten horizontal scanning lines. To be In such a case, if the signals on the same line are repeatedly displayed, a strange screen with a vertical stripe pattern appears, which gives the viewer an unpleasant feeling.
Therefore, another embodiment will be described below.

FIG. 9 shows the write control circuit 11 in FIG.
4 is a block diagram showing the configuration of another specific example of No. 4 of FIG. In FIG. 9, 901 is a counter circuit, 902 is an AND circuit,
902 is an OR circuit, and other parts and signals are the same as those in FIG.

In FIG. 9, the counter circuit 901 is reset by the edge signal of the input horizontal synchronizing signal 153, and when the pulse signal 350 generated in approximately 1H period is counted for several counts (for example, 3H), the counter circuit 901 is set to the high level. Output. As a result, the AND circuit 902 outputs the signal 350, and the address counter 301 is reset and the count is started via the OR circuit 903.

As a result of the above operation, if the period in which the horizontal synchronizing signal is not input continues for several H (for example, 3H), the signal 350 acts as a signal instead of the horizontal synchronizing signal 153 after that, and the writing to the memory is restarted. . At this time, the video signal written in the memory is noise, and the strange vertical stripes described above are not displayed.

[0117]

According to the present invention, in a reproducing apparatus for magnetically recorded video signals, high-speed fast-forward reproduction or rewinding reproduction (reproduction at least 20 times faster than that at the time of recording) which has not been hitherto achieved. However, there is an advantage that it can be realized with high image quality without disturbance of color signals and at low cost.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a state in which two memories are accessed for each horizontal scanning line (1H).

3 is a circuit block diagram showing a specific example of a write control circuit in FIG.

FIG. 4 is a circuit block diagram showing a specific example of a read control circuit in FIG.

FIG. 5 is a timing chart showing memory control when rewinding reproduction is performed.

FIG. 6 is a timing chart showing memory control when fast-forward reproduction is performed.

7 is a circuit block diagram showing a specific example of the track jump phase detection circuit in FIG.

8 is a circuit block diagram showing a specific example of a memory control phase shift calculation circuit in FIG.

9 is a block diagram showing another specific example of the write control circuit in FIG. 1. FIG.

10 is a block diagram showing a configuration of a magnetic head and a head switching circuit in FIG.

FIG. 11 is an explanatory diagram showing a color signal processing circuit devised to remove adjacent interference components between adjacent tracks during reproduction.

12 is a block diagram showing details of a phase shift and frequency conversion circuit in FIG.

FIG. 13 is a timing chart of signals of respective parts when a phase is corrected by a track jump.

FIG. 14 is a timing chart of signals of respective parts when the phase correction by the track jump and the repetitive correction by the memory control occur at the same time.

FIG. 15 is an explanatory diagram showing an example of a head locus when a rotary head scans and reproduces a video track recorded obliquely to the running direction of the magnetic tape.

FIG. 16 is an explanatory diagram showing another example of a head locus when a rotary head scans and reproduces a video track recorded obliquely with respect to a running direction of a magnetic tape.

17 is a block diagram showing a specific example of the phase shift control circuit in FIG.

[Explanation of symbols]

105 ... Sync signal demodulator, 113A, 113B ... Memory, 114 ... Write control circuit, 115 ... Read control circuit, 121 ... Phase shift control circuit, 122 ... Phase shift and frequency conversion circuit, 126 ... Track jump phase detection circuit, 127 ... Memory control phase shift calculation circuit, 1
36 ... Magnetic tape, 141-144 ... Magnetic head

Claims (8)

[Claims] 1. A reproducing apparatus for a video signal in which a video track recorded obliquely with respect to a running direction of a magnetic tape is scanned and reproduced by a rotary head, wherein (a) fast-forward reproduction or rewind reproduction (hereinafter , And both reproductions are simply referred to as high-speed reproduction), at the time of high-speed reproduction, a time-axis conversion means of the video signal for correcting a frequency change accompanying the high-speed reproduction of the reproduction video signal, and (b) the reproduction video signal. Scanning line thinning-out or repetitive interpolating means for compensating the increase or decrease in the number of scanning lines constituting one field of (1), and (c) the frequency-modulated color signal included in the reproduced video signal. By calculating and correcting the phase change at the time of a track jump accompanying the high speed reproduction of the carrier wave and the phase change caused by the thinning or repeated interpolation of the scanning lines, A reproducing apparatus for magnetically recorded video signals, characterized by comprising a phase correction means for correctly operating the interference removal function from an adjacent track, and capable of displaying a reproduced video signal at high speed reproduction on a monitor without disturbing colors. . 2. The reproducing apparatus of the magnetically recorded video signal according to claim 1, wherein the magnetically recorded video signal is a frequency-converted color signal obtained by changing a frequency of a carrier wave by a color signal. The video signal includes a carrier wave whose phase is rotated by a constant angle such as 90 degrees for each 1H (1H is one horizontal scanning line) of the video signal, and the rotation direction is reversed for each track. As described above, the video signal includes such a color-converted color signal, and the time-axis conversion means and the scanning line thinning-out or repetitive interpolation means for the video signal are (a) an image for at least two horizontal scanning lines. First storage means (113A, 113B) having a storage capacity capable of storing a signal and storing a video signal reproduced from a magnetic tape
(B) Write control means (11) for generating a control signal for writing the reproduced video signal to the first storage means in synchronization with the synchronization signal reproduced from the magnetic tape.
4) and (c) a control signal for reading a reproduced video signal from the first storage means in synchronization with a clock signal having a constant frequency or a timing signal obtained by dividing the clock signal. The read-out control means (115) for generating, and (d) the phase of the carrier wave of the color signal reproduced from the magnetic tape in the scanning line before the jump during the track jump and after the jump. Means (126) for detecting a difference from the phase on the scanning line and subtracting the phase change amount of the constant angle such as 90 degrees from the difference, and (e) detecting the carrier wave. Phase shift amount of at least 2
Second storage means capable of storing batches (706A, 706B)
(F) means (311 and 411) for performing writing and reading in the second storage means in association with the writing and reading control in the first storage means, and (g) thinning-out or repeated interpolation of the scanning lines. Means for detecting a shift amount of the carrier phase of the color signal caused by
27), and (h) an addition means (121) for adding the deviation amount of the carrier phase read from the second storage means and the deviation amount of the carrier phase of the color signal caused by the thinning or repeated interpolation of the scanning lines. (I) A phase correction means (12) for correcting the amount of deviation of the carrier phase as a result of addition by the addition means for the color signals included in the video signal read out from the first storage means.
2) An apparatus for reproducing a magnetically recorded video signal, comprising: 3. The reproducing apparatus for the magnetically recorded video signal according to claim 2, wherein a shift amount of a carrier phase of a color signal caused by thinning out or repeatedly interpolating the scanning line of (g) is detected. The means (127) adds the phase change amount of the constant angle such as 90 degrees by the number of thinning-outs when the scanning lines are thinned out, and when the repeated interpolation is performed, It comprises means for detecting the amount of deviation of the carrier phase of the color signal by subtracting the number of times, and when the scanning line is repeatedly interpolated, the second storage means (706A, 706B) in (e) above is used. A reproducing apparatus for a magnetically recorded video signal, comprising a prohibiting means (708) for prohibiting the output of the read carrier wave phase shift amount. 4. The reproducing apparatus of the magnetically recorded video signal according to claim 1, wherein the time axis conversion means of (a) has a storage capacity capable of storing at least video signals of two horizontal scanning lines. Storage means for storing the video signal reproduced from the magnetic tape, and write control for generating a control signal for writing to the storage means in synchronization with a synchronization signal reproduced from the magnetic tape. Means, read control means for generating a control signal for reading from the storage means in synchronization with a clock signal having a constant frequency or a timing signal obtained by dividing the frequency, and the horizontal scanning line A means for adjusting the timing so that the delimiter of the video signal when thinning or repeating the unit is a timing before the horizontal synchronizing signal on the time axis (1
12) and a reproducing device for a magnetically recorded video signal, comprising: 5. The apparatus according to claim 4, wherein the write control means is configured such that the write address to the storage means is initialized in synchronization with a horizontal synchronizing signal of a video signal reproduced from a magnetic tape, A delay circuit is provided as the timing adjusting means in the preceding stage of the storage means, and the write video signal is delayed to delimit the video signal when thinning or repeating the horizontal scanning line unit in the horizontal synchronizing signal on the time axis. A reproducing apparatus for magnetically recorded video signals, which is characterized by being in the foreground. 6. The reproducing apparatus for magnetically recorded video signals according to claim 1, wherein the time axis conversion means in (a) has a storage capacity capable of storing at least video signals for two horizontal scanning lines. Storage means for storing the video signal reproduced from the magnetic tape, and write control for generating a control signal for writing to the storage means in synchronization with a synchronization signal reproduced from the magnetic tape. Means, read control means for generating a control signal for reading from the storage means in synchronization with a clock signal having a constant frequency or a timing signal obtained by dividing the clock signal; During the period in which the sync signal is not reproduced for some reason, the same video signal is repeatedly read out without writing to the storage means, which may otherwise occur. Means for suppressing the generation of noise (3
01) and a reproducing device for a magnetically recorded video signal. 7. The reproducing apparatus for magnetically recorded video signals according to claim 6, wherein the timing generating means (313, 314) operating in phase synchronization with the synchronization signal reproduced from the magnetic tape, and the synchronization. When the period during which the signal is not reproduced exceeds a certain period, the timing signal (350) from the self-running timing generation means permits writing to the storage means and recognizes the generation of noise (902). A reproducing apparatus for a magnetically recorded video signal, further comprising: 8. A reproducing apparatus for magnetically recorded video signals according to claim 1, 2, 3, 4, 5, 6 or 7, wherein a plurality of magnetic heads rotating on a video track recorded on a magnetic tape. For switching a signal from the plurality of magnetic heads to reproduce a continuous video signal, a means for replacing a missing portion of the reproduced video signal with a video signal of another horizontal scanning line, and switching the signals from the plurality of magnetic heads. A means for obtaining a video signal free from noise by replacing the period including this switching timing with a video signal of another horizontal scanning line while maintaining the horizontal sync signal by performing the timing before the horizontal sync signal. A reproducing apparatus for a magnetically recorded video signal, comprising: