JPH07244982A - Word line selecting circuit - Google Patents

Abstract

PURPOSE:To obtain a word line selecting circuit capable of surely deterring transient currents, easy for design and suitable for high-integration of a semiconductor memory. CONSTITUTION:In an inactivated state, a control signal phi10 becomes an 'H' and consequently transistors Q11 and Q19 having high threshold voltages come into nonconductive conditions and the supply of a power source voltage VCC to a pseudo power source voltage VDD is completely stopped and also a current passing through the inside of an NAND gate 1 is completely interrupted. Further, a control signal phi11 becomes an 'L' and then a transistor Q18 comes into a conductive condition and since the output of the NAND gate 1 is held at the level of the power source voltage VXCC and a transistor Q16 is controlled to be always a nonconductive condition, a current flowing from the drain to the source of the transistor Q16 is suppressed to be of the order of the leakage current flowing through a MOS transistor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a word line selection circuit for a semiconductor memory device, and more particularly to a word line selection circuit for reducing power consumption in circuits around memory cells when the semiconductor memory device is inactive. Is.

[0002]

2. Description of the Related Art Generally, an inactive state (standby state)
The power consumption of the semiconductor memory device described above depends on the leak current flowing between the source and drain of the MOS transistor. Although the leakage current of the MOS transistor can be reduced by setting the threshold voltage of the MOS transistor high, it also causes a switching time to increase. Conventionally, as a method of minimizing the influence on the switching time and reducing the leak current, a MOS transistor having a high threshold voltage is used for a logic gate formed of a MOS transistor having a low threshold voltage. A method of connecting switches in series has been proposed (for example, S.Muto, 1V High-Speed Digital Circ
uit Technology with 0.5um Muti-threshold CMOS, IEE
E International ASIC Conference and Exhibit, pp186
-189, September 27 to October 1, 1993).

A case where the above method is applied to a word line selection circuit of a semiconductor memory device will be described below. Figure 5
FIG. 4 is a circuit diagram showing a word line selection circuit of a semiconductor memory device according to a conventional method. In the figure, Q51 is a PchMOS transistor having a high threshold value, which corresponds to a control signal φ50 indicating an active / inactive state. Thus, the supply of the power supply voltage V _CC to the pseudo power supply line V _DD is controlled. Reference numeral 6 denotes a 2-input NAND gate which constitutes an address decoding unit in the semiconductor memory device, and selects the word line WL based on the address signals IN51 and IN52 input to the semiconductor memory device.

Reference numeral 7 denotes an inverter, which is a NAND gate 6
Is a word driver that receives the output (connection point T5) as an input and inverts and outputs it to the word line WL. Both the NAND gate 6 and the inverter 7 are supplied with power from the pseudo power supply line V _DD . C5 is the parasitic capacitance of the pseudo power line V _DD , Q58
Is an NchMOS transistor that clamps the potential of the word line WL to the ground potential in the non-selected state. Note that N
The AND gate 6 is connected in parallel between the pseudo power supply line V _DD and the output, and is connected in series between the PchMOS transistors Q52 and Q53 which receive the address signals IN51 and IN52, respectively, and the address signal IN5.
1, an NchMOS transistor Q54, Q55 which receives inputs of IN52, and an inverter 7
Is a PchMOS connected between the pseudo power line V _DD and the output
It is composed of a transistor Q56 and an NchMOS transistor Q57 connected between the output and the ground potential.

The word selection circuit shown in FIG. 5 is individually provided for one word line WL, and such single circuits are arranged in a one-dimensional array in the semiconductor memory device. Here, when the semiconductor memory device is activated, the control signal φ50 is controlled to the low level “L”. As a result, the transistor Q51 becomes conductive and the power supply voltage V _CC is supplied to the pseudo power supply line V _DD . Therefore, the transistor Q58 that clamps the word line WL
Becomes non-conductive, the NAND gate 6 and the inverter 7 become operable by the power supply from the pseudo power supply line V _DD, and the transistors Q54 and Q55 become conductive in response to the address signals IN51 and IN52. , A high level "H" is output to the word line WL via the inverter 7, and a predetermined memory cell (not shown) is brought into a selected state.

On the other hand, when the semiconductor memory device is inactivated, the control signal φ50 is controlled to "H". As a result, transistor Q51 becomes non-conductive, and since the threshold voltage of transistor Q51 is set high, there is almost no leakage current, and supply of power supply voltage V _CC to pseudo power supply line V _DD is completely stopped. Therefore, from a static point of view, the NAND gate 6
Since the through current in the inverter 7 is zero, the power consumption of the word line selection circuit in the inactive state is also zero.

[0007] Here, immediately after the virtual power supply line V _DD is disconnected from the power supply voltage V _CC is the parasitic capacitance C of the pseudo power supply line V _DD
The charge stored in 5 becomes a dynamic leak current and is discharged to the ground potential via the NAND gate 6 and the inverter 7. The potentials of the pseudo power supply line V _DD , the NAND gate 6 and the inverter 7 will eventually drop to the ground potential in response to the discharge of electric charges.

[0008]

Therefore, in such a conventional semiconductor memory device, a MOS transistor having a high threshold value is simply provided, and the power supply voltage for the pseudo power supply line V _DD is changed according to the active / inactive state. Since it controls the supply of V _CC , it has a large parasitic capacitance C on the pseudo power line V _DD.
5 exists, the input potential (T
5) becomes lower than the potential of the pseudo power supply line V _DD by the threshold voltage of the MOS transistor or more, the transistor Q56 of the inverter 7 becomes conductive, and the charge (current I) is transferred from the pseudo power supply line V _DD to the word line WL. Flowing in, as a result of this,
There is a problem that the potential of the word line WL rises and the memory cell is selected, and in the worst case, the stored contents of the memory cell are destroyed.

Further, in the design stage of the word line selection circuit, the parasitic capacitance C5 of the pseudo power supply line V _DD is accurately calculated,
A method is possible in which the conduction resistance of the transistor Q58 is set to a resistance value sufficient to clamp the transiently generated current I and the rise of the potential of the word line WL is suppressed, but it is provided in each part of the semiconductor memory device. Not only enormous effort is required to accurately calculate the parasitic capacitance C5 of the pseudo power supply line V _DD and also to design the clamp transistor Q58 corresponding thereto, but also all the word lines WL
On the other hand, it is necessary to dispose the transistor Q58 which occupies a large area, which causes a problem of hindering high integration of the semiconductor memory device. The present invention is to solve such a problem, and an object of the present invention is to provide a word line selection circuit which can suppress transient current without fail and which is easy to design and suitable for high integration of a semiconductor memory. There is.

[0010]

In order to achieve such an object, the word line selection circuit according to the present invention provides a signal indicating a non-selected state to a word line when the semiconductor memory device is inactivated. Setting means for setting the output of the multi-input logic gate to the output logic level, and shutting off the through current that flows from the power supply voltage to the ground potential in the multi-input logic gate when the semiconductor memory device is deactivated. And means. Further, the cutoff means is commonly provided to the multi-input logic gates respectively provided in the plurality of word line selection circuits. Further, the setting means is composed of a MOS transistor connected between the power supply voltage and the input of the word driver and turned on in response to the inactive state, and the cutoff means is provided with the ground terminal and the ground potential of the multi-input logic gate. It is composed of a MOS transistor which is connected between the two and has a high threshold voltage and becomes non-conductive in accordance with the inactive state. In addition, the multi-input logic gate activates / deactivates a plurality of address signals and semiconductor memory devices.
NAND with control signal for controlling inactive state as input
Alternatively, the setting means comprises a NOR gate and the setting means is a NAN.
Of the MOS transistors connected in parallel in the D or NOR gate between the power supply voltage and the output, the MOS transistor receives the control signal, and the breaking means is N
Of the MOS transistors connected in series between the output and the ground potential in the AND or NOR gate, the MOS transistor receives the control signal. Furthermore, the MOS transistor that constitutes the cutoff means has a high threshold voltage.

[0011]

Therefore, when the semiconductor memory device is deactivated, the setting means sets the output of the multi-input logic gate to the logic level at which the signal indicating the non-selected state is output to the word line. The cut-off means cuts off a through current flowing from the power supply voltage to the ground potential in the multi-input logic gate. Further, the through current is interrupted by the interrupting means commonly provided to the multi-input logic gates respectively provided in the plurality of word line selection circuits. Further, when the semiconductor memory device is deactivated, the MOS transistor connected between the power supply voltage and the input of the word driver is turned on as the setting means, and the multi-input logic gate is grounded as the breaking means. A MOS transistor connected between the terminal and the ground potential and having a high threshold voltage is rendered non-conductive. Further, when the semiconductor memory device is inactivated, the MOS transistor which receives the control signal among the MOS transistors connected in parallel between the power supply voltage and the output in the NAND or NOR gate as the setting means becomes conductive. It becomes a state and NAN as a blocking means
Among the MOS transistors connected in series between the output and the ground potential in the D or NOR gate, the MOS transistor to which the control signal is input becomes non-conductive. Further, the MOS transistor having a high threshold voltage as the cutoff means is turned off.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of a word line selection circuit in a semiconductor memory device which is an embodiment of the present invention. In the figure, Q11 is a PchMOS transistor having a high threshold value, which controls the supply of the power supply voltage V _CC to the pseudo power supply line V _DD according to the control signal φ10 indicating the active / inactive state. Reference numeral 1 denotes a 2-input NAND gate that constitutes an address decoding unit in the semiconductor memory device, and is an address signal IN1 input to the semiconductor memory device.
The word line WL is selected based on 1, IN12.

Reference numeral 2 is an inverter, which is a NAND gate 1
Is a word driver that receives the output (connection point T1) of FIG. The NAND gate 1 and the inverter 2 are supplied with power from the power supply voltage V _CC and the pseudo power supply line V _DD , respectively. C1 is the pseudo power line V
It is the parasitic capacitance of _DD . The NAND gate 1 is connected in parallel between the pseudo power supply line V _DD and the output, and the address signal I
The inverter 2 includes PchMOS transistors Q12 and Q13 having N11 and IN12 as inputs, and NchMOS transistors Q14 and Q15 which are connected in series between the output and the ground potential and have address signals IN11 and IN12 as inputs, respectively. A PchMOS transistor Q16 connected between the pseudo power supply line V _DD and the output (word line WL), and an N connected between the output and the ground potential.
It is composed of a chMOS transistor Q17.

Q18 is a PchMOS transistor which is connected between the power supply voltage V _CC and the input of the inverter 2 and receives the control signal φ11 as an input. The low level “L” of the control signal φ11, that is, the semiconductor memory device is inactive. In this state, the power supply voltage V
Set to _CC level, Q19 is NAND gate 1
NchMO connected between the ground terminal (source of the transistor Q15) and the ground potential of the control signal φ11
The S transistor is a non-conductive state when the control signal φ11 is "L", that is, in the inactive state of the semiconductor memory device, and cuts off the through current of the NAND gate 1.

The word selection circuit shown in FIG. 1 is individually provided for one word line WL, and such single circuits are arranged in a one-dimensional array in the semiconductor memory device. Here, when the semiconductor memory device is activated, the control signal φ10 is controlled to “L”.
As a result, the transistor Q11 becomes conductive, and the power supply voltage V _CC is supplied to the pseudo power supply line V _DD . Therefore, the inverter 2 becomes operable and the address signals IN11, I
When the transistors Q14 and Q15 are rendered conductive in response to N12, the transistor Q19 has already been rendered conductive by the control signal φ11, so that the high level “H” is output to the word line WL via the inverter 2. Is
A predetermined memory cell (not shown) is in the selected state.

On the other hand, when the semiconductor memory device is inactivated, the control signal φ10 is set to "H" (control signal φ11).
To "L"). As a result, the transistor Q11
And Q19 are non-conductive, and since the threshold voltages of the transistors Q11 and Q19 are set high, there is almost no leak current in the non-conductive state, and the supply of the power supply voltage V _{CC to} the pseudo power supply line V _DD is complete. Address signal IN11, I
The current passing through the NAND gate 1 from the power supply voltage V _CC to the ground potential is completely cut off regardless of the level state of N12. This gives you a static perspective
Since the through current in the NAND gate 1 and the inverter 2 becomes zero, the power consumption of the word line selection circuit in the inactive state also becomes zero.

[0017] Here, immediately after the virtual power supply line V _DD is disconnected from the power supply voltage V _CC is the parasitic capacitance C of the pseudo power supply line V _DD
The electric charge stored in 1 becomes a dynamic leak current and is discharged to the ground potential via the NAND gate 1 and the inverter 2. However, since the control signal φ11 is controlled to be “L”, the transistor Q18 becomes conductive, and the output of the NAND gate 1, that is, the connection point T1 is held at the level of the power supply voltage V _CC ,
As a result, the transistor Q16 of the inverter 2 is always controlled to be in the non-conducting state, and the current flowing from the drain to the source of the transistor Q16 is suppressed to about the leak current in the MOS transistor.

Further, since the transistor Q17 becomes conductive, it serves as a clamper against a dynamic leak current, and the word line WL is held at "L". Therefore, for each word line selection circuit in the semiconductor memory device, a transistor Q18 for setting the input of the inverter 2 to the level of the power supply voltage V _{CC in} the inactive state and a transistor Q19 for cutting off the through current of the NAND gate 1 are provided. By providing, the power consumption in the word line selection circuit is reduced, and the dynamic leak current due to the parasitic capacitance of the pseudo power supply line V _DD is suppressed, the word line WL is not adversely affected, and stable operation is performed. It can be realized.

Next, a second embodiment according to the present invention will be described with reference to FIG. FIG. 2 shows a configuration in which the transistor Q18 for voltage level setting and the transistor Q19 for shutting off the through current provided in each word line selection circuit are realized by a part of the NAND gate in the above description (see FIG. 1). Is. In the figure, parts that are the same as or equivalent to those in the circuit diagram of FIG.
Is a three-input NAND gate forming an address decoding unit in the semiconductor memory device, and selects a predetermined word line WL based on the address signals IN11, IN12 and the control signal φ11 input to the semiconductor memory device.

The NAND gate 3 is connected to the pseudo power line V
Address signal IN11, which is connected in parallel between _DD and output,
P to which IN12 and control signal φ11 are input
chMOS transistors Q22, Q23 and Q28,
Address signal IN connected in series between the output and ground potential
11 and IN12 and NchMOS transistors Q24 and Q25 to which the control signal .phi.11 is input respectively, and an NchMOS transistor Q29 having a high threshold voltage.

The operation is similar to that described above,
When the semiconductor memory device is activated, the control signal φ10 is controlled to "L", which causes the transistor Q1.
1 becomes conductive, the power supply voltage V _CC is supplied to the pseudo power supply line V _DD , and the control signal φ11 becomes "H". Therefore, the transistor Q29 becomes conductive, and the NAND gate 3 and the inverter 2 can operate. Become. On the other hand, when the semiconductor memory device is inactivated, the control signal φ10 is controlled to “H”. This allows the transistor Q
11 and Q29 are in a non-conducting state, and the threshold voltages of the transistors Q11 and Q29 are set high. Therefore, there is almost no leak current in the non-conducting state, and the power supply voltage V _CC is supplied to the pseudo power supply line V _DD . When it is completely stopped, the pseudo ground line V _SS is disconnected from the ground potential, and the power supply voltage V _{CC is changed} to the ground potential NA.
The current passing through the ND gate 3 is completely cut off.

As a result, from the static point of view, the through current in the NAND gate 3 and the inverter 2 becomes zero, and the power consumption of the word line selection circuit in the inactive state also becomes zero. Also, the pseudo power line V _DD
Of the pseudo power supply line V by the electric charge stored in the parasitic capacitance C1 of
_The dynamic leak current that occurs when _DD is disconnected from the power supply voltage V _CC causes the transistor Q28 to be conductive and the transistor Q16 of the inverter 2 to be non-conductive, as described above. It is suppressed to about the current, and the transistor Q
Since 17 becomes conductive, it serves as a clamper against a dynamic leak current, and the word line WL is held at "L".

Therefore, an NAN for address decoding provided for each word line selection circuit in the semiconductor memory device.
The D gate is formed of a 3-input NAND gate, and one of the MOS transistors connected in series is formed of a MOS transistor having a high threshold voltage, and a control signal φ11 for controlling the active state of this transistor.
By inputting, the input of the inverter 2 can be set to the level of the power supply voltage V _{CC in} the inactive state, and the shoot-through current of the NAND gate 3 can be cut off, thereby reducing the power consumption. It is possible to further integrate the semiconductor memory device using the word line selection circuit that realizes stable operation.

Next, a third embodiment of the present invention will be described with reference to FIG. In FIG. 3, in the above description (see FIG. 1), instead of the transistor Q19 for interrupting the through current provided in each word line selection circuit, a transistor Q39 is shared by a plurality of word line selection circuits. Is. In the figure, parts that are the same as or equivalent to those in the circuit diagram of FIG.
NchMOS 39 is connected between the ground terminals of the plurality of NAND gates 1 and the ground potential and receives the control signal φ11 as an input.
It is a transistor, and a high threshold voltage is set in order to make the leak current at non-conduction almost zero.
V _SS is a plurality of NANDs provided in each word line selection circuit
It is a pseudo ground line that connects the ground terminals of the gate 1 in common.

The operation is similar to that described above,
When the semiconductor memory device is activated, the control signal φ10 is controlled to "L", which causes the transistor Q1.
1 becomes conductive, the power supply voltage V _CC is supplied to the pseudo power supply line V _DD , and the control signal φ11 becomes "H", so that the transistor Q39 becomes conductive and the potential of the pseudo ground line V _SS becomes the ground potential. Since they are equal to each other, the NAND gate 1 and the inverter 2 can operate respectively. On the other hand, when the semiconductor memory device is deactivated, the control signal φ
10 is controlled to "H" (control signal φ11 is "L").
As a result, transistors Q11 and Q39 are rendered non-conductive, and since the threshold voltages of transistors Q11 and Q39 are set high, there is almost no leak current in the non-conductive state, and pseudo power supply line _VDD
Supply of the power supply voltage V _{CC to} the circuit is completely stopped, the pseudo ground line V _SS is disconnected from the ground potential, and the current passing through the NAND gate 1 from the power supply voltage V _CC to the ground potential is completely cut off. .

As a result, from a static point of view, the through current in the NAND gate 1 and the inverter 2 becomes zero, and the power consumption of the word line selection circuit in the inactive state also becomes zero. Also, the pseudo power line V _DD
Of the pseudo power supply line V by the electric charge stored in the parasitic capacitance C1 of
_The dynamic leak current that occurs when _DD is disconnected from the power supply voltage V _CC causes the transistor Q18 to be conductive and the transistor Q16 of the inverter 2 to be in a non-conductive state as described above. It is suppressed to about the current, and the transistor Q
Since 17 becomes conductive, it serves as a clamper against a dynamic leak current, and the word line WL is held at "L".

Therefore, for each word line selection circuit in the semiconductor memory device, the transistor Q1 which sets the input of the inverter 2 to the level of the power supply voltage V _{CC in} the inactive state.
The number of transistors can be reduced by providing 8 and the transistor Q39 that cuts off the through current of a plurality of NAND gates 1 in common, and the word line for reducing the power consumption and realizing the stable operation described above. It is possible to further integrate the semiconductor memory device using the selection circuit.

In the above description, the word line WL
Although the description has been given by taking the semiconductor memory device in which the memory cell is in the selected state when is "H", that is, the power supply voltage V _CC level, when the word line is "H", that is, the ground potential level, the memory cell is The same applies to the semiconductor memory device which is in the non-selected state and is in the selected state when "L", that is, the power supply voltage V _CC 'level (V _CC '<ground potential). The word line selection circuit of the semiconductor memory device in which the memory cell is in the selected state when the word line is at the "L" level, that is, the power supply voltage V _CC level will be described below with reference to FIG.

FIG. 4 is a circuit diagram of a word line selection circuit using a 3-input NOR gate, and in FIG.
Reference numeral 1 denotes an NchMOS transistor having a high threshold value, which responds to a control signal φ40 indicating active / inactive state.
It controls the supply of the power supply voltage V _CC 'to the pseudo power supply line V _DD '. Reference numeral 4 denotes a 3-input NOR gate which constitutes an address decoding unit in the semiconductor memory device, and which has address signals IN41 and I input to the semiconductor memory device.
A predetermined word line WL 'is selected based on N42. Reference numeral 5 denotes an inverter, which receives the output of the NOR gate 4 (connection point T4) as an input and inverts and outputs it to the word line WL ′.
Are both supplied from the pseudo power supply line V _DD '.
C4 is the parasitic capacitance of the pseudo power supply line V _DD '.

The NOR gate 4 is connected in parallel between the pseudo power supply line V _DD 'and the output and is connected to the address signal IN4.
1, IN42 and control signal φ41 are input to Nch MOS transistors Q42, Q43 and Q48, respectively.
And PchMOS transistors Q44 and Q45 which are connected in series between the output and the ground potential and which receive the address signals IN41 and IN42 and the control signal φ41, respectively, and a PchMOS transistor Q49 having a high threshold voltage. Is composed of an NchMOS transistor Q46 connected between the pseudo power supply line V _DD 'and the output (word line WL'), and a PchMOS transistor Q47 connected between the output and the ground potential.

When the semiconductor memory device is activated, the control signal φ40 is controlled to "H" (ground potential), whereby the transistor Q41 becomes conductive and the pseudo power supply line V _DD 'is powered. Since the voltage V _CC 'is supplied and the control signal φ41 becomes "L", the transistor Q49 becomes conductive, and the NOR gate 4 and the inverter 5 can operate respectively. On the other hand, when the semiconductor memory device is inactivated, the control signal φ40 is controlled to "L". As a result, the transistors Q41 and Q49 become non-conductive, and the transistors Q41 and Q49
Since the threshold voltage of 49 is set high, there is almost no leak current in the non-conducting state, the supply of the power supply voltage V _CC ′ to the pseudo power supply line V _DD ′ is completely stopped, and the NOR gate 4 is The ground terminal and the ground potential are separated, and the power supply voltage V _CC 'is changed to the ground potential.
The current passing through the gate 4 is completely cut off.

As a result, from a static point of view, the through current in the NOR gate 4 and the inverter 5 becomes zero, and the power consumption of the word line selection circuit in the inactive state also becomes zero. Also, pseudo power line V _DD '
Of the pseudo power supply line V by the electric charge stored in the parasitic capacitance C4 of
_The dynamic leakage current generated when _DD 'is disconnected from the power supply voltage V _CC ' is suppressed to about the leakage current in the MOS transistor because the transistor Q48 is turned on and the transistor Q46 of the inverter 5 is controlled to be off. Then, the transistor Q47 becomes conductive, which serves as a clamper for the dynamic leak current, and the word line WL 'is HI.
It is held at the GH (ground potential) level.

Therefore, even in the semiconductor memory device in which the memory cell is in the non-selected state when the word line WL 'is "H", the inverter 5 is in the inactive state as described above.
Of the semiconductor memory device using the word line selection circuit that can set the input of the power supply to the level of the power supply voltage V _CC 'and cut off the through current of the NOR gate 4 to reduce the power consumption and realize the stable operation. Can be converted. In addition,
In the above description, the case where the 3-input NOR gate is used has been described, but the same operational effect can be obtained even if the MOS transistors are separately provided or the through-current cutoff MOS transistors are provided in common.

[0034]

As described above, according to the present invention, the setting means for setting the output of the multi-input logic level to the logic level at which the signal indicating the non-selected state is output to the word line and the multi-input logic gate are provided. A shutoff means for shutting off a through current flowing from the power supply voltage to the ground potential is provided, and when the semiconductor memory device is deactivated, the setting means outputs a signal indicating a non-selected state to the word line to a logic level. The output of the multi-input logic level is set, and the break-through means cuts off the through current flowing from the power supply voltage to the ground potential in the multi-input logic gate. Therefore, in the inactive state,
The power consumption in the word line selection circuit is reduced, and the dynamic leak current due to the parasitic capacitance of the power supply line is suppressed, the word line is not adversely affected, and stable operation as a semiconductor memory device can be realized. It will be possible.

Further, since the interrupting means is provided commonly to the multi-input logic gates respectively provided in the plurality of word line selecting circuits, the required number of interrupting means is reduced and the semiconductor memory device can be more integrated. Is possible. further,
As setting means, a MOS that is connected between the power supply voltage and the input of the word driver and becomes conductive according to the inactive state.
The transistor is composed of a transistor, and has a high threshold voltage M as a breaking means, which is connected between the ground terminal of the multi-input logic gate and the ground potential and becomes non-conductive in accordance with the inactive state.
Since it is composed of OS transistors, reliable operation can be realized with a simple circuit element configuration.

The multi-input logic gate is composed of a NAND or NOR gate to which a plurality of address signals and a control signal for controlling the active / inactive state of the semiconductor memory device are input, and the setting means is NAND or NOR.
MO connected in parallel between the power supply voltage and the output in the gate
Of the S transistors, a MOS transistor that receives a control signal is used, and as a breaking means, a MOS transistor that receives a control signal among the MOS transistors connected in series between the output and the ground potential in the NAND or NOR gate.
Since it is configured by the transistor, it is not necessary to provide the setting means and the cutoff means separately from the multi-input logic gate, and not only the MOS transistor on the most ground potential side in the NAND or NOR gate but also the series connection. Any MOS transistor may be used as the cutoff means, which facilitates the design of the semiconductor memory device and realizes high integration. Furthermore, since the MOS transistor having a high threshold voltage is used as the breaking means, the leak current in the non-conducting state is almost eliminated, and the reliable operation can be realized by the simple circuit element structure.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a word line selection circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a word line selection circuit according to another embodiment of the present invention.

FIG. 3 is a circuit diagram of a word line selection circuit according to another embodiment of the present invention.

FIG. 4 is a circuit diagram of a word line selection circuit according to another embodiment of the present invention.

FIG. 5 is a circuit diagram of a conventional word line selection circuit.

[Explanation of symbols]

1, 3 ... NAND gate, 2 ... Inverter, 4 ... NOR
Gate, Q11, Q49 ... PchMOS transistor (high threshold voltage), Q12, Q13, Q16, Q18, Q
22, Q23, Q28, Q44, Q45, Q47 ... Pch
MOS transistors, Q14, Q15, Q17, Q2
4, Q25, Q42, Q43, Q46, Q48 ... NchM
OS transistors, Q19, Q29, Q39, Q41 ...
Nch MOS transistor (high threshold voltage), V _CC , V
_CC '... Power supply voltage, V _DD , V _DD ' ... Pseudo power supply line, V _SS ... Pseudo ground line, WL ... Word line, IN11, IN12, IN
41, IN42 ... Address signal, φ10, φ11, φ4
0, φ41 ... Control signal, C1, C4 ... Parasitic capacitance, T1,
T4 ... connection point.

Claims (5)

[Claims] 1. A word comprising a multi-input logic gate for decoding a plurality of address signals input to a semiconductor memory device, and a word driver for controlling a selection state of a memory cell according to an output of the multi-input logic gate. In the line selection circuit, setting means for setting the output of the multi-input logic gate to a logic level at which a signal indicating the non-selected state is output to the word line when the semiconductor memory device is inactivated. A word line selection circuit comprising: a cutoff means for cutting off a through current flowing from the power supply voltage to the ground potential in the multi-input logic gate when the device is inactivated. 2. The word line selection circuit according to claim 1, wherein the cutoff unit is provided commonly to multi-input logic gates provided in each of the plurality of word line selection circuits. Line selection circuit. 3. The word line selection circuit according to claim 1, wherein the setting means is connected between the power supply voltage and an input of the word driver and is turned on in accordance with the inactive state. A MOS transistor comprising a transistor, wherein the cut-off means is connected between the ground terminal of the multi-input logic gate and the ground potential, has a high threshold voltage, and is in a non-conducting state according to the inactive state. A word line selection circuit comprising: 4. The word line selection circuit according to claim 1, wherein the multi-input logic gate receives a NAND or NOR inputting a plurality of address signals and a control signal for controlling an active / inactive state of the semiconductor memory device. The setting unit is a MOS transistor that receives the control signal as an input among the MOS transistors connected in parallel between the power supply voltage and the output in the NAND or NOR gate; A word line selection circuit comprising a MOS transistor that receives the control signal as an input, among the MOS transistors connected in series between the output and the ground potential in the NAND or NOR gate. 5. The word line selection circuit according to claim 4, wherein the MOS transistor forming the cutoff means has a high threshold voltage.