JPH07244980A - Dynamic memory - Google Patents

Abstract

PURPOSE:To prevent the loss of storage data at the time of executing an internal test mode by supplying a data shifting clock as a refresh requesting signal to an internal circuit at the time of the internal test mode. CONSTITUTION:When an internal test mode signal ITM is in the normal operation mode of an inactive level, a data shifting control signal SCN is also in the inactive level and a selector 4 selects a refresh requesting signal TRQ outputted by a refresh timer 2 to transfer it as a refresh requesting signal RPQ to an internal circuit 1, When the signal ITM is in the internal test mode of an active level, the selector 4 selects a data shifting clock SCK in accordance with the active level of the signal SCN to transfer it as a signal RRQ to the circuit 1. By such a constitution, the storage data in the circuit 1 are made not to be lost even when the number of signal terminals is increased and a long time is required for data shiftings.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic memory, and more particularly to a dynamic memory to which a boundary scan technique is applied.

[0002]

2. Description of the Related Art In developing and manufacturing electronic devices,
Usually, tests such as an in-circuit test and a function test are carried out on a mounting board, a module, an IC, etc. that constitute the electronic device at a predetermined stage.
However, endlessly subsequent diversification of functions of the electronic device, is advanced, the mounting board and modules, also spread like IC, in the above test methods, a long period of time to develop and test itself test tool, it takes a long time Not only that, sufficient testing cannot be performed, resulting in a longer development period, longer manufacturing period, higher cost, and lower reliability.

Therefore, the momentum to solve such a problem arises, and the boundary scan technology for the purpose of supporting the development of the test tool, supporting the test itself, and improving the efficiency was developed, and in the early 1990s, IEEE S
standard 1149.1-1990. “IEEE Standard Test Access Port and Boundary Scan Architecture (IEEE)
E Standard Test Access Po
rt and Boundary-ScanArchi
).

The boundary scan technology is a mounting board, module, IC, etc. (hereinafter, these are called devices).
Is a test technique in which a data register is provided between the signal input / output terminal and the internal circuit and these are sequentially connected in series to form a register chain (shift register), and the register chain is controlled to perform various tests. .

FIG. 4 shows a general example (first example) in which the boundary scan technique is applied to a dynamic memory.

This dynamic memory includes various control signals including a refresh control signal REF, and various signals IN1 to INm including data and address signals.
A plurality of signal terminals TI1 to TIm, TIr, TO1 to TOn for exchanging OUT1 to OUTn with an external circuit;
An internal circuit 1 including a memory cell array, an address selection circuit, and a write / read control circuit, which writes / reads / refreshes data according to various signals transmitted and outputs a predetermined signal, and a refresh control signal input terminal A refresh timer 2 that generates a refresh request signal RRQ at a predetermined timing in response to the active level of the signal, and test data TD from the outside.
I, test mode setting signal TMS and test clock T
An internal test mode signal ITM having an active level in response to CK, a data shift control signal SCN which changes to an active level, an inactive level, or an active level at a predetermined timing during a predetermined period of the active level of the internal test mode signal ITM, The data shift clock SCK is sequentially activated during the active level period of the data shift control signal SCN, and is activated at a predetermined timing during the inactive level period of the data shift control signal during the active level period of the internal test mode signal ITM. An internal boundary scan control signal including an internal test execution signal ITE that becomes a level and a test execution result transmission control signal RTC that becomes an active level after a predetermined period of delay from the internal test execution signal is generated. Secondary scan test control circuit (hereinafter, referred to as BST control circuit) 3, a plurality of terminals TI
1 to TIm, TIr, TO1 to TOn, respectively, and in accordance with the internal boundary scan control signal, when the internal test mode signal ITM is in the normal operation mode of the inactive level, the signal terminals TI1 to T1.
Im and TO1 to TOn are transmitted, and signals are transmitted between the signal terminal TIr and the refresh control signal input terminal of the refresh timer. When the internal test mode signal ITM is in the active level internal test mode, the signals are sequentially connected in series. Sequentially shifting the test data from the outside to the rear stage side, transmitting the signal of the predetermined stage to the internal circuit 1, and taking in the signal from the internal circuit to the predetermined stage. , And a plurality of registers RBI1 to RBIm, RBIr, and RBO1 to R that sequentially shift the fetched signal to the subsequent stage side and output the signal from the last stage.
BOn.

Further, the registers RBI1 to RBIm, RB
As shown in FIG. 5, Ir and RBO1 to RBOn each have a first input end PI connected to a corresponding signal terminal (or a corresponding signal input / output end of the internal circuit 1) and an internal circuit 1 respectively.
First output terminal RPO connected to the corresponding signal input / output terminal (or corresponding signal terminal) of, and the output signal of the previous stage side when the shift register is formed (test data from the outside in the front stage) TPI) second input terminal SI
And a second output end RPO for transmitting a signal to the rear stage side (outputting a signal to the outside in the last stage), and first and second input ends PI, SI according to the data shift control signal SCN.
SL1 for selecting one of the signals, a data shift clock SCK and an internal test result transmission control signal RT
A D-type flip-flop FF1 which latches the output signal of the selector SL1 according to C and outputs it to the second output terminal SO;
One of the D-type flip-flop FF2 that latches and outputs the output signal of the D-type flip-flop FF1 according to the internal test execution signal ITE, and the signal at the first input end and the output signal of the D-type flip-flop FF2 according to the internal test mode signal ITM. Of the internal test mode signal IT.
When M is at the inactive level, the first input terminal PI
Signal is transmitted to the first output terminal RPO, and during the active level period, the signal of the second input terminal SI is taken in in synchronization with the data shift clock SCK during the active level period of the data shift control signal SCN. The internal test execution signal ITE is held during the period of the inactive level of the data shift control signal SCN.
Signal held in response to the active level of the first output terminal SO is transferred to the second output terminal SO, and the signal of the first input terminal PI is received and held in response to the active level of the test execution result transfer control signal RTC to output the second output. It is configured to be transmitted to the end SO.

Next, the operation of the dynamic memory will be described with reference to the timing chart of the signals of the respective parts shown in FIG.

First, when the internal test mode signal ITM is a low level inactive level, the selector SL is used.
2 allows the signal at the first input PI of each register to be the first
Of the signal terminals TI1 to TIm are transmitted to the internal circuit 1 and the output signals of the internal circuit 1 are transmitted to the signal terminals TO1 to TOn, and the internal circuit 1 performs a normal write operation. , Read operation is performed, and the result is output from the signal terminals TO1 to TOm. Further, the refresh control signal REF of the signal terminal TIr is transmitted to the refresh timer 2, and the refresh timer 2 sequentially generates the refresh request signal RRQ in response to the active level of the refresh control signal REF to generate the internal circuit 1.
Communicate to. Then, the internal circuit 1 performs the refresh operation according to the refresh request signal RRQ.

Next, the operation of the internal test mode in which the internal test mode signal ITM is at the active level (high level) will be described.

First, between the signal terminals TI1 to TIm and TIr for inputting various signals by the data shift control signal SCN and the registers RBI1 to RBIm and RBIr, and between the signal output end of the internal circuit 1 and the registers RBO1 to RBOn. Are separated from each other, and these registers are sequentially connected in series by the second input terminal SI and the second output terminal SO to form a shift register having a plurality of stages. Then, in synchronization with the data shift clock SCK that is sequentially generated during the active level of the data shift control signal SCN, the test data TDI from the input end of the register (ROIr in this example) at the front stage is sequentially shifted to the rear stage side. Then, when these test data are transmitted to and held in the corresponding registers, the data shift control signal SCN becomes inactive level, and the generation of the data shift clock SCK is stopped. Therefore, the registers are separated from each other, and the signal terminals and the registers, the registers and the internal circuit, and the refresh timer are connected.

During the inactive level period of the data shift control signal SCN, the internal test execution signal I is first
In response to the active level of TM, the data (data IN held in the D-type flip-flop FF1) held in a predetermined register (RBI1 to RBIm in this example).
1 to INm) are taken into the D-type flip-flop FF2 and transmitted to the internal circuit 1 through the selector SL2, and the internal circuit 1 performs a predetermined operation. Then, in response to the active level of the internal test execution result transmission control signal RTC, the output signal (output data) of the internal circuit 1 is taken into the D-type flip-flop FF1 of a predetermined register (RBO1 to RBOn in this example). Retained.

When the data shift control signal SCN becomes active level again, the registers RBI1 to RBIm, R
BIr and RBO1 to RBOn form a shift register of a plurality of stages, and the held data (signal) is sequentially shifted to the rear stage side in synchronization with the data shift clock that is sequentially generated, and the output terminal of the register RBOn of the last stage. Is output from the outside (TDO).

In this way, the signal terminals TI1 to TIm, TI
The operation of the internal circuit 1 can be tested regardless of the signals r, TO1 to TOn.

In this example, the refresh control signal REF
I explained the dynamic memory in the case of performing the refresh operation by inputting the voltage from the outside, but in the dynamic memory that has the operation mode for the purpose of retaining data by operating at a low power supply voltage by battery backup, etc., the power supply voltage is not detected. Generates an internal refresh control signal to operate the refresh timer. FIG. 7 shows an example (second example) in which the boundary scan technique is applied to such a dynamic memory.

The difference between this dynamic memory and the dynamic memory shown in FIG. 4 is that when the power supply voltage drops below a preset level (for example, 2 V when the normal power supply voltage is 5 V), it becomes an active level. The self refresh control circuit 5 for generating the internal refresh control signal IREF is provided, and the signal to the refresh control signal input terminal of the refresh timer 2 is set to the internal refresh control signal IREF instead of the external refresh control signal REF. is there.

In this dynamic memory, when the power supply voltage drops below a predetermined level, refresh request signal RRQ is supplied from internal refresh timer 2 to internal circuit 1, and internal circuit 1 performs a refresh operation. Other operations are similar to those in the first example.

[0018]

In the first example, the above-mentioned conventional dynamic memory has the following problems.
During the first active level period of the data shift control signal SCN, the signal terminals for inputting various signals and the corresponding registers are separated from each other, and the signal output terminals of the internal circuit 1 and the corresponding registers are separated from each other to establish a cascade connection between the registers. Then, the test data is sequentially shifted to the subsequent stage side by the data shift clock SCK to be set and held in the D-type flip-flop FF1 of a predetermined register, and the next inactive of the data shift control signal SCN. During the level period, the registers are separated from each other to connect the signal terminals / registers, the register / internal circuit 1 and the refresh timer 2 to each other, and are held in the D-type flip-flop FF1 of a predetermined register by the internal test execution signal ITE. Data stored in the D-type flip-flop FF2 and transmitted to the internal circuit 1. A predetermined operation is executed on the path 1, and the result is taken in and held by the D-type flip-flop FF1 of the predetermined register by the internal test execution result transmission control signal RTC, and during the next active level period of the data shift control signal SCN, The registers are cascaded again to form a multi-stage shift register, and the data shift clock SCK
Thus, the data held in the predetermined register is sequentially shifted to the subsequent stage side and output from the last stage, so that the refresh control signal REF from the outside is supplied to the refresh timer 2 during the internal test mode. The refresh timer 2 receives the test data set in the D-type flip-flop FF1 without being transmitted to the D-type flip-flop FF2 by the internal test execution signal ITE.
Therefore, if the level of the signal taken in by the D flip-flop FF2 is a level corresponding to the inactive level of the refresh control signal REF, the refresh control signal input terminal of the refresh timer 2 will have an internal test execution signal. It remains at the inactive level until it becomes the active level by ITE, the refresh request signal RRQ is not output from the refresh timer 2, and therefore the internal circuit 1 does not perform the refresh operation, and the stored data is lost. is there.

In the second example, the refresh request signal RRQ is not output from the refresh timer 2 unless the power supply voltage drops below a preset level. Therefore, when the internal test mode is executed at the normal power supply voltage, the refresh is performed. The request signal RRQ is not generated, and similarly to the first example, the stored data is lost.

It is an object of the present invention to carry out the internal test mode at a normal power supply voltage regardless of whether the refresh operation is controlled by an external control signal or an internal control signal. It is an object to provide a dynamic memory that can prevent stored data from being lost.

[0021]

A dynamic memory of the present invention has a plurality of signal terminals for transmitting and receiving various control signals including a refresh control signal and various signals including data and address signals to and from an external circuit. , A memory cell array, an address selection circuit, and a write / read control circuit, to write data according to various signals transmitted,
An internal circuit for performing a read operation and a refresh operation and outputting a predetermined signal; a refresh timer for generating a refresh request signal at a predetermined timing in response to an active level of a signal transmitted to a refresh control signal input terminal; Of the plurality of signal terminals other than the signal terminal corresponding to the refresh control signal in the normal operation mode in accordance with the internal boundary scan control signal including the data shift clock. Signals are transmitted to and from internal circuits and between the signal terminal corresponding to the refresh control signal and the refresh control signal input terminal of the refresh timer, and in the internal test mode, they are sequentially connected in cascade to shift a plurality of stages. Form a register and send it to the latter stage of test data from the outside Sequential shift, transmission of a signal of a predetermined stage to the internal circuit, acquisition of a signal from the internal circuit to a predetermined stage, sequential shift of the acquired signal to the subsequent stage side and signal output from the last stage Select a refresh request signal from the refresh timer in the normal operation mode according to the internal boundary scan control signal and the data shift clock in the signal shift operation in the internal test mode. A selection circuit for transmitting to a refresh request signal input terminal of the internal circuit.

Further, it receives an external test data, a test mode setting signal and a test clock, and an internal test mode signal having an active level, and an active level at a predetermined timing during a predetermined period of the active level of the internal test mode signal. A data shift control signal, a data shift clock that sequentially becomes an active level during the active level of the data shift control signal, and an inactive level of the data shift control signal during the active level of the internal test mode signal. A boundary scan test control circuit that generates an internal test execution signal that becomes active level for a predetermined period during the period of and a test execution result transmission control signal that becomes active level later than this internal test execution signal is provided, and a plurality of registers are provided. This A first input terminal connected to a corresponding signal terminal (or a corresponding signal input / output terminal of the internal circuit) and a first input terminal connected to a corresponding signal input / output terminal (or a corresponding signal terminal) of the internal circuit. Output terminal, a second input terminal that receives the output signal (data from the outside in the front stage) on the front side when the shift register is formed, and the signal is transmitted to the rear side (on the last stage). A second output end) for transmitting a signal from the first input end to the first output end during a period when the internal test mode signal is at an inactive level, During the active level period, during the active level period of the data shift control signal, the signal of the second input terminal is fetched and held in synchronization with the data shift clock and transmitted to the second output terminal. Shift control signal in In the active level period, the held signal is transmitted to the second output terminal in response to the active level of the internal test execution signal, and the first signal is transmitted in response to the active level of the test execution result transmission control signal. It is configured as a circuit that takes in and holds the signal at the input end and transmits it to the second output end.

A self-refresh control circuit for generating an internal refresh control signal by determining that the internal circuit is in a low power supply voltage operating state is provided, and the internal refresh control signal is supplied to a refresh control signal input terminal of a refresh timer. It has a configuration designed to do so.

[0024]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

This embodiment differs from the conventional dynamic memory shown in FIG. 4 in that the data shift control signal S
When CN is at the inactive level, the refresh request signal output from the refresh timer 2 is selected, and when it is at the active level, the data shift clock SCK is selected and the selector 4 for transmitting to the refresh request signal input terminal of the internal circuit 1 is selected. It is in the point provided.

Next, the operation of this embodiment will be described.
FIG. 2 is a timing chart of signals of respective parts for explaining the operation of this embodiment.

First, in the normal operation mode in which the internal test mode signal ITM is inactive level (low level), the data shift control signal SCN is also inactive level (low level), and the selector 4 outputs from the refresh timer 2 The output refresh request signal TRQ is selected and transmitted to the internal circuit 1 as the refresh request signal RRQ. As a result, the refresh operation of the internal circuit 1 is executed. This operation is the same as that of the conventional example shown in FIGS.

Next, when the internal test mode signal ITM is in the active level (high level) internal test mode, the selector 4 outputs the data shift clock SCK in response to the active level (high level) of the data shift control signal SCN. It is selected and transmitted to the internal circuit 1 as the refresh request signal RRQ. As a result, the refresh operation of the internal circuit 1 is executed. Data shift control signal SC
N is at the time of data shift when setting the test data in each register to execute the test of the internal circuit 1,
Since the signal of the test result after the test execution of the internal circuit 1 becomes the active level during the signal (data) shift to the outside, even if the number of signal terminals increases and the data shift takes a long time, the stored data is It never disappears.

FIG. 3 is a block diagram showing a second embodiment of the present invention. In this embodiment, the present invention is applied to the second conventional example shown in FIG. 7. The difference from the first embodiment is that the signal to the refresh control signal input terminal of the refresh timer 2 is , Signal terminal TIr, register RBIr
The internal refresh control signal IREF from the self-refresh control circuit 5 is used instead of the refresh control signal REF from.

The self-refresh control circuit 5 does not set the internal refresh control signal IREF to the active level unless the power supply voltage drops below 2V, for example. Therefore, when the internal test mode is executed with the normal power supply voltage (for example 5V), the refresh timer is refreshed. 2 does not output the refresh request signal TRQ. However, in this embodiment, even in this case, the data shift clock SC
Since K is transmitted to internal circuit 1 as refresh request signal RRQ, the refresh operation of internal circuit 1 is not executed and the stored data is not lost.

[0032]

As described above, according to the present invention, the refresh request signal output from the refresh timer is supplied to the internal circuit in the normal operation mode, and the test data is supplied for executing the internal test in the internal test mode. A data shift clock that performs data shift when setting to each register and data shift when outputting the test result fetched to each register after executing the internal test is supplied to the internal circuit as a refresh request signal. Therefore, whether the refresh operation is controlled by an external control signal or an internal control signal generated by detecting the level of the power supply voltage, the internal test mode is performed at the normal power supply voltage. There is an effect that it is possible to prevent the stored data from being lost when is executed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a timing chart of signals of respective parts for explaining the operation of the embodiment shown in FIG.

FIG. 3 is a block diagram showing a second embodiment of the present invention.

FIG. 4 is a block diagram showing a first example of a conventional dynamic memory.

5 is a circuit diagram showing a specific example of a register of the dynamic memory shown in FIG.

6 is a timing diagram of signals of respective parts for explaining the operation of the dynamic memory shown in FIG.

FIG. 7 is a block diagram showing a second example of a conventional dynamic memory.

[Explanation of symbols]

1 Internal Circuit 2 Refresh Timer 3 BST Control Circuit 4 Selector 5 Self Refresh Control Circuit FF1, FF2 D-type Flip-Flops RBI1 to RBIm, RBIr, RBO1 to RBOn
Registers SL1, SL2 selectors TI1 to TIm, TIrTO1 to TOn signal terminals

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location G11C 29/00 303 B 7004-5L G11C 11/34 363 E

Claims (3)

[Claims] 1. A plurality of signal terminals for exchanging various control signals including a refresh control signal and various signals including data and address signals with an external circuit, a memory cell array, an address selection circuit, and a write / read operation. An internal circuit including a control circuit, which performs data write, read, and refresh operations according to various signals transmitted and outputs a predetermined signal, and a predetermined circuit in response to the active level of the signal transmitted to the refresh control signal input terminal. A refresh timer for generating a refresh request signal at a timing; and a plurality of signal terminals in a normal operation mode according to an internal boundary scan control signal including a data shift clock provided corresponding to each of the plurality of signal terminals. Signal terminal other than the signal terminal corresponding to the refresh control signal of A signal is transmitted between the child and the internal circuit, and between the signal terminal corresponding to the refresh control signal and the refresh control signal input terminal of the refresh timer. Forming a shift register of stages, sequentially shifting the test data from the outside to the rear stage side, transmitting a signal of a predetermined stage to the internal circuit, taking in a signal from the internal circuit to a predetermined stage, and A plurality of registers for sequentially shifting the embedded signal to the subsequent stage side and outputting a signal from the last stage, and a refresh request signal from the refresh timer in the normal operation mode according to the internal boundary scan control signal, During the signal shift operation in the internal test mode, the data shift clock is selected to request refreshing of the internal circuit. Dynamic memory, characterized in that it comprises a selection circuit for transmitting a signal input terminal. 2. An internal test mode signal having an active level in response to external test data, a test mode setting signal and a test clock, and an active level at a predetermined timing during a predetermined period of the active level of the internal test mode signal. A data shift control signal, a data shift clock that sequentially becomes an active level during the active level of the data shift control signal, and an inactive level of the data shift control signal during the active level of the internal test mode signal. A boundary scan test control circuit that generates an internal test execution signal that becomes active level for a predetermined period and a test execution result transmission control signal that becomes active level later than the internal test execution signal during the period To A first input terminal connected to a corresponding signal terminal (or a corresponding signal input / output terminal of an internal circuit) and a first output connected to a corresponding signal input / output terminal (or a corresponding signal terminal) of the internal circuit. An end, a second input end for receiving an output signal (data from the outside in the front stage) on the front stage side when the shift register is formed, and a signal for transmitting to the rear stage side (in the last stage, Output the signal to the outside)
A second output end, the signal of the first input end is transmitted to the first output end while the internal test mode signal is at the inactive level, and the data is transferred during the active level period. During the period of the active level of the shift control signal, the signal of the second input terminal is taken in and held in synchronization with the data shift clock and is transmitted to the second output terminal of the inactive level of the data shift control signal. The held signal is transmitted to the second output terminal in response to the active level of the internal test execution signal, and the signal of the first input terminal is transmitted in response to the active level of the test execution result transfer control signal. 2. The dynamic memory according to claim 1, wherein the dynamic memory is a circuit which takes in and holds and transmits it to the second output terminal. 3. A self-refresh control circuit for generating an internal refresh control signal by determining that the internal circuit is in a low power supply voltage operating state, and supplying the internal refresh control signal to a refresh control signal input terminal of a refresh timer. The dynamic memory according to claim 1, wherein