JPH07240833A - Image processing unit - Google Patents

Abstract

PURPOSE:To reduce the compensation processing time while minimizing the scale of the hardware by providing a random access memory section and an image data read means reading image data stored in the random access memory section to the processing unit. CONSTITUTION:Image data are stored in a random access memory to store image data, and the image data stored in the random access memory are read therefrom in a direction and a sequence to correct simultaneously distortion in a 2-dimension picture in the image data resulting from a tilted arrangement direction of photoelectric conversion elements of a line sensor with respect to a main scanning direction and a displacement of the 2-dimension picture in the image data resulting from a deviation of an image pickup object image from a regular posture stored in a storage means. Then tilt angles of image sensors I1, I2 are set respectively to be theta1, theta2 and a tilt angle of an original is set to be alpha, then a tilt read address of the memory reserved corresponding to the image sensors I1, I2 is obtained by calculation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image handling apparatus, and more particularly, to an image handling apparatus that captures image information using an image sensor such as an area sensor or a line sensor.

[0002]

2. Description of the Related Art For example, an image handling apparatus which moves a line sensor in a direction orthogonal to the line sensor with respect to a subject image and takes in whole image information has been widely adopted including a facsimile, and in recent years has also been adopted in an OA field. Has been done.

Image capturing processing by the line sensor of the image handling apparatus will be described with reference to FIGS. 27 and 28. Figure 2
7, the line sensor LS is electrically horizontal (H).
Direction, that is, the main scanning direction, and the vertical (V) direction, that is, the sub-scanning direction is performed by mechanically moving the line sensor. Normally, when installing the line sensor, it is almost impossible to make the horizontal scanning direction and the vertical scanning direction into a right-angled relationship because there is a displacement in arrangement. To do. When the image information is captured by using the line sensor LS while maintaining the inclination angle θ and the captured image is reproduced on the monitor as it is, the reproduced image is
Originally, an image that should be rectangular like the image G1 becomes a distorted parallelogram as shown in the image G2. Even if the subject image is accurately adjusted in the horizontal direction, the inclination angle is difficult to solve because the line sensor itself is not accurately adjusted in the horizontal direction. It is not impossible to adjust the mounting position of the line sensor with high accuracy at the factory stage, but considering the number of man-hours for that, the cost will increase and the solution is difficult.

Therefore, it is conceivable to electrically compensate image distortion caused by the inclination relationship between the line sensor and the subject image. The principle will be described with reference to FIG. 28. A signal from the line sensor is temporarily written in a field memory 202 capable of storing image data for one screen through a terminal 201A of a switch 201. Writing to the field memory 202 is performed by the memory controller 2
It is performed according to the write address supplied from 03. The image written in this way is an inclined image G2 when read out and reproduced as it is. Therefore, at the time of reading, the switch 201 is switched, and a read address is generated from the memory controller 203 so that the tilted image G2 becomes a normal image G1 to read the image in which the distortion is compensated from the field memory 202.

[0005]

In the image handling apparatus as described above, when writing and reading the image data obtained from the line sensor to the field memory having a capacity capable of storing the image data for one screen, Reading is performed using the read address generated to obtain an image that compensates for the distortion caused by the inclination.

However, in such an apparatus, a field memory having a capacity of one screen has to be prepared as a conversion memory for compensation, which causes a problem that the hardware scale becomes large. Also, after writing the image data from the line sensor to the conversion memory once,
There is also a problem that a relatively long processing time is required to obtain the final image because the reading is performed again and the compensation is performed. Such a problem naturally occurs in the case where the area sensor is used as the image sensor.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an image handling apparatus which shortens the compensation processing time while minimizing the hardware scale.

[0008]

In order to solve the above-mentioned problems, an image handling apparatus according to the present invention uses a line sensor to photoelectrically convert an imaged object image held in a fixed posture by a predetermined holding unit. An image handling apparatus configured to obtain image data representing a two-dimensional image by scanning in a main scanning direction which is an array direction of elements and a sub scanning direction which is a moving direction of the line sensor, and stores the image data. A random access memory section to which a predetermined capacity is allocated, and the image data resulting from the arrangement direction of the photoelectric conversion elements of the line sensor being inclined with respect to the reference direction that is the normal main scanning direction. Distortion of the two-dimensional image shown and deviation from the normal posture when the image pickup target image is held in a fixed posture by the holding means. 2 represented by the image data resulting from the
The image data stored in the random access memory unit by effectively scanning the random access memory unit in the direction and order for simultaneously correcting the distortion and displacement corresponding to both the displacement of the three-dimensional image. And image data reading means for reading.

[0009]

According to the present invention, a two-dimensional image is obtained by scanning the imaged object image held in a fixed posture in the main scanning direction, which is the arrangement direction of the photoelectric conversion elements of the line sensor, and the sub-scanning direction, which is the moving direction of the line sensor. To obtain the image data, the image data is stored in a random access memory for storing the image data, and the 2
From the random access memory in a direction and order for simultaneously correcting the distortion of the two-dimensional image and the displacement of the two-dimensional image of the image data due to the deviation from the normal posture when the image capturing target image is held by the holding unit. The stored image data is being read.

[0010]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a processing conceptual diagram for explaining an example of an image handling apparatus related to the present invention. In this example,
As shown in FIG. 3A, image data stored in a field memory by being tilted and read by a line sensor as an image sensor is compensated for distortion due to the tilt. When reading according to the read address, instead of using a field memory that stores image data for one screen as in the conventional case, a width WD that is slightly wider than the vertical width wd when reading in the tilt direction in FIG. A memory 2 having a capacity of line × (1 horizontal pixel) is prepared. In FIG. 6B, this memory capacity is conceptually shown, and the dotted line shows the reading direction. After reading the image data according to the read address in the direction of the dotted line in the state of FIG. 7B, the oldest data is erased and the data for the next one line is recorded in the address area. After reading the image data for one minute, the process of storing the image data for one new line at the address written first in the memory storage area is repeated. That is, a small-capacity memory is cyclically used, and the oldest image data is always erased and the latest image data is stored in association with each other. As a result, the data before and after the data to be read is always stored in the memory between FIGS. In this way, when the storage and read processing of one image data is completed in the state shown in FIG. 7D, finally the image in which the tilt is compensated is obtained as shown in FIG. If the requirements to be included in the memory 2 in the above-mentioned example are arranged, the inclination is formed corresponding to the inclination angle formed by the arrangement direction of the photoelectric conversion elements of the image sensor with respect to the reference direction which is the normal main scanning direction. The side obtained by projecting the scanning locus in one direction in the normal main scanning direction is the first side (n), and the side projecting the scanning locus in one direction in the regular sub-scanning direction is the second side ( A capacity smaller than the capacity (the capacity of the field memory) corresponding to the data of one screen related to the image to be captured, as long as the amount of data that can represent the area (n × m) surrounded by the rectangle (m) is storable. Can be said to be a random access memory unit to which is assigned. As a matter of course, the random access memory unit may be a dedicated RAM provided for the purpose of correcting the mounting angle of the image sensor, and of course, the RAM provided for other purposes can be specified. The manner of allocating the regions of the above for the above purpose is also defined as being subsumable. Further, in relation to the random access memory unit (memory 2) defined as described above, this apparatus follows the order of this scanning for each scanning in the main scanning direction by the image sensor, and Regarding the scanning to the sub-scan by the sensor, the random access memory unit is provided with the image sensor according to a cyclical sequence which is repeated every time the progress corresponding to the second side is performed according to the degree of the progress of the scan. Image data writing means for writing image data, image data written in the random access memory section by the image data writing means according to the order of this scanning with respect to scanning in the main scanning direction, and
Regarding the scanning to the sub-scan by the image sensor, image data reading means for sequentially reading in a cyclical sequence that is repeated every time the movement corresponding to the second side is performed according to the progress of the scanning, Comprising.

FIG. 2 is a block diagram showing the configuration of the device for writing and reading image data to and from the memory described with reference to FIG. Image data from an imager such as a line sensor is written in the memory 2 via the 3-state buffer 1. This writing is sequentially performed in the memory 2 shown in FIG. 1, and its address is generated by the memory controller 3. The reading is performed according to the inclined read address shown by the dotted line in FIG. The read address is generated from the memory controller 3 which receives the diagonal read address generated by the read address generation unit 4 based on the tilt data.

FIG. 3 shows a principle of generating a read address necessary for reading the image data stored in the memory 2 in an oblique direction. In the figure, θ indicates a tilt angle, (x, y) indicates a normal coordinate, and (x ′, y ′) indicates a fetched (stored) coordinate in the memory. From the figure, the relationship of (y′−y) / x = tan θ x / x ′ = cos θ is obtained, and in the end, the coordinates (oblique read address) x ′ and y ′ required for reading are x ′ = x / It is obtained by cos θ y ′ = x · tan θ + y.

FIG. 4 is a diagram for explaining the read address of the image data stored in the memory 2, which is indicated by a solid line in the memory in which the number of pixels in the horizontal direction is n and the number of lines in the vertical direction is m. A read address is generated. The line of this read address preferably passes through the center indicated by the black dot,
Considering the tilt angle θ, the initial read coordinates are (0, m /
2−n / 2 · tan θ), and generally read addresses x ′ and y ′ are as follows: x ′ = x / cos θ (1) y ′ = x · tan θ + y + m / 2−n / 2 · tan θ (2), and n = 2048 and m = 64, the absolute value of the corrected angle θ is smaller than 1.7.

An example of the x'address generating circuit in this case is shown in FIG.
Is shown in. 1 / cos θ and the output of the latch circuit 12 are input to the addition circuit 11, and the addition output is input to the latch circuit 12. The latch circuit 12 sends a latch output obtained by cumulatively adding 1 / cos θ to the adder circuit 11 in response to the pixel clock CLK, and is reset by the horizontal scanning direction synchronizing signal HD.

FIG. 6 similarly shows an example of the y'address generating circuit. Tan θ and the output of the latch circuit 22 are input to the addition circuit 21, and the cumulative addition data is latched in the latch circuit 22. The latch circuit 22 performs a latch operation in response to the pixel clock CLK and is reset by the clock HD in the main scanning direction (horizontal direction). The V counter 23 is a counter in the line direction, counts the clock HD, and is reset by the vertical clock VD.
The adder circuit 24 adds the output from the latch circuit 22 and the output (y) from the V counter 23, and sends the added output to the adder circuit 25. The addition circuit 25 adds the addition output from the addition circuit 24 and m / 2−n / 2 · tan θ, and y ′ = x · tan θ + y + m / 2−n / 2 · tan θ ( 2) is obtained. Since the memory 2 is used cyclically as described above, the output from the adder circuit 25 is output as 6-bit data in LSB units.

FIG. 7 is a diagram showing a configuration example of the memory controller 3, which has a V counter 31, an H counter 32, and changeover switches 33 and 34. The V counter 31 counts the clock HD and is reset by the clock VD. The H counter 32 counts the pixel clock CLK and is reset by the clock HD. Changeover switch 33
Reads the read address y ′ and the counter output of the V counter 31 according to the time of writing (W) and the time of reading (R).
Switch and output as memory address. Similarly, the changeover switch 34 includes a read address x ′ and an H counter 32.
The counter output from the switch is switched and output according to writing and reading. The changeover switches 33 and 34 are
At the time of writing, the V counter 3 supplied to the L terminal
1 and the output of the H counter 32 are output as the write address, and at the time of reading, the addresses y ′ and x ′ supplied to the H terminal are output as the read address.

FIG. 8 shows the memory 2 for the above-mentioned image input data.
A timing chart of write and read operations to and from is shown. Write address W (2,4), W (3,
4), W (4,4), W (5,4), ... And read addresses R (x ′, y ′) are alternately generated, and data is written in the memory 2 in accordance with the R / W signal.

According to the above-described example, as shown in FIG. 9, m lines (for example, 6
Immediately after the data of four lines) is written in the memory, the image data (output data) in which the inclination is compensated is obtained from the memory.

FIG. 10 is a diagram for explaining a cyclical use form of the memory 2 when the inclination angle θ = 1 °. In the figure, W indicates a write address and R indicates a read address. In this example, m = 64, n = 2048, 128 kbyte
This is an example of the case of using a (1 Mbit) memory. FIG. 7A shows the memory storage area at the start of writing, and the data of the first line is recorded in the upper end area according to the write address W. , The other areas are empty. In addition, yw described on the right side of (A) to (G) in the figure is a write line address of the memory corresponding to each figure, and y is an address as its normal coordinate,
y'indicates an address in the vertical direction at the time of oblique reading.

As shown in FIG. 3B, after the data is written at the write address W in the lower end area (yw = 63) of the memory, as shown in FIG. While being written in the uppermost area (yw, y = 0),
Y ′ = 1 obtained by substituting x = 0 and y = 0 into the equation (2)
Y '= obtained by substituting x = 2047 and y = 0 from 4
Inclination-compensated image data is read according to the inclination read address R reaching 49.

Further, writing is subsequently executed, and (D)
At the time of writing yw, y = 16 as shown in, the read address is y ′ = 30 to 65, but the memory capacity is m.
= 64, the address exists only up to y '= 63. After the read address R1 up to y' = 63, the address returns to the upper end of the memory area and the read address R2 up to y '= 1. The image data is read in accordance with.

As shown in FIG. 7E, yw, y = 32
When y is reached, yw, y =
When the number reaches 48, the read address y ′ = 46 to 81
(46 to 17) and image data is read according to the gradient read addresses R1 and R2 corresponding to 62 to 97 (62 to 33), and yw and y = 63 as shown in FIG.
, The read address y ′ = 77 to 112 (13 to
The image data is read according to the gradient read address R of 48).

The effect of reducing the memory capacity according to the above example will be described based on specific numerical values as compared with the conventional case. When one image data is composed of 2048 × 2048 × 8 bits, the number of horizontal pixels is 2048. The number of vertical lines can be corrected with one 2048 × 64, one 1 MbS RAM, and the correction range is from tan θ = m / n to an absolute value of θ degrees of 1.7. The read address y'from the memory is
From 64 = 2 ⁶ to 6 bits, only the lower 6 bits need be supplied to the memory. Therefore, the capacity of the memory is 64/2048 = 1/32, which is not only a great saving, but also the image data is read out with a delay of 64 lines, which is much larger than the conventional delay of 2048 lines. The processing can be speeded up. The above is an example of the line sensor, but the same can be considered when the image sensor is an area sensor. At this time, when the horizontal reading direction of the image sensor and the inclination of the input image are θ, the conversion address is given by the equation (3):

[0024]

[Equation 3]

[0025]

The above example is an example of compensating the inclination θ of the image sensor when a subject image (original) is captured by the image sensor.
As shown in FIG. 1, the document mounting inclination angle α actually exists. Even when such an inclination angle exists, it can be dealt with as follows.

Also in this case, the read addresses x'and y'can be obtained according to the equation (4), as in the above-mentioned example.

[0028]

[Equation 4]

Further, there is a relationship of tan (θ + α) = m / n.

An image handling device for compensating for the two inclination angles θ and α as shown in FIG. 11 is constructed, for example, as shown in FIG. In FIG. 12, the components designated by the same reference numerals as those in FIG. 2 indicate components having the same function. In the E ² PROM 6, for example, inclination data θ of the image sensor set at the time of factory adjustment is stored in advance. The CPU 5 calculates the equation (4) based on the inclination data θ from the E ² PROM 6 and the original inclination (input image inclination) data α, and sends the operation result to the read address generating circuit 4.

FIG. 13 is a diagram for explaining an embodiment of the present invention, which is an example in which inclination compensation is possible in the case where one image is read by two image sensors in order to obtain a higher definition image. is there. When the inclination angles of the image sensor I1 and the image sensor I2 are θ1 and θ2, respectively, and the inclination angle of the document is α, the image sensors I1 and I2 are
Gradient read address (x1 ', y
1 ') and (x2', y2 ') are obtained by the same calculation as described above, that is, according to the equations (5) and (6).

[0032]

[Equation 5]

[0033]

[Equation 6]

Next, another configuration example related to the present invention will be described. This example relates to an image handling device that compensates for color shift due to a placement shift of R, G, and B color separation filters of an image handling device using an RGB in-line image sensor.

Since the R line sensor, the G line sensor and the B line sensor in a normal image handling apparatus are spatially separated as shown in FIG. 14, data obtained by each line sensor at the same timing. Are data for different pixels. In the figure, an example is shown in which each line sensor is arranged to be separated by 21 pixels.

In FIG. 14, d0,0, d0,1 and d0,2
, D0,3, ... are R at a certain timing (0th line)
Pixel sensor for line sensor # 1, # 2, # 3, # 4
These data strings are represented as D0 in the output from the. Similarly, the data string D1 is a data string obtained from the sensors # 1 to # 4 at the next timing (first line), and D2 is the data string obtained at the next timing.

Similarly, a data string consisting of outputs d21,0, d21,1, d21,2, ... From the three sensors of the G line sensor is represented by D21, and d22,0, d22,1, d22,2. A data string consisting of, ... Is represented by D22.

Also for the B line sensor, the output d42,0,
The data sequence consisting of d42,1, d42,2 ... is D42, and the output d4
A data string composed of 3,0, d43,1, d43,2, ... Is represented by D43.

FIG. 15 shows a configuration diagram for storing these line sensor outputs in the corresponding memory.
Outputs from the R line sensor 50R, the G line sensor 50G, and the B line sensor 50B are respectively output from the image pickup unit 51.
After the well-known imaging process is performed on R, 51G, and 51B,
Converted into digital data by the A / D converters 52R, 52G and 52B, and the R memory 53R, G memory 53G and B
It is stored in the memory 53B.

FIG. 16 shows the R memory 53 shown in FIG.
Input data to the R, G memory 53G and B memory 53B are arranged in the order of timing (that is, 0 line, 1 line, ..., 2).
1 line, ..., 42 lines). As is clear from the figure, the data input at the beginning of the 0th line is d0,0, d21,0, d42,0, and each memory has data shifted by 21 pixels corresponding to the line sensor separation distance. Has been. Therefore, the R memory 53 for the same pixel
Input data (for example, data d42,0) to the R, G memory 53G and the B memory 53B is obtained in the 0th line in the B memory 53B and in the G memory 53 as shown by the shaded portion.
It is the 21st line in G and the 42nd line in the R memory 53R.

FIG. 16 is a timing chart of data in the normal scan state, but the timing is different in the double speed scan. 17A, 17B and 17C, the normal scan, the double speed scan and the 4 scan are shown.
The timing relationship of the data string of the input data to each memory at the time of double speed scanning is shown.

In the normal scan shown in FIG. 16A, as described with reference to FIG. 16, each memory input is obtained as data shifted by 21 lines. On the other hand, in the double speed scan shown in FIG. 7B, as the data input to each memory, the integrated value (average value) data of the two data in the normal scan is supplied as one data. For example,
The data string D01 of the 0th line is the integrated value data of the data strings D0 and D1, and the data string D23 is the data strings D2 and D.
Obtained as an integrated data value of 3.

By the way, in this case, the data string corresponding to the B memory input data string D42 43 is obtained as the 21st line data string at the R memory input, as is apparent from FIG. 17B. , G memory input does not exist and only appears as data strings D41 42 and D43 44 on the 10th and 11th lines. Conventionally, since either one of the data strings D41 42 or D43 44 is used, a color shift will occur.

Similarly, during the 4 × speed scan, as shown in FIG. 17C, the B memory input data string D42 4
Since there is no input data string to the R memory and G memory corresponding to 5, there is no choice but to use one of the two data strings, and a color shift occurs.

Therefore, in this example, when the corresponding pixel data exists in the form of straddling two adjacent data strings, the two data are multiplied by a predetermined weighting coefficient to obtain a more appropriate data string. In view of the above, the problem of color misregistration is reduced.

FIG. 18A shows a block diagram of the configuration of this example. The R line data from the R line sensor is delayed by 1H by the 1H delay unit 101R, and the multiplication unit 1
02R is multiplied by the weighting coefficient kr1. Further, the R line data is multiplied by the weighting coefficient kr2 in the multiplication unit 103R. The multiplication results of the multiplication units 102R and 103R are added by the addition unit 104R to obtain R memory input data R ′.

Similarly, the G line data is stored in the 1H delay unit 1
After being delayed by 1H by 01G, the multiplication unit 102G multiplies the weighting coefficient kg1 and supplies the result to the addition unit 104G. The G line data is also multiplied by the weighting coefficient kg2 in the multiplication unit 103G, and the multiplication unit 10G in the addition unit 104G.
It is added with the output of 2G and becomes the data input G'to the G memory.

On the other hand, the B line data is not processed at all and is used as it is as the input data to the B memory. The weighting factors kr1, kr2, kg1 and kg2 are shown in FIG.
As shown in (A), it changes depending on the scan speed and is supplied from the CPU 105 to each multiplication unit. FIG.
In (B), the relationship between the scan speed and the weighting coefficient is shown as a table.

As is apparent from FIG. 17, at normal speed, the R line data and G line data are
Since it is output as it is, kr2 and kg2 are set to "1" and the others are set to "0".

On the other hand, at the double speed scan (× 2), R
Since the line data is output as it is, kr1 and kr
2 is set to "1" and the G line data takes the average value of two adjacent data, so kg1 and kg2 are "1 /"
Set to 2 ".

Further, at the time of 4 × speed scanning (× 4), R
The line data is 2 as shown in FIG.
Since it suffices to find the intermediate value of two data strings, for example D40,43 and D44,47, kr1 and kr2 are set to "1/2", but the G line data must be weighted appropriately. Data strings D41 44 and D45 48 in FIG. 17C
To find the data sequence that most closely matches D42 45 from
A 3: 1 weighting is required for both data. Therefore, "1/4" as kg1 and "1" as Kg2
/ 4 "is set.

FIG. 19 shows an operation timing chart at the time of double speed scanning in the example shown in FIG. In the figure, each line data, 1H delay output, and memory input are shown. Further, the value of the weighting coefficient to be multiplied by each data string is shown at the right end of the figure. As described above, the R memory input data corresponding to the B memory input data string D42 43 is obtained as it is, but the G memory input data is the average data string of the G line data string D43 44 and the 1H delay output data string D41 42. (D41 42 + D43 44) / 2
Is obtained as G memory input data.

As is apparent from FIG. 19, according to the present example, color misregistration can be compensated, but when writing to the R, G, and B memories, data necessary for image processing is different in time and timing. Will be entered in. Therefore, a specially devised hardware configuration is required for processing using data input at different timings. The following configuration example related to the present invention is an example in which data is input to each memory at the same time and timing.

FIG. 20 is a block diagram showing the configuration of the main part of this example. In this example, the output data R'to the R memory is matched with the timing of the other output data G'and B '. G line data is stored in the memory controller 1
Under the control of 40, a G having a capacity of storing, for example, 32 lines of data via the 3-state buffer 111.
The data is stored in the buffer memory 112, and the data is read at a timing delayed by 21 lines for timing adjustment with the R line data. The data read from the G buffer memory 112 is input to the registers 113 and 114, and the output of each register 113 and 114 is the multiplication circuit 11
The weighting factors kg1 and kg2 are multiplied by 5 and 116, then added by the adder circuit 117 and input to the register 118. The output of the register 118 becomes G'data to the G memory.

Similarly, the B line data is stored in the B buffer memory 122 having a capacity for recording data for 64 lines via the 3-state buffer 121, and for example, 42 for the timing adjustment with the R line data. Data is read at the timing delayed by the line. In this case, the read data does not need pixel interpolation, and the input data B ′ to the B memory can be directly obtained through the registers 123 and 124.

The R line data is set to 1 by the 1H delay unit 131.
After being delayed by H, the multiplication circuit 132 weights the coefficient k.
It is multiplied by r1. The R line data is also multiplied by the weighting coefficient kr2 in the multiplication circuit 133, and the addition circuit 13
At 4, the output from the multiplication circuit 132 is added. The addition output from the addition circuit 134 is output as R ′ data via the register 135.

The CPU 150 supplies the above-mentioned weighting coefficient to each unit and controls the memory controller 140. Registers 113, 114, 118, 123, 1
24 and 135 are used for compensating for the time lag caused by the processing time of each line data processing system.

FIG. 21 shows a timing chart of the data strings of respective parts at the time of normal scanning in the example shown in FIG. As shown in FIG. 18B, since the weighting coefficients kr1 and kr2 supplied to the multiplication circuits 132 and 133 are "0" and "1", respectively, the R'line data is the same as the R data.

At the time of inputting the data line D63 of G line data, the data read from the G buffer memory 112 is D42 and D43 in order to match the timing with the pixel data of the R'line data line D42 and obtain the corresponding data. , Are input to the registers 113 and 114, respectively. In this case, since the weighting factors kg1 and kg2 supplied to the multiplication circuits 115 and 116 are "1" and "0", the data string of D42 is output as it is as the G'line data string D'42. become.

At the same time when the data string D84 of B line data is input, the data string D42 is read from the B buffer memory 122 for timing adjustment, and the register 1 is read.
It is output as a B'line data output via 23 and 124.

While FIG. 21 shows the operation timing of each data column in the example shown in FIG. 20, FIG. 22 shows the operation timing of each data unit corresponding to each pixel. R
R'line data output is obtained for / G / B input data. Further, in the G line data processing, since two lines of data delayed by 21 lines are read from the G buffer memory 112, the data read according to the G buffer memory address is stored in the register 113.
And 114. The G'line data output is obtained by the above-mentioned weighting calculation based on the output data from the registers 113 and 114. Further, for the B line data, in order to match the time with the R line data, the data delayed by 42 lines from the B buffer memory 122 is read, and the B ′ line data output is performed via the registers 123 and 124. can get. As a result of such processing, as shown by the shaded area in the figure, R ′, G ′, corresponding to the same pixel,
The B'line data string output is obtained at the same timing.

FIG. 23 is a timing chart of data of each part for explaining the operation at the time of double speed scanning in the above example. When scanning at double speed, the weighting coefficient is
The coefficients are as shown in FIG. 18B, and the data used for the calculation is also different from that in the normal scan as shown in FIG. 17B. Therefore, at the same time as FIG.
R ', G', and B'line data outputs corresponding to the same pixel are obtained at the same timing. Obviously, the same operation timing chart can be used to explain the case of quadruple speed scanning.

FIG. 24 shows an operation timing chart for the same line data sequence as in FIG. 21 at the time of double speed scanning. As shown by the shaded area, R ', G', B'line data output for the same pixel is shown. Are obtained at the same timing.

FIG. 25 shows the B memory and G in the above example.
A block diagram is shown illustrating an example of a memory controller that generates B and G memory addresses to supply to a memory. This controller uses R line data for G
When the line data and the B line data are read by adjusting the timing, the read address is offset and generated.

The WV counter 201 is a counter for generating an address in the line (vertical) direction for writing, counts the clock HD, and is reset by the clock VD.
The output of the WV counter 201 is the changeover switches 206 and 2
It is sent to each terminal W of 07. Changeover switch 206
The terminals 207 and 207 operate so that the terminal W is selected and the counter output from the WV counter 201 is supplied to the B memory and the G memory when writing to the memory.

The H counter 204 has a pixel clock CLK.
Are counted and reset by the clock HD, and the count output is sent as a memory address. The B offset value of the address corresponding to the time difference from the R data is supplied to the BV counter 202, and the counting operation is started from this offset value. In the above example, the offset value is set to "42". This offset value is a value that depends on the scan speed.

The GV counter 203 is the BV counter 20.
As in the case of 2, clock HD is counted and clock VD
The count output is sent to the G1 terminal of the changeover switch 207. This count output is added by the adder circuit 2
At 05, "1" is added and sent to the G2 terminal. Therefore, two consecutive read address data for reading two adjacent data are sent to the terminals G1 and G2. The G offset value set in the GV counter 203 is “21” in the above example.

The change-over switch 206 selects the terminals W and B once and outputs the B memory address. Further, the changeover switch 207 sequentially selects the terminal W and the terminals G1 and G2 and outputs the G memory address.

FIG. 26 shows the relationship between the scan speed, the weighting coefficient, the B offset value, and the G offset value in the above example. In the figure, the numbers shown as the B offset value and the G offset value indicate conceptual addresses, and the numbers in parentheses indicate the addresses to actually start.

In each of the above embodiments, the memory and control circuit used in each section are of course shared if necessary.

[0071]

As described above, according to the image handling apparatus of the present invention, it is possible to quickly capture image information with a small-scale circuit configuration.

[Brief description of drawings]

FIG. 1 is a processing conceptual diagram for explaining an example of an image handling apparatus related to the present invention.

FIG. 2 is a configuration block diagram of an apparatus for writing and reading image data to and from the memory described in FIG.

FIG. 3 is a diagram showing a generation principle of a read address necessary for reading image data stored in a memory 2 shown in FIG. 2 in an oblique direction.

FIG. 4 is a diagram for explaining a read address of image data stored in a memory 2.

5 is a diagram showing an example of an x'address generating circuit in FIG.

6 is a diagram showing an example of a y'address generating circuit in FIG.

FIG. 7 is a diagram showing a configuration example of a memory controller 3.

FIG. 8 is a diagram showing a timing chart of writing and reading operations of image input data to and from the memory 2.

FIG. 9 is a diagram for explaining the operation and effect of the above example.

FIG. 10 is a diagram for explaining a cyclic use form of the memory 2 in the above example when the inclination angle θ = 1 °.

FIG. 11 is a diagram for explaining an inclination angle θ of an image sensor and an attachment inclination angle α of a document.

12 is a configuration diagram showing an image handling device for compensating for the two inclination angles θ and α shown in FIG. 11. FIG.

FIG. 13 is a diagram for explaining an example of the present invention.

FIG. 14 is a diagram for explaining another configuration example related to the present invention.

FIG. 15 is a configuration diagram for storing the output of each line sensor in FIG. 14 in a corresponding memory.

16 is an R memory 53R and a G memory 5 in FIG.
Input data to the 3G and B memory 53B is arranged in the timing order (that is, 0 line, 1 line, ..., 21 line ,.
42 line).

FIG. 17 is a diagram showing a timing relationship regarding a data string of input data to each memory at the time of normal scanning, double speed scanning and quadruple speed scanning.

FIG. 18 is a configuration block diagram of an image handling apparatus related to the present invention.

19 is a diagram showing an operation timing chart at the time of double-speed scanning in the configuration shown in FIG.

FIG. 20 is a configuration block diagram showing a main part of an apparatus related to the present invention.

FIG. 21 is a diagram showing a timing chart of data strings of respective parts at the time of normal scanning in the example shown in FIG. 20.

FIG. 22 is a diagram showing an operation timing of a data unit corresponding to each pixel.

FIG. 23 is a timing chart of data of each part for explaining the operation during double speed scanning.

FIG. 24 is an operation timing chart for a line data string similar to FIG. 21 at the time of double speed scanning.

FIG. 25 is a block diagram showing an example of a memory controller that generates a B memory address and a G memory address to be supplied to the B memory and the G memory.

FIG. 26 is a diagram showing a relationship between a scan speed, a weighting coefficient, a B offset value, and a G offset value.

FIG. 27 is a diagram illustrating an image capturing process by a line sensor of a conventional image handling device.

FIG. 28 is a block diagram showing a configuration of an image capturing section using a line sensor of a conventional image handling device.

[Explanation of symbols]

1 3 State Buffer 2 Memory 3 Memory Controller 4 Read Address Generation Circuit 5 CPU 6 E ² PROM

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Claims (1)

[Claims] 1. An image pickup target image held in a fixed posture by a predetermined holding means is moved by a line sensor in a main scanning direction which is an arrangement direction of photoelectric conversion elements of the line sensor and a sub-scanning direction which is a moving direction of the line sensor. An image handling apparatus configured to obtain image data representing a two-dimensional image by scanning, a random access memory unit to which a predetermined capacity for storing the image data is allocated, and a regular main scanning direction. Distortion of the two-dimensional image represented by the image data due to the arrangement direction of the photoelectric conversion elements of the line sensor being inclined with respect to the reference direction.
The distortion and the displacement correspond to both the displacement of the two-dimensional image represented by the image data due to the deviation from the normal posture when the image capturing target image is held in the constant posture by the holding unit. Image data reading means for reading the image data stored in the random access memory unit by effectively scanning the random access memory unit in a direction and order for simultaneously correcting Image handling equipment.