JPH0724021B2 - Multi-valued ALU - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Multilevel signal source, memory array, first selecting means,
It is composed of a second selecting means and an output circuit.

From the multi-valued signal source, signals representing respective logic values of multi-valued logic are generated.

The memory array is provided with an address line group including a large number of address lines for each function to be operated. Any multi-valued logic signal appears on the address line of each address line group by the program based on the truth table of the corresponding function.

Any one of the plurality of address line groups is selected by the first selecting means to which a signal designating a function to be operated is given.

One address in the selected address line group
The line is selected by the second selection means supplied with the input signal, and the logical value signal of the line is guided through the output circuit.

Table of contents (1) Background of the invention (2) Outline of the invention (2.1) Purpose of the invention (2.2) Structure and effect of the invention (3) Description of embodiments (3.1) Definition of multivalued logic function (3.2) Field programmable multi Value logic function circuit (3.3) Decoder (3.4) Other example of address switch (3.5) Mask programmable multi-value logic function circuit (3.6) Multi-function circuit (3.7) Multi-value ALU (3.8) Multi-value MAX / MIN function Circuit (3.9) Multi-value full addition circuit (3.10) Multi-value full subtraction circuit (3.11) Multi-value full multiplication circuit (3.12) Multi-value total division circuit (3.13) CMOS multi-value ALU (1) Background of the invention Programmable multi-level ALU that is the basis for constructing multi-level logic system and is suitable for IC implementation
(Arithmetic and Logic Unit).

2. Description of the Related Art Multi-valued logic and its arithmetic circuit have been actively researched as a means for complementing or overcoming some limitations of binary logic which is the basis of many digital circuit systems including computers. The binary logic handles two values of 0 and 1, and the signal used in the binary logic circuit system takes two levels corresponding to these two values, whereas the multivalued logic has three or more values. The signal used in the multi-valued logic circuit system has three or more levels.

Multilevel logic (circuit system) is binary logic (circuit system)
It is said that it has the following advantages compared with.

1) It is possible to describe an indeterminate state between 0 and 1 (for example, in the case of 3 values).

2) The wiring area and the number of pins on the IC substrate can be reduced, and the effective integration level can be increased. For example, in the case of 64 levels, 1/6 wiring area of a binary logic circuit is sufficient.

3) The realization of a 10-value machine enables the use of the same logic as humans, so the encoder and decoder required in a 2-value machine are unnecessary.

The multi-valued ALU is the most basic for constructing a multi-valued logic system having such features, especially a system replacing the conventional binary computer. This multivalued ALU must be capable of performing arbitrary multivalued logical operations.
There are more than a dozen types of multi-valued logical operations, including well-known operations such as MAX, MIN, addition, subtraction, multiplication, and division. According to a simple combination, in the case of n-valued r variables, there are n n-th powers of r-th power. For example, in the case of 3-valued 2-variable, the type of multi-valued logical operation is 3 to the power of 3,
In other words, it is 19683, and there are about 4.3 billion ways in a four-value two variable. It is almost impossible to design a multi-valued ALU capable of executing such a huge number of multi-valued logical operations in the usual way.

(2) Outline of the Invention (2.1) Object of the Invention An object of the present invention is to provide a programmable multi-level ALU capable of executing an arbitrary operation.

(2.2) Structure and effect of the invention A multi-valued ALU according to the present invention is connected to a plurality of multi-valued signal sources that generate signals respectively representing a plurality of logic values of the applied multi-valued logic, and are connected to these signal sources, respectively. A plurality of signal lines and a plurality of different functions to be operated are provided for each, and programmed according to a truth table of each function, so that a plurality of signal lines connected to any one of the signal lines at a node are connected. A memory array including an address line group consisting of address lines, a first selecting means for selecting any one of the address line groups by a select signal for selecting a function to be operated, and a multi-valued input signal A second selection means for selecting at least one address line in the selected address line group, and the first and second selection means. It is characterized in that it is provided with an output circuit for outputting a signal representing a logical value obtained from the selected address line.

Execution of a multivalued logical operation is equivalent to generation of a multivalued logical function that represents the result of the operation. A desired plurality of multi-valued logic functions can be easily programmed in the memory array according to their truth tables. Then, the first selecting means can select one of the programmed multiple-valued logic functions, and the variable is selected from the selected multiple-valued logic functions by providing an input signal representing the variable. A signal representing the function value can be obtained.

In this way, it becomes possible to program a multi-valued ALU that operates an arbitrary multi-valued logical function using a truth table,
In addition, the multi-valued ALU can be operated to derive the programmed calculation result.

(3) Description of Embodiments (3.1) Definition of Multivalued Logic Function There are two types of methods for defining a multivalued logic function.

One of them is a method of defining with a formula expressing a function. For example, a multi-valued logical function MAX having x and y as variables is expressed by the following equation.

The multivalued logic function MIN is defined by the following equation.

Another way to define a multivalued logic function is to use a truth table. Fig. 1 shows an example of a truth table of a multi-valued logical function (which also has four values) that has three variables x, y and z and each variable has four values 0, 1, 2 and 3. Is shown in. Since any value can be written in the truth table, it is possible to easily define any multivalued logical function by using the truth table. While the types of functions that can be defined are limited according to the definition method using function expressions, any function can be defined using a truth table.
This is a great advantage of the definition method using the truth table. In addition, since the function defined by using the formula can also be replaced with the truth table, it can be said that the method using the truth table includes the method using the formula.

Therefore, in the following description, a multi-valued logical function is defined using a truth table in principle.

A multi-valued logical function defined by a truth table can be expressed by a mathematical expression as follows using the values in the truth table. That is, the multi-valued logical function f (x, y, z) with variables x, y and z is given by the truth table value Clmn,
It is expressed as follows.

f (x, y, z) = ΣΣΣClmn * {kl (x) · km (y) · kn (z)} ...
(3) where And for r values, x, y, z, l, m, n are 0, 1, ..., (r
-1).

In the equation (3), the symbols * and · both represent multiplication.

When considering a multi-valued logic function circuit that outputs a multi-valued signal representing the function f (x, y, z) of the equation (3), the variables x, y, z are multi-valued inputs representing those values. Given by signal. Also,
The symbol * is realized by AND logic operation, and * is realized by switching.

In order to obtain an output signal representing an arbitrary multivalued logic function by such a multivalued logic function circuit, the circuit must be programmable. Any multi-valued logic function will be obtained by programming the value Clmn of the truth table above on the circuit, ie by programming the circuit which produces the value Clmn.

To program the circuit that generates the value Clmn in the truth table, the method of programming the circuit in the process of manufacturing the circuit in the IC manufacturing process (mask programmable), and the unprogrammed circuit can be programmed by the user using a PROM writer. There is a method of programming (field programmable).

(3.2) Field programmable multivalued logic function circuit FIG. 2 shows a circuit for realizing the operation represented by the above-mentioned expression (3) to obtain an output signal representing the function f (x, y, z). The value Clmn in the truth table shows an example of a field programmable circuit. This circuit is a multi-valued logic function circuit with four values and three inputs (three variables).

The circuit shown in FIG. 2 can operate in both the current mode and the voltage mode. First, description will be given on the premise of the current mode, and then the case of switching to the voltage mode will be described.

In FIG. 2, the multivalued logic function circuit includes four signal sources 10 to 10
13, a node memory array 21 connected to these signal sources 10 to 13, and an address memory array 21 connected to this array 21.
It is composed of a switch 23 and an output line 5 connected to the output side of the addressed switch 23.

The signal sources 10 to 13 are current sources, and the detailed configuration thereof will be described later. Since this embodiment is a four-valued logic function circuit, these four values 0, 1, 2 are obtained from these signal sources 10 to 13.
Currents representing 3 and 3 are output respectively. The current source 10 for the current representing the value 0 is not absolutely necessary.

In the node memory array 21, these current sources 10 to
The lines (signal lines) connected to 13 respectively form rows, and these lines are called the 0th to 3rd lines. Lines (address lines) forming 64 columns are arranged with respect to the lines forming these rows.
From the left side of FIG.
Columns, ..., Let's call these lines in the 64th column. Each line that forms a row and each line that forms a column are connected to each other only at one location to form a node.

This memory array is field programmable, and generally, rows and columns of lines are arranged in a three-dimensional manner on a silicon chip. Normal programmable RO
Similar to M, the type that forms a node by the destruction of the pn junction or the breakdown of the insulating layer due to the application of a large current or a large voltage, and the necessary node is left by melting the fuse of the unnecessary node There are some types, but all are applicable.

In any case, this memory array 21 is programmed with the truth table values representing the desired multi-valued logic function as shown in FIG. The line in the first column is x = 0, y = 0, z
= 0, the line in the second column corresponds to x = 1, y = 0, z = 0, the line in the third column corresponds to x = 2, y = 0, z = 0, and, for example, All columns correspond one-to-one to all combinations of variables x, y, z, such that the line in the ninth column corresponds to x = 0, y = 2, z = 0. Then, the line of each column has a function f (x, x, y, z whose value is a variable
y, z), that is, the value of the truth table, Clmn (= Cxyz), is connected by a node to the line of the row derived from the current source.

The combination circuit of the current sources 10 to 13 and the memory array 21 is 64
It can be said that it is equivalent to individual current sources.

Since the memory array 21 is programmable, it is possible to program the values of any truth table so that a circuit for outputting a signal representing any multivalued logic function f (x, y, z) can be programmed. Will be realized.

The addressed switch 23 selects the current representing the function f (x, y, z) set in the memory array 21 according to the inputs x, y, z given to the input terminals 1,2,3, respectively. It is to be taken out or read out (switched on). The addressed switch 23 includes decoders (1 of 4 decoders) 31, 32 and 33 having inputs x, y, z as inputs,
It is composed of an AND array 22 connected to the output side of these decoders. When the input x (current mode or voltage mode) represents a logical value of 0, the decoder 31 outputs an H level signal to the output terminal of l = 0 and outputs the output of the other output terminals to L level. To level. Similarly, when the input x has logical values of 1, 2, and 3, H level signals are output to the output terminals of l = 1, 2, and 3, and the output of the other output terminals is set to L level. The other decoders 32, 33 work similarly.

From each decoder 31, 32, 33 extend four control lines in rows, which intersect with column lines extending from or connected to the memory array 21. At this intersection, a switching element composed of an n-channel MOS FET represented by a circle indicated by A is provided (see FIG. 3). Three of these switching elements A are connected in series to each column line, and each switching element is controlled by a control line forming a row extending from each decoder 31, 32, 33. The control lines for controlling the three switching elements in each column are different in each column. For example, the three switching elements in the first column have x = 0, y = 0, z
When = 0, all are turned on and this line is conducted. Similarly, the line in the second column is x = 1, y = 0, z = 0, and the line in the third column is x = 2, y = 0, z = 0,
The lines in the tenth column are conductive when x = 1, y = 2, and z = 0.

That is, the addressed switch 23 conducts only the one of the 64 column lines addressed by the combination of inputs x, y, z. It goes without saying that the addressed switch 23 or at least the AND array 22 is also integrated into an IC.

At the output side of the address switch 23, these 64
One column line is connected to one output line 5.
The output line 5 is provided with the output terminal 4 of the function f (x, y, z).

Therefore, the column line designated by the inputs x, y, z is made conductive by the addressed switch 23, and a current of a preprogrammed value from the corresponding node of the memory array 21 is applied to the designated column. The corresponding function f through the line, output line 5, and output terminal 4
It is output as a current representing (x, y, z).

FIG. 4 shows an example of a specific configuration of the current sources 11-13.

In FIG. 4 (A), the current I ₀ corresponding to the value 1 in the multi-valued logic is given to the input terminal 9, and this current I ₀ is nMOS.
It is input to the 6-output current mirror 14 composed of a FET. The direction of one output current of this current mirror 14 is inverted by the current mirror 15 consisting of a pMOS FET, and the output voltage I ₀ is output to the output terminal.
Appears in 11a. This output current I ₀ corresponds to the output current of the current source 11 in FIG. By connecting the two output drains of the current mirror 14 to each other, a current having a value of 2I ₀ is produced, and this current 2I ₀ is inverted by the current mirror 16 and appears at the output terminal 12a. Further, the three output drains of the current mirror 14 are connected to each other to generate a current having a value of 3I ₀ , which is inverted by the current mirror 17 and appears at the output terminal 13a. Output current of output terminals 12a, 13a 2I ₀ , 3I
₀ corresponds to the output current of the current sources 12 and 13 in FIG.

In FIG. 4 (B), three currents having the value of I ₀ are output from the three-output current mirror 14B, and these three currents are input to the current mirrors 15B, 16B, and 17B, respectively. Since the current mirror 15B is a one-output current mirror, it outputs a current having a value equal to the input current I ₀ . The current mirrors 16B and 17B are two-output current mirrors and three-output current mirrors, respectively, and their output drains are connected to each other, so that currents of 2I ₀ and 3I ₀ are obtained from these current mirrors. To be

In FIG. 2, a series circuit of a switching element 34 composed of an nMOS FET and a resistor 35 is connected in parallel to the output line 5. The resistor 35 is grounded. Switching element 34
Is ON / OFF controlled by a voltage signal applied to the mode select terminal 7.

When the circuit of FIG. 2 is operated in the current mode as described above, the voltage of H level is applied to the terminal 7 to turn off the switching element 34.

When operating in the voltage mode, an H level voltage signal is applied to the terminal 7 to turn on the switching element 34. Then, the current representing the function f (x, y, z) flows through the switching element 34 to the resistor 35, so that the voltage drop appears at the output terminal 4. However, the input impedance of the circuit at the next stage connected to the output terminal 4 is assumed to be large. In this way, the current sources 10 to 13 are left as they are (the line of the 0th row connected to the current source 10 is preferably grounded), and only the mode select signal applied to the terminal 7 is switched. This makes it possible to switch between current mode and voltage mode.

Instead of connecting the switching element 34 and the resistor 35 to the output line 5, they may be connected to each row line of the memory array 21.

Needless to say, the circuit of FIG. 2 can be changed to a voltage mode circuit by using a voltage source instead of the current sources 10 to 13.

Also provided in FIG. 2 are circuits for programming the memory array 21. This circuit includes switching elements 40 to 43 each having one terminal connected to each row line of the memory array 21, and the switching elements 40 to 43.
6 connected to the other terminal of the switching element, and a switching element
It is composed of a decoder 44 for generating a signal for controlling ON / OFF of 40 to 43. Decoder 44 has terminal 8
A line select signal is given from. This select signal is also preferably a four-valued signal.

Programming is performed as follows. By the line select signal applied to terminal 8, the memory array
Select any of the four 21 row lines. The switching element (any one of 40 to 43) corresponding to the selected row line is turned on. Further, a signal for selecting a column line is applied to the input terminals 1, 2, and 3 as inputs x, y, and z to bring a desired column line into a conductive state. After the above operation, output terminal 4
A large current or a large voltage is applied between the terminal and the terminal 6. Then, at the intersection of the selected row line and column line,
Nodules are formed or cut depending on the type.

This operation is repeated for all nodes to be formed or cut to complete programming of the memory array.

It is possible to replace the current sources 11 to 13 with the circuit of FIG. 4 to form the entire circuit of FIG. 2 into an IC, and in this case, the number of input terminals can be extremely reduced. That is, input terminals 1, 2, 3, output terminal 4, voltage or current application terminal 6 for programming, mode select terminal 7, line
The select terminal 8, the input terminal 9 for the unit current I ₀ , and the necessary operating power source V _DD and the ground terminal are all provided on a single chip, that is, 10 pins.

(3.3) Decoder Next, specific examples of the decoders 31, 32, 33 and 44 shown in FIG. 2 will be described. Since these decoders can have exactly the same configuration, the decoder 31 will be described as an example.

FIG. 5 is an example of a decoder applied when the input x is a voltage signal. The output of the four output terminals l = 0-4
It is shown from x _{0 to} x ₄ . Since the circuit of FIG. 5 is formed by sequentially connecting basic circuits, the basic circuit will be described first with reference to FIG.

In FIG. 6, two pMOS FETs Qa and Qb are connected in series. A power supply voltage, that is, an H level voltage Vj _{+ 1} is applied to the drain of one FET Qa, and the source of the other FET Qb is connected to the gate and grounded. The output terminal is provided at the connection point of the two FETs Qa and Qb (output voltage Ej). In this basic circuit, the output voltage Ej is H level only when the H level voltage is applied to the source of one FET Qa and the L level input voltage Vj is applied to the gate of the FET Qa.
Become a level.

Now, returning to FIG. 5, this circuit is the same as the basic circuit described above.
They are connected in sequence. A power supply voltage V _DD (for example, 5V) is applied to FETs Q ₁ , Q ₂ , and Q ₃ of one of the three basic circuits, and those FETs Q ₁ , Q ₂ and Q ₃ are controlled by an input voltage signal x. . FETQ ₅ and Q ₆ of the other two basic circuits are FETQ ₁ and
Connected to the drain side of Q ₂ , another basic circuit FET Q
_The power supply voltage V _DD is applied to ₄ . If the right side of the circuit of FIG. 5 is taken as the front stage side, the gates of the FETs Q ₄ , Q ₅ , and Q ₆ are controlled by the output voltage (corresponding to Ej of FIG. 5) of the basic circuit of the front stage.

Further, as shown in FIG. 7, the rising threshold values V _TH of the drain currents of the FETs Q ₁ , Q ₂ and Q ₃ are different from each other −θ ₁ , −
θ ₂ , −θ ₃ , for example, θ ₁ = 0.83V, θ ₂ = 2.50V, θ ₃ = 4.
Each is set to 17V. V _DD −θ ₃ , V _DD −θ ₂ , V _DD
-Θ ₁ is the threshold value Th for discriminating the level of the input voltage x.
It becomes ₁ , Th ₂ , Th ₃ . The threshold V _TH of the other FETs Q _{4 to} Q ₁₂ may be about 1V or more.

When the input voltage x is less than or equal to the threshold value Th ₁ , an L level voltage is applied to the gate of the FET Q ₃ of the basic circuit at the front stage, so the output voltage x ₀ of this basic circuit is H.
It becomes a level. Of the basic circuit that produces the other outputs x ₁ , x ₂ , x ₃
Since the gates of FETQ ₆ , Q ₅ and Q ₄ are at H level, their outputs x ₁ , x ₂ and x ₃ are at L level.

When the input voltage x is Th ₂ >x> Th ₁ , the voltage at each point changes as shown in (). In other words, the gate of the FETs Q ₃ because the H level, the output x ₀ becomes L level.
As a result, the gate of the FET Q ₆ becomes L level, and the output x ₁ becomes H level. The other outputs x ₂ and x ₃ remain L level.

Thus, when Th ₃ >x> Th ₂ , only output x ₂ is H
When Th ₃ <x, only the output x ₃ becomes H level.

The circuit in Fig. 5 is composed of pMOS FETs,
It goes without saying that the decoder can be configured in the same way even if MOS FETs are used. Next, an example of the decoder when the input signal x is a current will be described. This can be constructed using multiple literal circuits operating in current mode. The current mode literal circuit is described in detail in the applicant's earlier application, Japanese Patent Application No. 60-16897, which will be briefly described here.

An example of a 1-of-4 decoder utilizing four literal circuits is shown in FIG. Input current x is a multi-output current mirror
To the literal circuit 50, which produces six currents of the same value as the input current x, one of which produces the output of x ₀ , and the other two each produce x ₁ , The remaining one is sent to the literal circuits 51 and 52 that generate the x ₂ output, and the other one is sent to the literal circuit 53 that generates the x ₃ output.

The operation of the literal circuit 51 that generates the output signal ^ab _x ▼ (a = 0.5, b = 1.5) will be described.
PMOS is connected between the current source 59 representing the value of -1) and the output terminal.
FETQ _S1 and nMOS FETQ _S2 are connected in series. Further, current sources 55 and 56 for currents representing the values of a and b are provided, and the output sides of the multi-output current mirror 54 are connected to the output sides of these current sources 55 and 56 at nodes 57 and 58, respectively. FETs Q _S1 and Q _S2 are controlled by the voltages at the nodes 57 and 58, respectively.

When x> a, the potential of node 57 becomes L level, and FETQ
_S1 turns on. When x <b, the potential at the node 58 becomes H level and the FET Q _S2 is turned on. Therefore, as shown in FIG. 9 (B), only during a <x <b,
A current of (r-1) is obtained at the output terminal.

Similarly, in the literal circuit 52, since a = 1.5 and b = 2.5 are set, the output current is obtained from the output terminal when 1.5 <x <2.5.

In the literal circuit 50, those corresponding to the current source 55 and the FET Q _S1 are omitted. Also, b is set to 0.5. Therefore, the output current is obtained when x <0.5.

In the literal circuit 53, the parts corresponding to the current source 56 and the node Q _S2 are omitted, and a = 2.5 is set, so that the output current is obtained at 2.5 <x.

These output currents are shown in FIG. Therefore, from the circuit shown in FIG. 8, the output current can be obtained from any one of the four output terminals according to the value of the input current x. This output current is made to flow to the ground side through the resistance as shown by the chain line, and the voltage drop in this resistance causes
The switch A of the AND array 22 may be controlled.

When the circuit of FIG. 8 is used as a decoder, the value of (r-1) of the current source 59 may be any value.

(3.4) Another example of the addressed switch In the multivalued logic function circuit shown in FIG.
The switch 23 can be replaced by other circuits, for example some bilateral T-gates as shown in FIG.

For simplification, the circuit shown in FIG. 10 shows the case of two inputs x and y. Further, voltage sources 11A to 13A are used instead of the current sources 11 to 13 in FIG. Of course, a current source can be provided, and in that case, a current, voltage changeover switch and resistance can be provided.

The bilateral T gate is a gate for selecting one of a plurality of input signals according to the value of a select signal and outputting one of them as an output signal. In FIG. 10, the addressed switch has four bilateral T gates 61 to 64 each having an input x as a select signal and each having four input terminals, and inputs and outputs of these bilateral T gates. It is composed of one bilateral T gate 65 which uses y as a select signal.
Four lines from the first column to the sixteenth column are input to the bilateral T gates 61 to 64, respectively. In addition, bilateral T
The output of gate 65 represents the output signal f (x, y).

(3.5) Mask programmable multi-valued logic function circuit Field programmable and mask programmable are, in principle, the nodes of the memory array as shown by reference numeral 21 in FIG. There is no difference in the circuit, because there is only a difference in which process is used for programming (the IC structure also differs). However, in the case of mask programmable, since the circuit pattern is determined at the design stage, there is no flexibility, but there is an advantage that the circuit pattern can be simplified.

FIG. 2 is an example of a field programmable circuit, and FIG. 11 is an example of a circuit obtained as a result of simplifying the circuit of FIG. 2 by using a mask programmable circuit.
The simplification of the circuit pattern will be described in comparison with the figure. 11, the same parts as those shown in FIG. 2 are designated by the same reference numerals. Further, the decoder 44 and the switching elements 40 to 43 controlled by the output thereof are unnecessary.

As can be seen from the truth table of FIG. 1, at z = 0 and y = 2, f (x, y, z) = 1 regardless of the value of x.
This portion is realized as lines in columns 9 to 12 in the circuit of FIG. Since the nodes of the four columns are all in the first row on the memory array 21, it is possible to omit the lines for three columns and to represent the four columns by one line. . This new column line is shown in FIG. 11 as the new ninth column line. Since the output f (x, y, z) takes the same value regardless of the value of the input x, the switching element controlled by the input x is not provided on the new ninth column line in the AND array 22. On this new 9th column line, inputs y (= 2) and z (= 0)
Only the switching elements A1 and A2 controlled by are provided.

Similarly, in the truth table of FIG. 1, when z = 2, f (x, y, z) = 2 regardless of the values of x and y. Therefore, the corresponding lines in columns 33 to 48 in FIG. 2 can be represented by the new line in column 30 as shown in FIG. Z = 2 regardless of input x, y
Since f (x, y, z) takes a value of 2 when,
Only the switching element A3 controlled by the input z is provided on the column line.

Further, as shown in FIG.
It is also possible to omit the row lines, ie the column lines connected to the extension lines of the signal source 10 of zero.

In this way, the multiple logic function circuit of FIG. 2 becomes extremely simplified in the end as shown in FIG. 12 if the above-mentioned idea of omission is adopted.

In the mask programmable circuit, the memory array 21
It should be noted that the AND array 22 must be programmed as well.

(3.6) Multi-function circuit A multi-function circuit is a circuit that generates multiple function outputs for a certain combination of inputs. FIG. 13 shows an example of a truth table of a 2-input 4-value multi-function, and FIG. 14 shows an example of a multi-function circuit for executing the function operation of the truth table.

In FIG. 13 (A), four function values are shown in a matrix for the combination of the input variables x and y. These function values show the values of the functions f ₁ , f ₂ , f ₃ and f ₄ shown in FIG. 13 (B).

In FIG. 14, four row lines (output lines) connected to output terminals 35 to 38 for outputting _four functions f _{1 to} f ₄
Are provided and these row lines intersect the column lines from the memory array 21. The output lines of the first row corresponding to the function f ₁ are the lines of the first to fourth columns, and the output lines of the second row corresponding to f ₂ are the lines of the fifth to 14th columns, f
The output line of the third row corresponding to ₃ is connected to the lines of columns 15 to 28, and the output line of the fourth row corresponding to f ₄ is connected to the lines of columns 29 to 42, respectively. It forms a knot. These four lines and nodes are sum arrays
Make up 24.

On the four column lines connected in the sum array 24 to the output row lines corresponding to the function f ₁ , the switching elements controlled by the outputs of the decoders 31 and 32 in the AND array 22 are provided in the memory array 21. Voltage signal source 11A-13A
Nodes with three extending line lines are each preprogrammed in the optional manner described above.

The same applies to the column lines that generate the other functions f _{2 to} f ₄ .

According to the circuit of FIG. 14, when a certain combination of inputs x and y is given, four different functions f ₁ showing the results of calculating the inputs x and y according to the truth table of FIG. 13 (A). ~ F ₄
It will be easy to understand that a signal representative of is obtained. In such a multi-function circuit, the memory array 21, the AND array 22
In addition to the above programming, the thumb array 24 also needs to be pre-programmed.

In the circuit of FIG. 14, the number of column lines can be further omitted. For example, the second line and the 40th line
Both lines in the column are for generating output signals of the value 3 when x = 2 and y = 1, and these signals appear at the output terminals 35 and 38, respectively. Therefore, change the line in the second column and the line in the 40th row connected to the output terminal 38 to B
Even if the line in the 40th column is removed, the same output signal as that described above can be obtained at the output terminals 35 and 38 by connecting with the node shown by. In this way, among the different functions, it becomes possible to leave only one line and omit the other lines for the column lines that generate the function output of the same value when the combination of inputs is the same.

(3.7) Multi-valued ALU Fig. 15 shows a field programmable 4-value 2-input ALU constructed by using the above memory array and addressed switches (decoder and AND array). The same components as those described above are designated by the same reference numerals.

There are two input signals, x and y. This ALU can perform four different operations. This operation or the operation result is represented by f ₁ , f ₂ , f ₃ and f ₄ . Since performing an operation is the same as obtaining the value of a function that represents the operation, the above-mentioned f _{1 to} f ₄ may be called functions in some cases in the following description.

In FIG. 15, the memory array 21 is programmed with a truth table of _four different functions f _{1 to} f ₄ . An AND array portion is provided for each of the inputs x and y for the memory array portion of each function in the same manner as shown in FIG. 2, and the set of these AND array portions is an AND array.
It is 22. 1 for all column lines in AND array 22
It is connected to the output line 5 of the book.

A select terminal 37 is provided to select the above-mentioned four operations or functions, and a four-value select signal is input to this terminal 37. The select terminal 37 is connected to the input side of the 1-of-4 decoder 36, and the decoder 36 outputs four control lines. Any one of the control lines designated by the inputted four-value select signal becomes H level.

Between the AND array 22 and the memory array 21, one switching element is provided for each column line, and these switching elements are controlled by control lines which specify the corresponding functions of the decoder 36. These switching elements and the like form the select array 25.
The select array 25 may be provided between the AND array 22 and the output line 5.

As described above, in the ALU of FIG. 15, when the inputs x and y and the select signal S are given, the operation selected by the select signal S is performed on the inputs x and y, and the result is output. Output terminal 4 through line 5
Can be obtained from

This ALU also has a current / current, as shown in FIG.
The voltage mode may be switched, and further, the decoder 44 for programming and the switching element 40 may be used.
~ 43 and the like may be provided. Further, the mask program ALU can be used. According to the present invention, an AL for more than 3 inputs and multi-values other than 4 values
Easy to deploy on U.

The multi-valued ALU of FIG. 15 can be integrated and produced on one chip, in which case this chip would be illustrated as shown in FIG. The minimum required pins are input x, y
Input pin, select signal S input pin, calculation result f output pin, current input pin for inputting a current representing four logic values 0 to 3, operating voltage application pin and ground terminal pin. It has 10 pins. Further, if necessary, two pins, that is, a pin for the program terminal 6 and a pin for the current / voltage mode switching signal input terminal 7 (both see the second) will be added.

FIG. 17 shows an example in which the multi-valued ALU addressed switch and select array shown in FIG. 15 are realized by a bilateral T gate. Four of the column lines of the memory array 21 are each connected to the input side of 16 bilateral T-gates 71 controlled by the input x. The output lines of these bilateral T-gates 71 are 4
Each of them is connected to the input side of four bilateral T gates 72 controlled by the input y, and the output lines of these bilateral T gates are connected to the select signal S.
It is connected to the input side of a bilateral T gate 73 controlled by. The output line of the bilateral T gate 73 is connected to the output terminal 4. In this way, it is possible to construct a multi-valued ALU even by using a bilateral T gate.

FIG. 18 shows an example in which a four-value two-input ALU of 16 functions is configured by using five 4-chip 1-chip ALUs shown in FIG.

Four 4-function 1-chip ALU75s are connected in parallel.
These ALU75 are pre-programmed with a total of 16 different functions. Further, inputs x and y are applied to the input terminals 1 and 2 of these ALU75, and currents representing logical values of values 0 to 3 are applied to the terminals of the current source.

The 16 functions can be selected by the 4-value 2-digit signal S ₁ S ₀ . Lower digit S ₀ of the select signal S ₁ S ₀ each ALU75
To the select terminal (indicated by 37a in FIG. 18). Therefore, four functions F _{1 to} F ₄ selected by the signal S ₀ are output from the four ALUs 75.

Any _{one of} these functions F _{1 to} F ₄ is selected in another ALU 76 to which the high-order signal S ₁ is applied. The ALU76 is a kind of bilateral T gate, and of course, a bilateral T gate can be used instead of the ALU76.

The specific wiring of the ALU76, which acts as a bilateral T-gate that selects one of the four inputs, is shown in FIG. In the row lines of the memory array 21, the currents representing the functions F _{1 to} F ₄ output from the ALU 75 described above are input instead of the currents representing the logical values. A control line connected to the output 0 terminal of the decoder 32 and also a decoder
Only the lines from the first column to the fourth column controlled by the control line connected to the output 0 terminal of 36 are arranged in the memory array.
At 21, it is programmed to have a node with each of the four row lines. In addition, terminals where the input sides of the decoders 32 and 36 are connected to each other and a signal of logical value 0 is given
It is connected to 37b. Therefore, 0 of the decoders 32 and 36
An H level control signal appears at the output terminal of the
The corresponding switching element in the line of the fourth column is turned on. The select signal S ₁ of the upper digit is given to the decoder 31, and _one of the lines of the first to fourth columns is selected by this select signal S ₁ , and the memory array
_{One of the} functions F _{1 to} F ₄ input to 21 is sent to the output terminal 4.

As described above, an ALU capable of calculating 16 different functions is realized. This will cover almost all functions that are already defined.

Above, some specific multi-valued function circuits are described.

(3.8) Multi-valued MAX / MIN function circuit The multi-valued MAX function is expressed by the above equation (1), and the multi-valued MIN function is expressed by the equation (2). The operation of multi-valued two-variable MAX is to select the larger value of variables x and y and take the larger value as the result.
The operation of N is to select the smaller one of the variables x and y and use the smaller value as the result.

Figure 20 shows a circuit that performs both MAX and MIN operations. This circuit, indicated by the reference numeral 85,
Two input terminals and a flag input for signals representing y and y
It has an input terminal for Fin, an output terminal for MAX operation result A, an output terminal for MIN operation result I, and an output terminal for flag output Fout. Flag output Fo
ut represents the magnitude relation between inputs x and y, and Fout = 0 when x = y, Fout = 1 when x <y, and Fout = 2 when x> y. The input terminal of the flag input Fin is for guiding the flag output Fout of the circuit at the preceding stage when such MAX / MIN function circuits are connected in multiple stages.

The MAX / MIN circuit shown in FIG. 20 is the multi-function circuit of FIG.
It can be realized by changing to an input circuit. Also,
It can also be realized as a part of the multi-valued ALU shown in FIG. Multivalued A
When it is made a part of LU, it will be possible to select either MAX output A or MIN output I by the select signal S.

As shown in FIG. 21, when a plurality of MAX / MIN circuits 80 to 83 are configured in multiple stages by connecting the flag output of the preceding stage with the flag input of the latter stage, multi digit variable (x) of multiple digits (digits) MAX, MIN operations of ( ₃ x ₂ x ₁ x ₀ ) and (y ₃ y ₂ y ₁ y ₀ ) can be performed. The first flag input Fin ₀ is 0. The final flag output Fout ₃ indicates which of the above 4-digit multivalued variables is large as a whole.

Regarding the case where the truth table of the MAX / MIN multi-valued function has 4 values 22.
Given in the figure.

When Fin = 0, the output A or I indicates the larger one of the inputs x and y, whichever is smaller.

When Fin = 1 (that is, y> x), the output A directly represents one input y and the output I directly represents the other input x. In addition, Fout = 1.

When Fin = 2 (x> y), the output A is equal to x,
The output I is equal to y. Also, Fout = 2.

Figure 23 is a four-value MA constructed using the truth table of Figure 22.
It is a connection diagram of an X / MIN function circuit. In this figure, both nodes and switching elements are shown as black circles.
The outline can be easily understood from the comparison with the multi-function circuit shown in FIG. In addition, x and y have 3 inputs by adding Fin, 3 outputs are A, I, and Fout, and a current source is used as a signal source. It is slightly different from that shown in FIG. 14 in that it is opposite to that shown in FIG.

FIG. 24 is a simplified version of the circuit shown in FIG.
This is a mask programmable circuit as described above.

(3.9) Multi-value full adder circuit Figure 25 shows the block of full adder circuit FA and its input / output relationship.
And the arithmetic expression of full addition are shown. The inputs are x and y as variables and the renormalization Cin from the lower digits. The output is the sum S and carry Cout to the upper digit.

FIG. 26 shows a circuit for adding a 4-digit variable (x ₃ x ₂ x ₁ x ₀ ) and (y ₃ y ₂ y ₁ y ₀ ) and an arithmetic expression for this addition. Four circuits FA ₀ , FA ₁ , FA ₂ , FA ₃ equivalent to the full adder circuit block shown in FIG. 25 connect the Cout of the lower digit block to the Cin of the upper digit block, It is connected in series.

FIG. 27 shows a truth table of the 4-value full adder circuit.

Further, FIG. 28 is a specific connection diagram of the full adder circuit programmed based on such a truth table. In the case of four values, the renormalization Cin takes only two values 0 and 1. Therefore, in the AND array of FIG. 28, two of the four column lines connected to the output side of the Cin decoder are meaningless. Also, since there are only two types of output, S and Cout, the remaining one output line of the three output lines is actually unnecessary.

Figure 29 is a simplified version of the wiring diagram of Figure 28.

(3.10) Multivalued full subtraction circuit Fig. 30 shows the input / output relation of the first type full subtraction circuit FS and the arithmetic expression of the full subtraction. Inputs are variables x and y and lending Bin to the lower digits, and outputs are difference D and borrowing Bout to the upper digits. Bin and Bout are 0 or 1
Takes the value of. This circuit is effective only when x> y.
The truth table of the total subtraction in the case of r = 4, that is, four values is shown in FIG.

FIG. 31 shows four full subtraction circuits FS ₀ , FS ₁ , FS ₂ , FS ₃ having the same function as the full subtraction circuit for FIG. Connected in series, the four-digit variable (x ₃ x ₂ x ₁ x ₀ ) to (y ₃ y ₂ y ₁
7 shows a circuit configured to subtract y ₀ ). However, the condition is (x ₃ x ₂ x ₁ x ₀ )> (y ₃ y ₂ y ₁ y ₀ ).

Fig. 33 shows a concrete connection diagram of the full subtraction circuit for four values.
The simplified wiring diagram is shown in FIG.

FIG. 35 shows a special subtraction circuit. Flag input Fin,
Without considering the lending Bin, the larger one of the inputs x and y is selected by the MAX circuit, and the smaller one is selected by the MIN circuit.
The selected values are input to the full subtraction circuit FS and D = x−
A difference output of y (x ≧ y) or D = y−x (y ≧ x) is obtained. This is an absolute difference. Considering Fin and Bin, it becomes a very special circuit.

FIG. 36 shows the circuit of FIG. 35 connected in cascade for four digits.

FIG. 37 is applicable to the case where either input x or y is large, and can output the sign (+ or −) representing the comparison result of the second type. The input / output relationship of the circuit is shown. The code is the flag F (Fi
This flag F has a value of 2 when x> y, 0 when x = y, and 1 when x <y. The flag input Fin is input from the lower digit, and the flag output Fout is output to the upper digit. Other inputs and outputs are the same as those shown in FIG.

A truth table of the second type full subtraction circuit in the case of four values is shown in FIG.

FIG. 38 shows a subtraction circuit which performs 4-digit subtraction (x ₃ x ₂ x ₁ x ₀ )-(y ₃ y ₂ y ₁ y ₀ ) using the full subtraction circuit shown in FIG. There is. The MAX / MIN circuit for 4 digits shown in Fig. 21 determines whether (x ₃ x ₂ x ₁ x ₀ ) or (y ₃ y ₂ y ₁ y ₀ ) is larger, smaller, or equal. ，
The result is represented by the flag output Fout ₃ of the MAX / MIN ₃ circuit. Four full subtraction circuits FS _{0 to} FS ₃
And Fin of the upper digit are connected, and Bout of the lower digit and B of the upper digit are connected.
Connected in cascade by connecting with in. As the Fin ₀ of the least significant digit full subtraction circuit FS ₀ , the above MAX / M
IN ₃ Circuit Fout ₃ is input. Top digit circuit FS ₃
Fout ₃ represents the sign S of the final subtraction result.

(3.11) Multivalued full multiplication circuit The input / output signals of the multivalued full multiplication circuit Mul are shown in FIG. The input is two variables x and y and the carry-in Cin from the lower digit, and the output is the product P and the carry Cout to the upper digit.

FIG. 42 shows the truth table of the full multiplication circuit in the case of four values.

In addition, the specific connections programmed using this truth table are shown in FIG. 43, and their simplified forms are shown in FIG. 44.

FIG. 41 shows an example of a 4-digit.times.1-digit full multiplying circuit constructed by using the above four full multiplying circuits. This circuit is configured by connecting all the one-digit multiplication circuits Mul _{0 to} Mul ₃ in cascade so that the lower digit Cout is connected to the upper digit Cin. (X ₃ x ₂ x
₁ x ₀ ) × y ₀ multiplication is performed, so each circuit Mul _{0 to} Mul ₃
The inputs are x ₀ and y ₀ , x ₁ and y ₀ , x ₂ and y ₀ , x ₃ and y ₀ . The multiplication result is represented by (Cout ₃ P ₃ P ₂ P ₁ P ₀ ) using the product P _{0 to} P ₃ of each circuit Mul _{0 to} Mul ₃ and the circuit Mul ₃ carry Cout ₃ of each.
Cout ₃ may be replaced with P ₄ .

Multiplication of a variable of a plurality of digits and a variable of a plurality of digits is achieved by repeating multiplication of a variable of a plurality of digits and one digit and sequentially adding the multiplication results with digits aligned. However, it is also possible to multiply multiple digits and multiple digits at once. An example of a circuit that performs such multiplication is a 4-digit variable (x ₃ x ₂ x ₁
It is shown in FIG. 45 as a multiplication circuit of x ₀ ) and a 2-digit variable (y ₁ y ₀ ).

The circuit shown in FIG. 45 is a circuit for performing (x ₃ x ₂ x ₁ x ₀ ) x y ₀ Mul ₀₀
~ Mul ₃₀ (outputs P _{00 to} P ₄₀ ) and a circuit that performs (x ₃ x ₂ x ₁ x ₀ ) x y ₁ Mul _{01 to} Mul ₃₁ (outputs P _{01 to} P ₄₁ ) and the outputs of these circuits. Circuits that match digits Digit adder FA ₀ to FA ₄
It consists of and. The final multiplication result is (P ₅ P ₄ P ₃ P ₂
Given by P ₁ P ₀ ).

Two multiplication circuits Mul ₁₀ and Mul surrounded by broken lines shown in FIG.
₀₁ and adder FA _0, as shown in FIG.
It is also possible to collect them as output circuits and program them according to the corresponding truth table.

(3.12) Multivalued total division circuit Figure 47 shows the input / output relation of the multivalued division circuit FD. The inputs are the variables x and y and the borrowed Bin from the upper digit,
The output is the quotient Q and the remainder R.

The truth table of the 4-value division circuit is shown in FIG.
A wiring example of the total division circuit programmed by using this truth table is shown in FIG. 50, and a simplified wiring example thereof is shown in FIG. 51.

FIG. 48 shows that a 4-digit variable (x ₃ x ₂ x ₁ x ₀ ) is converted to a 1-digit variable y by connecting four full-divider circuits FD _{0 to} FD ₃ having the same configuration as the above-mentioned full-divider circuit in cascade. _A circuit divided by ₀ is shown. The remainder R in the upper digit is entered as the borrow Bin in the lower digit. One input of each circuit is x ₀ , x ₁ , x ₂ , x ₃ , but the other input is commonly y ₀ . The calculation result is (Q ₃ Q ₂ Q ₁
Q ₀ ) The remainder is R ₀ .

When dividing a variable with a plurality of digits by a variable with a plurality of digits, it is preferable to previously create a circuit capable of performing the division at once in accordance with a truth table corresponding to the operation. FIG. 52 shows the concept of a circuit in which a 4-digit variable (x ₃ x ₂ x ₁ x ₀ ) is divided by a 2-digit variable (y ₁ y ₀ ). This circuit consists of four full subtraction circuits FD _{10 to} FD ₁₃ connected in cascade, each full subtraction circuit having 5 inputs and 3 inputs.
It is an output circuit. That is, the input is xi, a 2-digit variable y ₁ and y ₀ , and a 2-digit borrow Bin ₁ i and Bi.
n ₀ i, the output is the quotient Q i and the 2-digit remainder R ₁ i and R ₀ i (i =
0-3). The truth table of such a circuit is a little complicated, but it is easy to create.

(3.13) CMOS multi-level ALU In the above embodiment, the AND array 22 and the select array 25
The nMOS FET is mainly used as the switching element in the above, but it can be replaced by the pMOS FET. However, using a CMOS FET can speed up and prevent the occurrence of errors. Below, CMOS
A circuit using is explained.

Figure 53 shows the switching operation using nMOS.
(A) is a circuit diagram and (B) is a waveform diagram.

In FIG. 53 (A), the voltage source E and the output terminal (output voltage
A switching element consisting of an nMOS FETQ _N is connected to Vo), and the output terminal is grounded via a large resistance _RL . FETQ _N is on / off controlled by a control signal Vc.

When the control voltage Vc becomes H level (for example, 5V), the FET Q _N is turned on and the H level output voltage Vo appears. Control voltage
When Vc becomes L level (OV), FETQ _N turns off and the output voltage Vo also becomes L level (OV).

In this switching operation, as shown in FIG. 53 (B), the output voltage Vo rises very quickly when the FET Q _N is turned on. However, the power supply voltage E is
The voltage is divided by the resistance of TQ _N and the resistance R _L, and the output voltage Vo becomes lower than the voltage E. This causes an error, and even if there are no problems in a circuit with 3 or 4 values, it becomes an important problem with, for example, about 10 values. Further, when the FETQ _N is turned off, the charge stored in the substrate-source capacitance C _SB of the FETQ _N is discharged through the resistor R _L , which causes a problem of extremely slow response.

FIG. 54 shows a solution of the above problems using a CMOS FET. (A) is a circuit diagram and (B) is a waveform diagram. First
In Fig. 54 (A), pMOS is connected between the voltage source E and the output terminal.
FETQp has nMOS FETQ _N connected between the output terminal and ground. Both of these FETs Qp and Q _N are controlled by the control voltage Vc. The control voltage Vc is shown in Fig. 54 (B).
It has both polarities (for example, + 5V to -5V) as shown in FIG.

When the control voltage Vc is H level (+ 5V), FETQp is off,
Since FETQ _N is turned on, the output voltage Vo is at L level (O
V). Conversely, when the control voltage Vc becomes L level (-5V), the FET Qp is turned on and the FET Q _N is turned off, so that the power supply voltage E appears at the output terminal as it is, and the output voltage Vo becomes H level (E).

In this way, the switching circuit shown in FIG. 54 (A) has a fast response speed in both rising and falling (for example, about several n seconds), and since there is no error, the circuit configuration for a high radix such as ten values is obtained. Is also possible, and one of FET Qp and Q _N is always on, so the output resistance is small.

In Fig. 54 (A), although the voltage relationship changes,
It goes without saying that Q _N may be exchanged.

FIG. 55 shows a multi-valued logic function circuit corresponding to FIG. 2 and the like constructed by using the switching circuit by the CMOS FET shown in FIG. 54 (A), only a part of which is shown. ing.

Instead of the AND array 22 described above, pMOS AND arrays 22A and nM
An OS AND array 22B is provided. In each column line, three pMOS FETs (eg Qpx, Qpy, Qpz) are connected in series in the pMOS AND array 22A, and these FETs are derived from the programmed connection of the outputs of the decoders 31, 32, 33. Controlled by the output being burned. Similarly, nMOS
Also in the AND array 22B, three nMOS FETs (eg, Q _N x, Q _N y, Q _N z) are connected in series in each column line, and these are connected to the corresponding pMOS FET of the pMOS AND array 22A.
Respectively controlled by the decoder output applied to the. One end of each column line of the nMOS AND array 22B is grounded, and the other end is connected to the output line 5. pMOS
One end of each column line of the AND array 22A has an output line 5
, And the other end is programmatically connected to any row line of memory array 21. The decoders 31 to 33 output the bipolar control signals described above. For example, when the input x is x = 0, the output terminal of 0 of the decoder 31 is -5V, all other output terminals (1,
2,3) is + 5V. In addition, voltage sources 11A to 13 are used as signal sources.
A (for example, 1V, 2V, 3V) is adopted.

The circuit part shown in FIG. 55 is such that when x = 0, y = 2, z = 3,
It is configured to generate a voltage signal (2V) representing a function value of logical 2 at the output terminal.

A multi-valued ALU as shown in FIG. 15 can be easily constructed by using a CMOS switching circuit. For example, the 4-input ALU with two inputs x and y has the decoder 31 (36) for the select signal S in FIG. 55 and the decoders 32 (31), 3
Let 3 (32) be for inputs x, y. Also pMOS AND
Array 22A with pMOS AND array (22a) and pMOS select
It may be functionally divided into an array (25a), and similarly, an nMOS AND array (22b) and an nMOS select array (25b) may be configured by the nMOS AND array 22B. In FIG. 55, for the sake of clear comparison with FIG. 15, the same or related symbols as those shown in FIG. 15 have the same or related symbols (symbols with subscripts a and b). It is shown in (). In the circuit part shown in FIG. 55, the function (operation) f ₁
, F ₁ (x, y) = f ₁ (2,3) = 2 (V). The signal representing the operation result appears at the output terminal 4.

[Brief description of drawings]

FIG. 1 is a diagram showing an example of a truth table of a four-value three-input multivalued logic function. FIG. 2 is a circuit diagram showing a multivalued logic function circuit that outputs a multivalued function represented by the truth table shown in FIG. 1, and FIG. 3 explains the symbols in FIG. FIGS. 4A and 4B are circuit diagrams showing examples of specific circuit configurations of the current signal source shown in FIG. FIG. 6 is a circuit diagram showing a specific example of the decoder shown in FIGS. 5 and 2 which operates in a voltage mode, and FIG.
It shows a basic circuit for explaining the circuit of the figure,
FIG. 7 shows the function of the rising threshold of the drain current of the FET shown in FIG. 5 and the threshold level of the circuit. FIG. 8 is a circuit diagram showing a specific example of the decoder operating in the current mode, and FIGS. 9A to 9D are graphs showing output signals of the circuit of FIG. FIG. 10 is a circuit diagram showing another example of the addressed switch. 11 and 12 are circuit diagrams showing a multivalued logic function circuit obtained by simplifying the circuit of FIG. 2 by making the circuit of FIG. 2 mask-programmable. FIG. 13 (A) is a diagram showing an example of a multi-function truth table, and FIG. 13 (B) is a diagram showing a correspondence relationship between four functions and values in the truth table. FIG. 14 is a circuit diagram showing an example of a multi-function circuit that realizes the truth table of FIG. FIG. 15 shows an example of a multi-valued ALU, which is a 4-level 2-input A
It is a circuit diagram of LU. FIG. 16 is a block diagram showing a state in which the multilevel ALU shown in FIG. 15 is integrated into one chip. FIG. 17 is a circuit diagram showing an example of a multi-valued ALU composed of a memory array and a bilateral T gate. Figure 18 is a block diagram of an ALU that can perform 16 functions using five ALU chips.
The figure is a circuit diagram showing a specific connection of an ALU used as a bilateral T gate in the circuit of FIG. Figure 20 shows the input / output relationship of the multi-valued MAX / MIN function circuit block. FIG. 21 is a block diagram of a multi-digit MAX / MIN circuit configured by connecting MAX / MIN circuits in multiple stages. FIG. 22 is a diagram showing a truth table of the four-valued MAX / MIN function. FIG. 23 is a connection diagram of a 4-valued MAX / MIN function circuit, and FIG. 24 is a knot diagram when the circuit of FIG. 23 is simplified. FIG. 25 shows the input / output relationship of the multilevel full adder circuit block. FIG. 26 is a block diagram of a full adder circuit for a plurality of digits configured by connecting the full adder circuits in multiple stages. FIG. 27 is a diagram showing a truth table for 4-value full addition. Fig. 28 is a wiring diagram of the 4-value full adder circuit, and Fig. 29 is a wiring diagram.
28 is a connection diagram that simplifies the circuit of FIG. 28. FIG. FIG. 30 shows the input / output relationship of the first type multi-value full subtraction circuit block. FIG. 31 is a block diagram of an all-subtraction circuit for a plurality of digits configured by connecting the first-type all-subtraction circuits in multiple stages. FIG. 32 is a diagram showing a truth table of four-value full subtraction in the first-type full subtraction circuit. FIG. 33 is a connection diagram of the first-type four-value full subtraction circuit, and FIG. 34 is a connection diagram simplified from the circuit of FIG. FIG. 35 shows a special subtraction circuit, and FIG. 36 is a block diagram of a circuit in which the circuit of FIG. 35 is connected in a cascade of 4 digits. FIG. 37 shows the input / output relationship of the second type total subtraction circuit block. FIG. 38 is a block diagram of an all-subtraction circuit for a plurality of digits configured by connecting the second-type all-subtraction circuits in multiple stages. FIG. 39 is a diagram showing a truth table of four-value full subtraction in the second type full subtraction circuit. FIG. 40 shows the input / output relationship of the multivalued all multiplication circuit block. FIG. 41 is a block diagram showing an example in which all the multiplying circuits are connected in multiple stages to form a multiplying circuit for variables of 4 digits and 1 digit. FIG. 42 is a diagram showing a truth table for four-value full multiplication. FIG. 43 is a connection diagram of the 4-value full multiplication circuit, and FIG. 44 is a simplified connection diagram thereof. FIG. 45 is a block diagram showing an example of a circuit for multiplying a 4-digit variable and a 2-digit variable all at once.
Figure 46 shows a block that summarizes some of the components of Figure 45. FIG. 47 shows the input / output relationship of the multivalued total division circuit block. FIG. 48 is a block diagram showing an example in which all division circuits are connected in multiple stages to configure a division circuit for dividing a 4-digit variable by a 1-digit variable. FIG. 49 is a diagram showing a truth table for 4-value total division. FIG. 50 is a wiring diagram of the 4-value full division circuit, and FIG. 51 is a simplified wiring diagram thereof. FIG. 52 is a block diagram showing the concept of a circuit for dividing a 4-digit variable by a 2-digit variable. FIG. 53 (A) shows an nMOS FET switching circuit, and FIG. 53 (B) shows its waveform. FIG. 54 (A) shows a CMOS FET switching circuit, and FIG. 54 (B) shows its waveform. FIG. 55 is a circuit diagram showing an example of a CMOS multilevel logic function circuit and a CMOS multilevel ALU. 5 ... Output line, 10,11,12,13 ... Signal source, 21 ... Memory array, 22,22a, 22b ... AND array, 23 ... Addressed switch, 25,25a, 25b ... Select array, 31,32,36 ... Decoder, 71,72,73 ... Bilateral T gate.

Claims (5)

[Claims] 1. A plurality of multi-valued signal sources which generate signals respectively representing a plurality of logic values of an applied multi-valued logic, a plurality of signal lines respectively connected to these signal sources, and a plurality of signals to be operated. An address line group consisting of a plurality of address lines connected at a node to any one of the signal lines is provided by being provided for each different function and programmed according to the truth table of each function. A memory array including; first selecting means for selecting one of the above address line groups by a select signal for selecting a function to be operated; at least one of the address line groups selected by a multilevel input signal Second selecting means for selecting one of the address lines, and the address line selected by the first and second selecting means. A multi-valued ALU having an output circuit that outputs a signal representing a logical value obtained from the above. 2. A multi-valued AL according to claim 1, wherein the memory array is field programmable.
U. 3. A multi-valued ALU according to claim 1, wherein the memory array, the first selecting means and the second selecting means are mask programmable. 4. The multilevel ALU according to claim 1, wherein the multilevel signal source is a current source. 5. The multilevel ALU according to claim 1, wherein the multilevel signal source is a voltage source.