JPH07240086A - Picture signal editing device using multi-head player - Google Patents

Abstract

PURPOSE:To monitor imaginably an edited result and to facilitate editing work by transferring each recording and reproducing head to each recording position of plural cut picture signal selected out of picture signals recorded in a recording medium. CONSTITUTION:A VTR 1 reproduces recorded information of a video tape set in the VTR 1 in accordance with play operation, and supplies a reproduced picture signal obtained at this time to a VDR(video disk recorder) 5 having multi-head constitution. The VDR 5 records a reproduced picture signal supplied from the VTR 1 to a recording disk being a recording medium, while reproduces a reproduced signal recorded in this recording disk and supplies it to the VTR 1 and an editing controller 6 respectively. The editing controller 6 synthesizes a reproduced picture signal supplied from the VTR 5 and a picture frame signal for editing work, generates a picture signal for editing work, and supplies it to a display 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image signal editing apparatus using a multi-head player for editing a video tape recorded by a VTR (video tape recorder) or the like.

[0002]

2. Description of the Related Art With the spread of home video cameras,
Editing work has been performed in which a video tape, which has been recorded by a video camera and has been recorded, is edited as desired to create a video library. For example, in such editing work, only a plurality of attractive cuts are selected from the video tapes that have been recorded, and these are connected in a desired order and recorded on a newly prepared video tape.

FIG. 1 is a diagram showing an example of an image signal editing system for performing such editing work. In the figure,
A video tape which has already been recorded by a video camera or the like is set in the VTR 1, and an empty video tape in which an image signal is not yet recorded is set in the VTR 2. The VTR 1 supplies the reproduced image signal obtained by reproducing the recorded information of the recorded video tape to the VTR 2 and the display 3, respectively. The VTR 2 records the reproduced image signal on the set video tape. The display 3 displays an image based on the reproduced image signal. The editing controller 4 sends VT command signals for reproduction, fast forward, rewind, recording, and operation stop.
By supplying R1 and 2, the operation control of each of the VTRs 1 and 2 is performed.

Next, the editing work operation executed in such a system configuration will be described. At this time, it is assumed that a video tape in which four different scenes are recorded as shown in FIG. 2A is set in the VTR 1. First, the edit controller 4 executes the reproduction operation of the VTR 1 to sequentially display the recorded scenes 1 to 4 shown in FIG. The user operates the editing controller 4 to select an attractive cut from the display screen. At this time, the tape counter numbers corresponding to the start position and the end position of the cut are stored in the memory built in the editing controller 4. In this example, it is assumed that cuts A to D shown by diagonal lines are respectively selected from the recorded scenes 1 to 4 shown in FIG.

Here, the cuts A to D selected as described above
Consider that A is connected in the order of A, D, B, and C to create a video library. First, the editing controller 4
Performs the rewinding operation of the VTR 1 on the basis of the tape counter number corresponding to the start position of the cut A to find the cut A. After the end of this cueing, the edit controller 4 simultaneously executes the reproduction operation of the VTR 1 and the recording operation of the VTR 2 to record the cut A on the video tape set in the VTR 2. At this time, VTR1
The operation of the VTR1 and VTR2 is stopped when the number of counts of the tape counter provided in (1) reaches the number indicating the end position of the cut A. Next, the edit controller 4 performs the fast-forward operation of the VTR 1 based on the tape counter number corresponding to the start position of the cut D to find the cut D. After the end of this cueing, the editing controller 4 simultaneously executes the reproduction operation of the VTR 1 and the recording operation of the VTR 2 to record the cut D on the video tape set in the VTR 2. At this time, VTR1
When the number of counts of the tape counter provided in the above has reached the number indicating the end position of the cut D, the operations of VTR1 and VTR2 are stopped.

Next, the editing controller 4 determines the VTR based on the tape counter number corresponding to the start position of the cut B.
The rewinding operation No. 1 is executed and the cut B is cued. After the end of this cue, the editing controller 4 sets V
The reproduction of TR1 and the recording operation of VTR2 are simultaneously executed to record the cut B on the video tape set in VTR2. At this time, when the count number of the tape counter provided in the VTR1 reaches the number indicating the end position of the cut B, the operations of the VTR1 and VTR2 are stopped. Next, the edit controller 4 sets V based on the tape counter number corresponding to the start position of the cut C.
The fast-forward operation of TR1 is executed to find the cut C. After the end of this cueing, the editing controller 4 simultaneously executes the reproduction operation of the VTR 1 and the recording operation of the VTR 2 to record the cut C on the video tape set in the VTR 2. At this time, the operations of the VTR1 and VTR2 are stopped when the count number of the tape counter provided in the VTR1 reaches the number indicating the end position of the cut C.

By the above-described operation, the cuts A, D, B and C are connected and recorded as shown in FIG. 2B on the video tape set in the VTR 2. However, as described above, since the recording medium to be edited is a video tape, there is a problem in that it takes time to find each cut and it takes time to perform the editing work.

In order to confirm whether the cuts are properly connected, a video tape in which the cuts are edited and recorded as shown in FIG. 2B. However, there is a problem in that it is time-consuming to create and to reproduce the recorded information on the video tape and monitor it.

[0009]

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and provides an image signal editing apparatus using a multi-head player capable of editing a video tape by an easy operation. The purpose is to provide.

[0010]

An image signal editing apparatus using a multi-head player according to the present invention comprises at least two recording / reproducing heads for reading recorded information from a recording medium on which an image signal to be edited is recorded. Have
A multi-head player for reproducing and transmitting the image signal based on a read signal from a selected recording / reproducing head of the recording / reproducing heads, and a plurality of cuts from the image signal transmitted from the multi-head player. A cut image selecting means for selecting an image signal and storing a frame address signal of each of these cut image signals in a memory;
A reproduction order setting means for setting the reproduction order of each of the cut image signals to obtain reproduction order information, a reading means for reading the frame address signal from the memory, and a frame address signal read by the reading means. Search operation command generating means for supplying a search operation command signal to the multi-head player to forcibly move each of the recording / reproducing heads to a corresponding position, and read each of the recording / reproducing heads in the order based on the reproduction order information. And a play action command generating means for supplying a play action command signal to the multi-head player to operate.

[0011]

The recording / reproducing heads are moved to respective recording positions of a plurality of cut image signals selected from the image signals recorded on the recording medium, and these recording / reproducing heads are read in the order corresponding to the cut image reproducing order. To operate.

[0012]

FIG. 3 is a diagram showing the configuration of an image signal editing apparatus using a multi-head player according to the present invention. In the figure, a VTR (video tape recorder) 1 reproduces the record information of the video tape set in the VTR 1 in response to a play operation, and the reproduced image signal obtained at this time is reproduced in a VDR (video tape) having a multi-head structure. It is supplied to the disk recorder) 5. The VDR 5 records the reproduced image signal supplied from the VTR 1 on a recording disk as a recording medium, while reproducing the image signal recorded on the recording disk and supplies the reproduced image signal to the VTR 1 and the editing controller 6, respectively. . The edit controller 6 supplies various command signals for executing the recording / reproducing operation of the VDR 5 as described above to the VDR 5. Also, the editing controller 6
Generates the editing work image signal by synthesizing the reproduction image signal supplied from the VDR 5 and the editing work image frame signal, and supplies the editing work image signal to the display 3. Display 3
Displays an image for editing work based on the image signal for editing work.

Below, the VDR 5 and the editing controller 6
Will be described in detail. FIG. 4 is a diagram showing the internal configuration of the VDR 5. In the figure, a recording disk 51
The recording / reproducing heads 53 and 54 are respectively arranged with the spindle motor 52 for rotating and driving 180 ° opposed to each other. The slider 55 moves the recording / reproducing head 53 in the radial direction of the recording disk 51 according to the play operation command signal, the search operation command signal, and the frame address signal supplied from the VDR controller 56. On this occasion,
The slider 55 is provided on the recording disk 51 corresponding to the above-mentioned frame address signal in response to the search operation command signal.
The recording / reproducing head 53 is forcibly transferred to the upper position. The recording / reproducing head 53 reads the record information from the recording disk 51 in response to the play operation command signal supplied from the VDR controller 56, and supplies the read signal obtained at this time to the selector 57. The slider 58 moves the recording / reproducing head 54 in the radial direction of the recording disk 51 according to the play operation command signal, the search operation command signal, and the frame address signal supplied from the VDR controller 56. At this time, the slider 58 forcibly moves the recording / reproducing head 54 to a position on the recording disk 51 corresponding to the above-mentioned frame address signal in response to the search operation command signal.

The recording signal generating circuit 59 modulates / encodes the reproduced image signal supplied from the VTR 1 into a desired format and converts it into a recording signal of a predetermined format, which is then reproduced by the recording / reproducing head 5.
Supply to 4. The recording / reproducing head 54 sequentially records the recording signal supplied from the recording signal generating circuit 59 on the recording disk 51 in response to the recording command signal supplied from the VDR controller 56. Also, the recording / reproducing head 5
4 reads the record information from the recording disk 51 according to the play operation command signal supplied from the VDR controller 56, and the read signal obtained at this time is read by the selector 57.
Supply to. The selector 57 is the VDR controller 56.
According to the head selection signal supplied from the recording / reproducing head 53, either the read signal from the recording / reproducing head 53 or the read signal from the recording / reproducing head 54 is selected and supplied to the recording information signal reproducing circuit 60. For example, the selector 57
When the head selection signal supplied from the VDR controller 56 is a logic "0", the read signal from the recording / reproducing head 54 is selectively supplied to the recording information signal reproducing circuit 60, while the head selection signal is a logical signal. When it is "1", the read signal from the recording / reproducing head 53 is selectively supplied to the recording information signal reproducing circuit 60. Furthermore, the VDR controller 56 supplies the recording command signal supplied from the editing controller 6 via the CPU bus 80 to the recording / reproducing head 54.

Further, the VDR controller 56 uses the C
A search operation command signal is supplied to the slider 55 according to the first head search operation command signal and the transfer destination frame address signal supplied via the PU bus 80. Furthermore, VD
The R controller 56 supplies the search operation command signal to the slider 58 according to the second head search operation command signal and the transfer destination frame address signal supplied via the CPU bus 80. Also, the VDR controller 56
In response to the first head play operation command signal supplied via the CPU bus 80, while supplying the play operation command signal to the recording / reproducing head 53, the head selection signal of logic "1" is supplied to the selector 57. In addition, the VDR controller 56
Supplies a play operation command signal to the recording / reproducing head 54 and a head selection signal of logic "0" to the selector 57 in response to the second head play operation command signal supplied via the CPU bus 80. To do.

The recording information signal reproducing circuit 60 obtains a reproduced image signal by demodulating and decoding the read signal supplied from the selector 57 as desired. The reproduced image signal is supplied to the VTR 1 and the edit controller 6 shown in FIG. 3, respectively. At this time, when a recording operation is performed in the VTR 1, the reproduced image signal supplied from the recording information signal reproducing circuit 60 is dubbed and recorded on the video tape set in the VTR 1.

As described above, in such VDR5,
The two recording / reproducing heads 53 and 54 are independently read in response to various command signals supplied from the editing controller 6, and information reproduction output is performed based on a read signal from one of these recording / reproducing heads. It is composed. FIG. 5 is a diagram showing the configuration of the editing controller 6.

In the figure, the edit image memory 61 has a first
The image frame signal for editing work and the second image frame signal for editing work are stored in the editing image memory 62 in advance. FIG. 6 shows a first edit work image display which is displayed and formed on the display 3 according to the first edit work image frame signal, and FIG. 7 shows a display according to the second edit work image frame signal. FIG. 7 is a diagram showing an example of a second image display for editing work which is displayed and formed on the display device 3.

As shown in the figure, the first editing work image includes a monitor screen display area 11, a sub monitor screen display area 12, a remote operation display 13, a cut title input display area 14, and a cut start position setting switch display 15. A cut end position setting switch display 16, a cut start frame address display area 17, a cut end frame address display area 18, a repeat playback operation display 19, and a registration designation switch display 20 are formed.

In the second editing work image, a plurality of divided cut screen display areas 31 to 39, title display areas 41 to 49 respectively associated with the divided cut screen display areas 31 to 39, and Reproduction operation displays 40 are formed respectively. In FIG. 5, the reproduced image signal supplied from the VDR 5 is supplied to the monitor image generation circuit 63, the cut image generation circuit 64, and the address extraction circuit 65, respectively.

The monitor image generation circuit 63 extracts an image signal from the reproduced image signal, and extracts it from the monitor image display area 11 and the sub monitor screen display area 12 shown in FIG.
The monitor image signals converted into the signal formats that can be displayed in the respective areas are generated, and these are supplied to the image synthesizing circuit 66. The address extraction circuit 65 extracts a frame address signal in the image signal from the reproduced image signal supplied from the VDR 5, and supplies this to the address image generation circuit 67, the frame address memory 68, and the CPU bus 80. The address image generation circuit 67 converts the supplied frame address signal into a signal format that can be displayed in each of the cut start frame address display area 17 and the cut end frame address display area 18 shown in FIG. A signal is generated and supplied to the image synthesis circuit 66. The image synthesizing circuit 66 synthesizes the first editing work image frame signal stored in the editing image memory 61, the monitor image signal supplied from the monitor image generating circuit 63, and the above-mentioned address image signal. An image signal for editing work is generated and supplied to the selector 69.

The cut image generation circuit 64 extracts an image signal from the reproduced image signal supplied from the VDR 5, and puts it in a signal format that can be displayed in each of the cut screen areas 31 to 39 shown in FIG. Generate the converted image signal,
This is supplied to the image synthesis circuit 66. At this time, when the cut start position setting signal is supplied via the CPU bus 80, only the image signal for one frame is extracted from the image signal extracted as described above and supplied to the cut image memory 70. The cut image memory 70 cumulatively stores the image signals for one frame sequentially supplied from the cut image generating circuit 64 while updating the storage address. Further, the cut image memory 70 responds to a data movement command signal supplied via the CPU bus 80, and stores data in two memory addresses designated by the command signal (that is, an image signal for one frame). Swap each other.

The image synthesizing circuit 71 includes an edited image memory 62.
A second editing work image frame signal stored in
A second editing work image signal is generated by synthesizing each image signal for one frame stored in the cut image memory 70 and the image signal supplied from the cut image generation circuit 64, and supplies this to the selector 69. To do. At this time, the image synthesizing circuit 71 compares the storage address of the cut image memory 70 with that of FIG.
The image signals for one frame stored in the cut image memory 70 and the second image frame signal for editing work are combined by associating with each of the cut screen display areas 31 to 39 shown in FIG.

For example, when the cut image memory 70 is one for accumulating and storing the image signal for one frame for each "100" (HEX display) as shown in FIG. 8, the first "001" to "001". The image signal for one frame stored in the address "100" is synthesized at the position of the cut screen area 31 in FIG. 7, and the image signal for one frame stored in the next addresses "101" to "200" is It is synthesized at the position of the cut screen area 32 in FIG.

The selector 69 is supplied from the first edit work image signal supplied from the image synthesizing circuit 66 or from the image synthesizing circuit 71 in accordance with the edit image selection switching signal supplied via the CPU bus 80. One of the second editing work image signals is selected and the selected editing work image signal is supplied to the display 3. The frame address memory 68 cumulatively stores the frame address signal supplied from the address extraction circuit 65 in the data upper bits in accordance with the cut start position setting signal supplied via the CPU bus 80. Further, the frame address memory 68 cumulatively stores the frame address signal supplied from the address extracting circuit 65 in the data lower bits in accordance with the cut end position setting signal supplied via the CPU bus 80.

FIG. 9 shows such a frame address memory 6
8 is a diagram showing an example of a memory map of FIG. In the figure,
The frame address memory 68 stores the frame address signal supplied from the address extraction circuit 65 at this point in the upper data bit of the address "1" according to the cut start position setting signal supplied first. On this occasion,
When the cut end position setting signal is supplied, the frame address signal supplied from the address extracting circuit 65 at this time is stored in the lower data bit of the address "1". Further, the frame address memory 68 stores the frame address signal supplied from the address extraction circuit 65 at this point in the upper data bit of the address "2" according to the cut start position setting signal supplied next. At this time, when the cut end position setting signal is supplied, the frame address signal supplied from the address extracting circuit 65 at this time is stored in the lower data bit of the address "2". Less than,
By the same operation, the frame address memory 68 cumulatively stores the frame address signal while updating its storage address each time the cut start position setting signal and the cut end position setting signal are supplied. Further, the frame address memory 68 exchanges the stored data (that is, the frame address signal) in the two storage addresses designated by the command signal in response to the data movement command signal supplied via the CPU bus 80. . Further, the frame address memory 68 sends the stored contents to the CPU bus 80 in the order of storage addresses in response to a data read command signal supplied via the CPU bus 80. That is, each of the frame address signals stored as shown in FIG. 9 corresponds to the CPU bus 80 in response to the data read command signal.
It is sent up.

The editing operation device 81 is an input device including, for example, a mouse and a keyboard, and sends a coordinate signal and an operation signal according to a user's operation to the CPU bus 80. At this time, the coordinate signal obtained by moving the position of the mouse is converted by an image coordinate controller (not shown) into a cursor image signal capable of displaying a cursor at a screen position corresponding to the coordinate. The cursor image signal is combined with the output of the selector 69 and supplied to the display 3. The CPU (Central Processing Unit) 82 sends out various command signals as described above to the CPU bus 80 based on the software stored in the ROM (Read Only Memory) 83 and the above operation signals.

Next, the operation of this configuration will be described. At this time, the VTR 1 in FIG.
A videotape in which four different scenes as shown in (a) are recorded is set, and the following is an example of an editing operation when performing editing as shown in FIG. 2B based on the videotape. I will describe.

First, the editing controller 6 simultaneously executes the reproducing operation of the VTR 1 and the recording operation of the VDR 5,
The image signals including the recording scenes 1 to 4 shown in (a) are recorded as they are on the recording disk 51 of the VDR 5. FIG. 10 is a diagram showing a recording state of the recording disk 51 in the recording operation. Next, the editing controller 6 displays the first image for editing work on the display 3 as shown in FIG. Here, the user operates the edit operation device 81 as desired to move the cursor to an arbitrary position on the remote operation display 13 during the display of the first image for editing work and clicks it. For example, on the remote operation display 13, fast-forward for remote operation of the VDR 5,
Rewind, double speed reproduction, scan reproduction and normal reproduction operation display are provided. When the cursor is moved to any position on these displays and clicked, the edit controller 6 supplies a command signal for causing the VDR 5 to execute the display operation to the VDR 5 via the CPU bus 80. At this time, if any one of the double speed reproduction, the scan reproduction, and the normal reproduction operation display on the remote operation display 13 is clicked, the VDR 5 performs the reproduction operation according to the operation. As a result, the reproduced image is displayed on the monitor screen display area 11 and the sub monitor screen display area 12. Here, the user is required to monitor the monitor screen display area 11
While monitoring, the desired cuts A to D indicated by the diagonal lines in FIG. 10 are selected from the displayed image.

The cut image selection operation will be described below. First, when confirming the image display of the cut A while monitoring the monitor screen display area 11, the user:
The edit operation device 81 is operated as desired to move the cursor to a position on the cut start position setting switch display 15 and click. In response to this operation, the frame address "a1" corresponding to the start position of the cut A is stored in the upper data bit of the address "1" of the frame address memory 68 as shown in FIG. At this time, the image signal for the first frame in the cut A is "001" to "10" in the cut image memory 70 as shown in FIG.
It is stored in the address "0". Next, when confirming the end of the image display of the cut A while monitoring the monitor screen display area 11, the user operates the edit operation device 81 as desired to move the cursor to the cut end position setting switch display 16. Move to the position of and click. In response to such movement,
The frame address "a" corresponding to the cut A end position
2 "is stored in the lower data bits of the address" 1 "of the frame address memory 68 as shown in FIG. After such an operation, the user can see the cut title input display area 1
While monitoring No. 4, the title of the cut A is input by the edit operation device 81, and then the cursor is moved to the registration designation switch display 20 and clicked. By this operation, the input title information signal is stored in the addresses "001" to "100" of the cut image memory 70.

Next, when the user confirms the image display of the cut B while monitoring the monitor screen display area 11, the user operates the editing operation device 81 as desired to display the cursor for the cut start position setting switch. 15 Move to the position above and click. In response to this operation, the frame address "b1" corresponding to the start position of the cut B is stored in the upper data bit of the address "2" of the frame address memory 68. At this time, the image signal for the first frame in the cut B is “10” in the cut image memory 70.
It is stored in addresses "1" to "200". Next, when confirming the end of the image display of the cut B while monitoring the monitor screen display area 11, the user operates the editing operation device 81 as desired to move the cursor to the cut end position setting switch display 16. Move to the position of and click. In response to this operation, the frame address “b2” corresponding to the end position of the cut B is stored in the lower data bit of the address “2” of the frame address memory 68. After such an operation, the user monitors the cut title input display area 14 and inputs the title of the cut B with the editing operation device 81, and then moves the cursor onto the registration designation switch display 20 and clicks it. By this operation, the input title information signal is converted into the cut image memory 7
It is stored in the address "101" to "200" of 0.

Thereafter, by the same operation, the frame address "c1" corresponding to the start position and the end position of the cut C is obtained.
And "c2" are stored in the address "3" of the frame address memory 68, and the image signal for the first frame in the cut C is stored in the addresses "201" to "300" of the cut image memory 70. Memorized in. Further, by the above-described operation, the frame addresses “d1” and “d” corresponding to the start position and the end position of the cut D are obtained.
2 ”is stored in the address“ 4 ”of the frame address memory 68, and the image signal for the first frame in the cut D is“ 301 ”in the cut image memory 70.
~ Stored in address "400".

Next, the editing controller 6 displays a second image for editing work on the display 3 as shown in FIG. At this time, “001” of the cut image memory 70
1 frame of image signal stored in addresses "100" is displayed as a still image on the cut screen area 31 and stored in addresses "101" to "200" of the cut image memory 70. An image signal for a frame is displayed as a still image on the cut screen area 32, and an image signal for one frame stored in addresses “201” to “300” of the cut image memory 70 is a cut screen area as a still image. 33 is displayed on the cut image memory 70, and “30
The image signal for one frame stored in addresses 1 "to" 400 "is displayed as a still image on the cut screen area 34. Further, from "001" of the cut image memory 70
A title corresponding to the title information signal stored in the address "100" is displayed on the title display area 41,
A title corresponding to the title information signal stored in the addresses "101" to "200" of the cut image memory 70 is displayed in the title display area 42, and in the addresses "201" to "300" of the cut image memory 70. A title corresponding to the title information signal stored in the cut image memory 70 is displayed on the title display area 43, and “301” of the cut image memory 70 is displayed.
A title corresponding to the title information signal stored in the address "400" is displayed on the title display area 44.

That is, at that time, the still image at the beginning of cut A is displayed in the cut screen area 31, the still image at the beginning of cut B is displayed in the cut screen area 32, and the still image at the beginning of cut C is displayed. The still image is displayed in the cut screen area 33, and the cut D
The still image at the beginning portion of is displayed in the cut screen area 34. At this time, if the user clicks any one of the cut screen areas and then clicks the playback operation display 40, the cut displayed as a still image in the clicked cut screen area is played back and displayed as a moving image. You can

Here, the cut screen areas 31 to 39
The sequence of corresponds to the reproduction order of each cut at the time of editing. At this time, the user rearranges the reproduction order of the cut images in a desired order by sequentially clicking the two cut screen areas. At this time, the user first clicks the cut screen areas 32 and 34 in order in order to rearrange them in the order as shown in FIG. In response to such an operation, "10" in the cut image memory 70 as shown in FIG.
The image signals stored in the addresses "1" to "200" are replaced with the image signals stored in the addresses "301" to "400" of the cut image memory 70. At the same time, the frame address memory 68 as shown in FIG.
The frame address signal stored in the address "2" of the above and the frame address signal stored in the address "4" of the frame address memory 68 are exchanged.

By this operation, the still image at the beginning of the cut A is displayed in the cut screen area 31, and the still image at the beginning of the cut D is displayed in the cut screen area 32.
The still image at the beginning of the cut C is displayed in the cut screen area 33, and the still image at the beginning of the cut B is displayed in the cut screen area 34. After that, the user sequentially clicks the cut screen areas 33 and 34. In response to such an operation, the image signals stored in the addresses "201" to "300" of the cut image memory 70 as shown in FIG.
The image signals stored in the addresses "1" to "400" are replaced. At the same time, the frame address signal and the frame address memory 68 stored in the address "3" of the frame address memory 68 as shown in FIG.
The frame address signal stored in the address "4" of the above is replaced.

Finally, as shown in FIG. 11, in the frame address memory 68, the cut A is at the address "1", the cut D is at the address "2", the cut B is at the address "3", and the cut B is at the address "4". Each of the cut start frame address and the cut end frame address signal corresponding to the cut C is stored. That is, the frame address memory 68 stores the reproduction order information in which the start frame address and the cut end frame address signal of each cut are set in the order corresponding to the reproduction order of the edited cut images.

At this time, the cut A is displayed in the cut screen area 31.
Of the cut D is displayed in the cut screen area 32, the still image of the start portion of the cut B is displayed in the cut screen area 33, and the cut screen area 34 is displayed. A still image at the beginning of the cut C is displayed at. The above-described operation completes the concatenation editing of cuts A, D, B, and C. The user sequentially clicks the cut screen areas 31 to 34 while clicking the reproduction operation display 40 to sequentially display the images of the cuts A, D, B, and C on the cut screen areas 31 to 34. Virtually monitor the edited result.

After the monitor is finished, the user can
The recorded video tape set to 1 is taken out, and a new video tape to be used as a video library is set to the VTR 1. Next, the editing controller 6 simultaneously executes the recording operation of the VTR 1 and the program reproducing operation of the VDR 5, thereby dubbing the virtual editing result as described above to the video tape set in the VTR 1.

12 and 13 are flowcharts showing the program reproduction operation flow of the VDR 5 executed by the CPU 82 of the edit controller 6. First, the CPU 82
Causes the register N to store "1" as the first storage address of the frame address memory 68 (step S
1). Next, the CPU 82 uses the frame address memory 6
The storage data stored in the storage address indicated by the register N is read out from 8. The CPU 82 stores the upper data of the read storage data in the register S1, and further stores the lower data of the storage data in the register E.
1 (step S2). Next, the CPU 82
Supplies the first head search operation command signal to the VDR 5 by using the contents stored in the register S1 as the transfer destination frame address signal (step S3). By executing the step S3, the recording / reproducing head 53 of the VDR 5
Moves to a position on the recording disk 51 according to the contents stored in the register S1.

After the moving operation of the recording / reproducing head 53 is completed, the CPU 82 supplies the first head play operation command signal to the VDR 5 (step S4). By executing step S4, the recording / reproducing head 53 starts the reproducing operation from the above-mentioned movement end position. At this time, the read signal read by the recording / reproducing head 53 is demodulated and decoded by the recording information signal reproducing circuit 60 to become a reproduced image signal, and this reproduced image signal is supplied to the VTR 1.
After executing step S4, the CPU 82 adds a value obtained by adding “1” to the storage content of the register N.
Is overwritten and stored (step S5).

Next, the CPU 82 reads the storage data stored in the storage address indicated by the register N from the frame address memory 68. The CPU 82 stores the upper data of the read storage data in the register S2, and further stores the lower data of the storage data in the register E2 (step S6). Next, CPU
82 supplies the second head search operation command signal to the VDR 5 by using the content stored in the register S2 as the transfer destination frame address signal (step S7). By executing the step S7, the recording / reproducing head 5 of the VDR 5
4 moves to a position on the recording disk 51 according to the contents stored in the register S2. That is, the recording / reproducing head 54 moves as described above during the reproducing operation by the recording / reproducing head 53.

After the moving operation of the recording / reproducing head 54 is completed, the CPU 82 keeps the frame address signal and the register E1 until the frame address signal obtained by the address extraction circuit 65 and the stored content of the register E1 become equal. Is compared with the stored contents (step S
8). When it is determined in step S8 that the frame address signal obtained by the address extraction circuit 65 and the stored content of the register E1 are equal, the CPU 82 outputs V
A second head play operation command signal is supplied to DR5 (step S9). By executing step S9, the recording / reproducing head 54 starts the reproducing operation from the above-mentioned movement end position. At this time, the read signal read by the recording / reproducing head 54 is demodulated and decoded by the recording information signal reproducing circuit 60 to become a reproduced image signal, and this reproduced image signal is supplied to the VTR 1. After the execution of step S9, the CPU 82 overwrites and stores the value obtained by adding “1” to the storage content of the register N in the register N (step S10).

Next, the CPU 82 reads the storage data stored in the storage address indicated by the register N from the frame address memory 68. The CPU 82 stores the upper data of the read storage data in the register S1, and further stores the lower data of the storage data in the register E1 (step S11). Next, CP
The U 82 supplies the first head search operation command signal to the VDR 5 by using the content stored in the register S1 as the transfer destination frame address signal (step S12). By executing step S12, the recording / reproducing head 53 of the VDR 5 moves to the position on the recording disk 51 according to the contents stored in the register S1. That is, the recording / reproducing head 53 moves as described above during the reproducing operation by the recording / reproducing head 54.

After the moving operation of the recording / reproducing head 53 is completed, the CPU 82 keeps the frame address signal and the register E2 until the frame address signal obtained by the address extraction circuit 65 and the stored content of the register E2 become equal. Is compared with the stored contents (step S
13). In step S13, the address extraction circuit 6
If it is determined that the frame address signal obtained in 5 and the stored contents of the register E2 are equal, the CPU 82
Determines whether the stored content of the register N exceeds the final storage address of the frame address memory 68 used in the above-described linked editing work (step S14). When it is determined in step S14 that the final storage address has not been exceeded, the CPU 82 returns to the operation of step 4 and repeatedly executes the above-described operation. Also, step S1
If it is determined in step 4 that the final memory address is exceeded, the program reproducing operation as described above ends.

The above registers N, S1, S2, E1
And E2 are registers built in the CPU 82. Next, VDR by such program playback operation
An operation example of No. 5 will be described with reference to FIGS. 10 and 11.
By executing the first steps S1 to S3, the recording / reproducing head 53 of the VDR 5 moves to the position of the frame address "a1" shown in FIG. Next, by executing step S4, the recording / reproducing head 53 starts the reproducing operation from the position of the frame address "a1", and reads the cut A portion in the scene 1. At this time, since the reproduced image signal corresponding to the cut A is supplied to the VTR 1, a signal corresponding to the cut A is recorded on the video tape set in the VTR 1 as shown in FIG. 2B. Go. During the reproducing operation by the recording / reproducing head 53, steps S4 to S7 are executed to move the recording / reproducing head 54 of the VDR 5 to the position of the frame address "d1" shown in FIG. The recording / reproducing head 54
When it is confirmed that the recording / reproducing head 53 has completed the reproducing operation up to the position of the frame address “a2” shown in FIG. 10 after the movement of step S8, the recording / reproducing head 54 is immediately executed by executing step S9. Starts the reproducing operation from the position of the above-mentioned frame address "d1". Therefore, at this time, since the reproduced image signal corresponding to the cut D in the scene 4 is supplied to the VTR 1,
As shown in FIG. 2 (b), the signal corresponding to the cut D is recorded on the video tape set to No. 2 immediately after the end of the cut A.

During the reproducing operation by the recording / reproducing head 54, steps S10 to S12 are executed to execute VDR5.
The recording / reproducing head 53 is moved to the position of the frame address "b1" shown in FIG. After the recording / reproducing head 53 is moved, step S13 is executed, and the recording / reproducing head 54 is moved to the frame address "d" shown in FIG.
When it is confirmed that the reproducing operation has been completed up to the position "2", the recording / reproducing head 53 immediately starts the reproducing operation from the position of the above-mentioned frame address "b1" by executing step S4 again. Therefore, at this time, since the reproduced image signal according to the cut B in the scene 3 is supplied to the VTR 1, the video tape set in the VTR 1 has the cut D after the end of the cut D as shown in FIG. 2B. Immediately, the signal corresponding to cut B is recorded.

By repeatedly executing the above operation, the cut image signals which are continuously connected are recorded on the video tape set in the VTR 1 as shown in FIG. 2B. Here, in step S14, when it is confirmed that the value of the register N exceeds the final storage address of the frame address memory 68, that is, "4" in the example of FIG. 11, the program reproducing operation is stopped.

As described above, in the program reproducing operation, the frame address signals are read out from the frame address memory 68 in the order of their storage addresses, and the recording / reproducing heads transferred to the positions corresponding to the read frame address signals are sequentially selected. Reproduction operation control such as reading operation is performed. In the above embodiment, the dubbing operation by simultaneously executing the program reproducing operation and the recording operation of the VTR 1 has been described.
This VDR5 is executed without executing the recording operation of the VTR1.
By displaying the image signal obtained by the program reproduction operation in the monitor screen display area 11 shown in FIG. 6, the edited result can be virtually monitored. According to such a virtual monitor, the connected cut images can be virtually monitored without recording the connected cut image signals as shown in FIG. 2B on the video tape, so that the editing work can be easily redone. Becomes

Further, in the above-mentioned embodiment, the read / write heads 53 and 54 are arranged to alternately execute the reading operation to obtain the concatenated cut image signal. A recording / reproducing head may be used. In short, the plurality of recording / reproducing heads are respectively moved to the plurality of desired positions on the recording medium (that is, the start positions of the respective cuts selected by the above-described cut selecting operation), and the respective recording / reproducing heads are moved to the desired positions. It suffices that the read signals obtained by sequentially performing the reading operations are connected and reproduced and output.

Further, in the above embodiment, the storage address of the frame address memory 68 and the reproduction order of the edited cuts are made to correspond to each other, and the storage addresses of the storage contents of the frame address memory 68 are exchanged based on this reproduction order. However, the configuration is not limited to this.
For example, the information for instructing the reproduction order is generated, stored in the reproduction order memory, and the reading operation of each recording / reproducing head is executed based on the reproduction order stored in the reproduction order memory. Is also good.

[0052]

As described above, in the image signal editing apparatus using the multi-head player of the present invention, recording / reproducing is performed at each recording position of a plurality of cut image signals selected from the image signals recorded on the recording medium. The heads are moved so that the recording / reproducing heads are read and operated in the order corresponding to the cut image reproducing order.

Therefore, according to the present invention, a plurality of cut image signals which are not continuous among the image signals to be edited recorded on the recording medium are connected in a desired order without interruption. It can be reproduced and output. Therefore, even if the edited result is dubbed onto a video tape and the information is reproduced from the video tape and the edited result is not monitored, the edited result can be virtually monitored based on the above-mentioned reproduction output, which facilitates the editing work. It is very desirable.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a conventional image signal editing system.

FIG. 2 is a diagram showing an example of a recording state of a video tape by an editing work.

FIG. 3 is a diagram showing a configuration of an image signal editing apparatus using a multi-head player according to the present invention.

FIG. 4 is a diagram showing a configuration of VDR5.

5 is a diagram showing a configuration of an editing controller 6. FIG.

FIG. 6 is a diagram showing an example of a first editing work display image.

FIG. 7 is a diagram showing an example of a second display image for editing work.

8 is a diagram showing an example of a memory map of a cut image memory 70. FIG.

9 is a diagram showing an example of a memory map of a frame address memory 68. FIG.

FIG. 10 is a diagram showing an example of a recording state of a recording disk 51.

11 is a diagram showing an example of stored contents of a frame address memory 68. FIG.

FIG. 12 is a VDR5 program playback operation flowchart.

FIG. 13 is a flow chart of a program reproducing operation of VDR5.

[Explanation of symbols for main parts]

 5 VDR 6 Editing controller 53, 54 Recording / playback head 57 Selector

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[Procedure amendment]

[Submission date] March 8, 1994

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 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yoshio Ishizawa 2680 Nishihanawa, Tatomi-cho, Nakakoma-gun, Yamanashi Pioneer Video Co., Ltd.

Claims (3)

[Claims] 1. At least 2 for reading recorded information from a recording medium on which an image signal to be edited is recorded.
A multi-head player which has two recording / reproducing heads and reproduces and transmits the image signal based on a read signal from a recording / reproducing head selected from the recording / reproducing heads; Cut image selecting means for selecting a plurality of cut image signals from the image signals and storing a frame address signal of each of these cut image signals in a memory; and a reproduction order information for setting the reproduction order of each of the cut image signals. Retrieval order setting means for obtaining, reading means for reading the frame address signal from the memory, and search for forcibly transferring each of the recording / reproducing heads to a position corresponding to the frame address signal read by the reading means. Search operation command generating means for supplying an operation command signal to the multi-head player; And a play operation command generating means for supplying a play operation command signal to the multi-head player so as to read each of them in the order based on the reproduction order information. apparatus. 2. The recording / reproducing head comprises two first and second recording / reproducing heads, and the second recording / reproducing head searches while the first recording / reproducing head is performing a reading operation. The multi-head player receives the search operation command signal and the play operation command signal so that the first recording / reproducing head performs the search operation while the second recording / reproducing head performs the reading operation. An image signal editing apparatus using a multi-head player characterized by being supplied. 3. The reproduction order setting means replaces the storage address of each frame address signal stored in the memory in accordance with the reproduction order of each of the cut image signals and uses this as the reproduction order information. An image signal editing device using a characteristic multi-head player.