JPH07235896A - Adaptive equalizer - Google Patents

Abstract

PURPOSE:To eliminate the effect of a sampling phase shift without increasing power consumption and a circuit scale in an MLSE equalizer. CONSTITUTION:A transmission line estimate device 279 is made up of a gain vector computing element 282 generating a gain vector by multiplying a vector whose elements are an output of a mapping circuit 276 with a weight coefficient having a timewise exponential attenuation characteristic, a correlation device 281 obtaining the correlation between the gain vector and an error signal, and an integration device 280 adding an output signal of the correlation device to a tap coefficient of one preceding time as a revision of a tap coefficient and providing an output of the result of sum as a tap coefficient. Then the mapping circuit 276 is made up of a tapped delay line filter implementing convolution processing to a transmission signal object series by using a product of a matrix whose diagonal elements are elements of an autocorrelation matrix of a waveform shaping filter output and a vector using impulse response of the filter as elements as a tap coefficient.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an equalizer for automatically compensating for waveform distortion due to delay generated in a propagation path in digital signal transmission.

[0002]

2. Description of the Related Art In digital signal transmission, intersymbol interference occurs in a demodulated signal due to the influence of a delayed wave generated in a propagation path, so that transmission characteristics are significantly deteriorated. An adaptive equalizer is an effective technique for compensating for this intersymbol interference. When the symbol space equalizer is applied as the equalizer, the optimum sampling phase changes depending on the delay amount of the delay wave. When the symbol space equalizer is applied to a transmission line in which the transmission line condition changes with time, such as a mobile transmission line, deterioration of the demodulation characteristics due to the optimum sampling phase change associated with the change in the transmission line condition cannot be avoided. Equalizers that can remove the influence of this sampling phase include a transversal linear equalizer with a fractional tap space or a decision feedback equalizer.

A maximum likelihood sequence estimation (MLSE: Maximum Likelihood) is applied to an equalizer having a higher equalization capability.
There is a d Sequence Estimator type equalizer. The method of removing the influence of the sampling phase in the MLSE type equalizer is as follows: (a) Sampling is performed at M times the symbol frequency and serial / parallel conversion is performed into an M series signal. Next, of the M series signals of this T (sampling period) interval, the series having the smallest error signal, that is, the sampling phase closest to the optimum sampling phase is selected and the demodulated signal of that series is used as the output signal. (B) Sampling is performed at a speed twice or more the Nyquist frequency, and at the same time, a temporary decision value sequence generated by the maximum likelihood sequence estimator is passed through a waveform shaping filter that samples at the same frequency as the sampling frequency of the received signal. Next, a replica of the received signal is generated from this filter output signal, and the error is used as likelihood information for maximum likelihood sequence estimation.

On the other hand, in digital signal transmission, bursts are divided on the time axis and a transmission channel is assigned to each burst, which is time division multiple access (TDMA).
Ion Multiple Access) method is used. At this time, as shown in FIG. 7, a preamble for synchronization or a training signal is added mainly to the head of one burst. From the viewpoint of burst utilization efficiency, it is desirable that there are few synchronization signals. That is, when applying the MLSE type equalizer to burst transmission, it is necessary to complete the transmission path estimation at high speed. The algorithm that realizes high-speed transmission channel estimation is based on the recursive least squares (RLS).
There is a Least Squares algorithm. R
The LS algorithm is shown below.

[0005]

[Equation 1]

In the above equation, K _k is a Kalman gain vector, e _k is an error signal, H _k is a tap coefficient, λ is a forgetting coefficient, U _k is a transmission signal candidate sequence, r _k is a reception signal, and P _k is a P matrix. It indicates the inverse matrix of the correlation matrix of a good transmission signal candidate sequence, and the subscript indicates the time. Further, H _k ^T _represents a transpose of the vector H _k , and lower case p _{i, j} , k _i , h _i , and u _i represent i or j elements of P, K, H, and U, respectively. RL
In the S algorithm, since the optimum tap coefficient is obtained from all the signals received from the beginning of the burst, high speed synchronization characteristics can be obtained.

FIG. 8 shows a configuration example in which this RLS algorithm is applied to an MLSE equalizer to which the method (a) is applied.
Shown in. In the figure, 25 is an input terminal, 26 is an output terminal, 27 is an S / P converter, 28 is a subtractor, 29 is a squaring circuit, 30 is a clock input terminal at a speed of M times the symbol rate, and 31 is a channel estimation. , 32 is a replica generator, 3
3 is an integrator, 34 is a tap coefficient update amount arithmetic circuit, 35 is a Kalman gain arithmetic circuit, 36 is a p matrix arithmetic circuit, 37
Is a 1-symbol delay circuit, 38 is an address decoder for the S / P converter 27, 39 is a selection / addition control circuit, 40
Is a selection / addition circuit from N sequences, and 41 is a maximum likelihood sequence estimation circuit.

The P-matrix calculation circuit executes the equation (4), and the Kalman gain calculator executes (1). In addition, the tap coefficient update amount calculation circuit calculates the second term on the right side of (3). Furthermore, the replica generator calculates the second term on the right side of (2). The input signal sampled at M times the symbol frequency is input terminal 2
5 and is converted by the S / P converter 27 into an M-sequence parallel signal. For each of these, an independent M-sequence transmission path estimator 31 and replica generator 32 are provided, and tap coefficient estimation and branch metric generation are performed in the same manner as in a normal MLSE equalizer. The output signal of the squaring circuit 29, which is the branch metric of the surviving path of each series, is input to the selection / addition control circuit. This selection / addition control circuit selects the series having the smallest value among the input signals, or when the selected square circuit input signal exceeds a predetermined threshold, the minimum and some input signals following it are selected. The selection / addition circuit 40 is controlled to add. The branch metric selected / added by the selection / addition circuit 40 is input to the maximum likelihood sequence estimation circuit for sequence estimation, and the decoded signal is output to 26 terminals. FIG. 10 shows a 4-tap transversal filter as a configuration example of the replica generator. In the figure, 89 is an input terminal, 97 is an input bus from the transmission path estimator, 90 to 92 are T delay circuits, 93 to 96 are multipliers, 98 is an adder, and 99 is an output terminal. The convolution calculation is realized by multiplying the input signal from time k to time k-3 by the tap coefficient input from 97 by the multiplier.

FIG. 12 shows, as an example of an integrator, a configuration for integrating four signals of two series. In the figure, 100-1 and 100-2 are input terminals, 101 is an output terminal, 102 is an integrator for one signal, and 103-1 and 1
Reference numeral 03-2 is an adder, and 104 is a T delay circuit. The adder 10 adds the input signals from the input terminals 100-1 and 100-2.
Add by 3-1. Next, the addition output and the signal one symbol before are added together by the adder 103-2, and the signal obtained by integrating the two series of input signals in the section from time 0 to k at time k is output.

FIG. 13 shows a configuration to which the Viterbi algorithm is applied as an example of the maximum likelihood sequence estimator. 1 in the figure
Reference numeral 05 is an error input terminal, 106 is an output terminal, 113 is a temporary judgment value output terminal, 108 is a path metric calculation circuit, 1
Reference numeral 11 is a comparison / selection circuit for comparing and selecting the output signals of several path metric calculation circuits, 112 is a path metric memory circuit for storing the path metric, 114 is a symbol series, and a survival series is stored. A path memory circuit, a switch circuit 107 for switching a path for each series, and a selection circuit 115 for selecting a series having the highest likelihood among the temporary determination values. One of the symbol candidates is output from the path memory circuit. The error signal at that time is input to the path metric calculation circuit 108 corresponding to each series. In the path metric calculation circuit, the error signal is added to the path metric one symbol before in each series by the adder 110 and output to the comparison / selection circuit 111. The comparison / selection circuit 111 selects and outputs the smallest value among the signals output from each series. This value is the path metric memory 1 as the path metric for the symbol candidate.
12 is stored in the path memory 114 as a surviving path. This operation is performed for all the symbol candidates, and after a certain time, the signal of the series having the smallest path metric among the surviving paths is selected by the selection circuit 115 and output as the final demodulated signal. In this sampling phase selection type MLSE equalizer, first, it is necessary to operate the A / D converter at a high sampling frequency of M times the symbol frequency, and M replica generators and RLS type transmission line estimators are required. There is a drawback in that it becomes necessary and leads to an increase in circuit scale and power consumption. Further, if M is reduced to avoid these drawbacks, there is a drawback that the characteristic deterioration due to the sampling phase shift cannot be sufficiently compensated.

On the other hand, FIG. 9 shows an example of the structure of an MLSE type equalizer to which the method (b) is applied, in which sampling is performed at twice the symbol frequency and parallel processing is performed. In the figure, 42 is an input terminal, 43 is an output terminal, 4
4 is an S / P converter, 45 and 46 are subtractors, 47 and 48 are squaring circuits, 49 is an adder, 50 is a clock input terminal for controlling the S / P converter 44, 51 and 64 are switch circuits, 53 is a transmission path estimator, 54 is a replica generator, and 55
Is an integrator, 56 and 59 are tap coefficient update arithmetic circuits, 5
Reference numerals 7 and 60 are Kalman gain arithmetic circuits, 58 and 61 are P matrix arithmetic units, 62 is a symbol period (T) delay circuit, 65 is a maximum likelihood sequence estimator, and 66 is a waveform shaping filter. The input signal sampled at twice the symbol frequency is input from the terminal 42, converted into a two-series signal by the S / P converter 44, and input into the subtracters 45 and 46, respectively. The difference between the estimated value of the received signal called a replica selected by the switch circuit 51 and the actual received signal is subtracted by the subtracters 45 and 4
6, and converted into a power signal by the squaring circuits 47 and 48, and then input to the adder 49. The maximum likelihood sequence estimator 65 uses this adder output signal as likelihood information to perform sequence estimation and outputs a decoded signal to the terminal 43. At the same time, the provisional decision value sequence or the surviving path sequence generated at the time of estimating the maximum likelihood sequence is input to the waveform shaping filter for sampling at the rate of 2 / T, and the replica generator 54 and the RLS transmission line estimator 53 are input.
Output at T / 2 intervals. In the transmission path estimator 53, the output signal from the waveform shaping filter is output by the switch circuit 64 to 2
It is converted into a series of signals. The first sequence updates the tap coefficients according to the normal RLS tap coefficient update algorithm. The rest of the sequences is the P matrix updated by the first sequence, which is 1
The tap coefficient is updated on the assumption that it is before the time, and the updated P matrix is output to the P matrix calculator (1) as the one in the first sequence one time before.

FIG. 14 shows a configuration to which a transversal filter is applied as a configuration example of the replica generator. In the figure, 154 is an input terminal from the maximum likelihood sequence estimator, 155
˜157 are T / 2 delay circuits, 158˜161 are multipliers,
162 is a memory circuit for storing tap coefficients, 163 is an adder, and 164 is an output terminal. The input signal sequence from the input terminal 154 is output to the multiplier as a sequence having different times by the delay circuit, and weighted by different coefficients from the memory. Finally, the adder 163 adds all the outputs and outputs the result to the output terminal 164. In this circuit configuration, the received signal basically satisfies the Nyquist sampling theorem because it samples at a rate twice the symbol rate. Therefore, the characteristic deterioration due to the sampling phase shift can be completely eliminated. However, even with this configuration, RLS
Since two sequences of algorithms are required, the circuit configuration becomes complicated, and the power consumption increases accordingly.

Further, there is a VLMS algorithm as a transmission path estimation algorithm having a simple structure and high-speed synchronization characteristics. The following equation shows the algorithm when this algorithm is applied to the fractional tap space.

[0014]

[Equation 2]

In the above equation, S _{k + 1} is expressed by the following equation.

[0016]

[Equation 3]

FIG. 24 shows an example of the structure of the VLMS algorithm. In the figure, 238 is an input terminal, 244 is an output terminal, 239 is a sampling frequency clock input terminal,
240 is a sampler, 241 is a subtractor, 242 is a squaring circuit, 243 is a maximum likelihood sequence estimator, 245 is a waveform shaping filter, 246 is a replica generator, 247 is a transmission path estimator,
248 is a gain vector calculator, 249 is a weight coefficient circuit, 250 is a matrix calculation circuit, 251 is a multiplication circuit, 252
Is a correlator and 253 is an integrator.

FIG. 11 shows an implementation example of the matrix operation circuit. 1
28 is an input terminal, 129 to 131 are T / 2 delay circuits, 1
32-147 are multipliers, 148-151 are adders, 15
2 is a memory circuit, and 153 is a vector output terminal.

FIG. 15 shows a configuration to which a memory is applied as a configuration example of the mapping circuit. In the figure, 75 is an input terminal from the maximum likelihood sequence estimator, 76 to 78 are T / 2 delay circuits, 79 is a memory circuit for storing tap coefficients, and 80 is an output terminal.

FIG. 17 shows a configuration example of the correlator. In the figure, 184 is an input terminal from the mapping circuit, and 185-
188 is a multiplier, 189 is a weighted error signal input terminal, 182 to 184 are T / 2 delay circuits, and 190 to 1
93 indicates an output terminal. For the signal sequence from the mapping circuit over several time points, the correlation value with the error signal is obtained by a multiplier, and this value is output.

FIG. 18 shows a configuration example of the weighting coefficient circuit. In the weighting coefficient circuit shown in the figure, 165 is a clock signal input terminal, 170 is a coefficient output terminal from the memory, and 167.
Is a binary counter, 166 is a memory element, 168 is a digital comparator, and 169 is a count setting circuit. A clock driven counter 167 counts the number of symbols from the beginning of the burst and outputs it to the memory 166. Based on this time information, the memory is (1-λ) (1-λ ^{k + 1} ) ^-1
The value of is output. On the other hand, the time information of the counter is also input to the comparator 168 at the same time and compared with the value set by the count setting circuit 169. If the time information matches or exceeds the counted setting, the counter is reset and the memory output is fixed. This is the exponentially weighted RL
This is because the correlation matrix Φ (k) of the S algorithm exhibits an exponentially convergent characteristic from (6) and hardly changes at a certain time, so that fixing the memory output signal does not affect the characteristic. At the same time, the circuit can be configured with only a limited memory space, so that the memory space can be saved.

FIG. 19 shows an implementation example of the count setting circuit. In the figure, 171 is an output terminal, 172 is a switch circuit,
Reference numeral 174 is a logic "1" level output terminal, and 175 is a logic "0" output terminal.

FIG. 20 shows another embodiment of the weight coefficient circuit.
Shown in. In the figure, 176 is an output terminal, 179, 1
Reference numeral 78 is a fixed coefficient storage circuit that outputs one level, 177 is a division circuit, 180 is an adder, 181 is a multiplier, 183 is a delay circuit, and 182 is a fixed coefficient storage circuit that outputs a forgetting coefficient. The circuit in the figure expresses the coefficient related to the lambda in the expression (6) by expanding it, and specifically realizes the sum of the power series related to the forgetting coefficient λ. The VLMS algorithm can greatly simplify the circuit configuration as compared with the RLS algorithm, but as compared with the LMS algorithm, the circuit scale increases because it includes a multiplier for the square of the number of taps as shown in FIG. There was a problem.

[0024]

When a MLSE type equalizer is applied to a burst transmission system in order to compensate for waveform distortion due to a delay that occurs in a transmission line, the RLS algorithm is used in order to realize high burst utilization efficiency. It is necessary to apply an algorithm that can establish high speed synchronization to channel estimation. In addition, in a transmission line such as a mobile transmission line in which the delay profile changes greatly and the optimum sampling phase changes, T
When the space MLSE equalizer is applied, there is a problem that characteristic deterioration occurs due to the sampling phase shift. In order to avoid this problem, there is a configuration in which sampling is performed at M times the symbol frequency and T space equalization of the M sequence is performed to select the sequence that generates the branch metric of the most surviving path. In addition to operating the A / D converter, power consumption increases, and since an independent RLS tap coefficient estimator for M sequences is required, there are significant drawbacks in terms of circuit configuration and power consumption. Further, if M is reduced to reduce the power consumption and the circuit configuration, there is a problem that the sampling phase shift cannot be sufficiently compensated.

On the other hand, the received signal is sampled at a rate not less than twice the Nyquist frequency, passed through a waveform shaping filter which samples the temporary decision value generated at the time of maximum likelihood sequence estimation at the same speed as the received signal, and the RLS at that speed. A configuration for performing tap coefficient estimation has been proposed. When this configuration is applied, there is a problem that the RLS algorithm requires a plurality of sequences or operates at several times the symbol rate, so that the circuit configuration becomes complicated and the power consumption and the circuit scale increase. It was Further, even when the VLMS algorithm is applied, there is a problem that the circuit scale increases because the matrix operation is included inside.

In view of these problems, the present invention uses MLS.
An object of the present invention is to eliminate the influence of sampling phase shift without increasing power consumption and circuit scale in an E-type equalizer.

[0027]

The feature of the present invention for achieving the above object is that the square of the error signal between the received signal sampled at M times the symbol frequency and the estimated value of the received signal is used as the likelihood information. Maximum likelihood sequence estimator for sequence estimation, mapping circuit for inputting each sequence candidate signal and outputting signal at sampling rate of received signal, transmission line estimator for estimating transmission line characteristic from mapping circuit output signal and error signal And an adaptive equalizer composed of a replica generator that outputs the estimated value of the received signal by convolving the transmitted signal candidate sequence with the tap coefficient that is the output signal, the transmission path estimator outputs the mapping circuit output. A gain vector calculator that generates a gain vector by multiplying a vector as an element by a weighting coefficient having an exponential decay characteristic with time, And a correlator that calculates the correlation between the in-vector and the error signal, and a correlator that adds the correlator output signal to the tap coefficient one hour before as the tap coefficient update amount and outputs the addition result as the tap coefficient. The mapping circuit is a delay line filter with a tap that convolves the transmission signal candidate sequence with a vector that is a product of a matrix that diagonalizes the autocorrelation matrix of the waveform shaping filter output and a vector that has the impulse response of the filter as an element. The adaptive equalizer is composed of

Another feature of the present invention is a maximum likelihood sequence estimator for performing sequence estimation using the square of the error signal between the received signal sampled at M times the symbol frequency and the estimated value of the received signal as likelihood information, and An adaptive channel estimator that estimates the channel characteristics from the sequence candidate signal and the error signal, and a replica generator that outputs the estimated value of the received signal by convolving the transmitted signal candidate sequence with the tap coefficient that is the output In the equalizer, the transmission path estimator is a gain circuit for generating a gain vector by multiplying a mapping circuit having the sequence signal candidate as an input and a weighting coefficient having an exponential attenuation characteristic with the output vector with time. A vector calculator, a correlator that finds the correlation between the gain vector and the error signal, and a correlator output signal are added to the tap coefficient one hour before as the update amount of the tap coefficient. And is configured from the integrator to output the addition result as a tap coefficient, the mapping circuit in the inverse matrix R of the autocorrelation matrix of the waveform shaping filter, a matrix for the impulse response of the shaping filter as elements,
The adaptive equalizer includes a delay line filter with a tap that outputs a vector that is a product of a matrix obtained by multiplying the transposed matrices from the left and right, and a vector having the transmission signal candidate as an element.

Still another feature of the present invention is a maximum likelihood sequence estimator for performing sequence estimation using the square of the error signal between the received signal sampled at M times the symbol frequency and the estimated value of the received signal as likelihood information. , A channel estimator that estimates channel characteristics from each sequence candidate signal and error signal, and a replica generator that outputs the estimated value of the received signal by convolving the transmitted signal candidate sequence with the tap coefficient that is the output. In the adaptive equalizer, the transmission path estimator is a mapping circuit that receives the sequence signal candidate as an input, a correlator that obtains a correlation between the output vector and an error signal, and a correlator output signal that updates the tap coefficient. And add it to the tap coefficient one hour before,
The mapping circuit is configured by an integrator that outputs the addition result as a tap coefficient, and the mapping circuit includes a matrix having an impulse response of the waveform shaping filter as an element and an inverse matrix R of the autocorrelation matrix of the waveform shaping filter. The tapped delay that outputs the vector that is the product of this matrix and the vector that has the candidate sequence as an element is stored It is in an adaptive equalizer composed of line filters.

[0030]

[Action]

(1) With respect to claim 1, in the tap coefficient updating formula (5) in the VLMS algorithm, R is an autocorrelation matrix and a symmetric matrix. Therefore, the orthogonal transformation enables diagonalization. That is, the orthogonal transformation matrix U _k can be transformed as shown in the following equation.

[0031] U ^T RU = Λ (8)

In the above equation, Λ is a diagonal matrix whose diagonal elements are the eigenvalues of the correlation matrix R. Here, from the property of the orthogonal transformation matrix, (5) is expressed as shown in the following equation.

[0033]

[Equation 4]

Here, the tap coefficient conversion is defined. That is, if U ^T H _k = W _k is set, (9) and the error function are expressed by the following equation.

[0035]

[Equation 5]

Here, U ^T S _k can be defined as a vector for the transmission signal candidate sequence X _k as follows.

Y _k = U ^T S _k = (U ^T H ^F ) X _k = MX _k (11)

Here, since H ^F is the impulse response of the waveform shaping filter, it is possible to define a matrix M that combines two linear transformations into one as shown in (11). That is,
By convolving the transmission signal candidate sequence with a matrix M instead of the waveform shaping filter, the tap coefficient can be obtained by a simple calculation as shown in the following equation.

[0039]

[Equation 6]

Therefore, by providing a memory for realizing the mapping M, the present algorithm can be realized without a multiplier / adder for matrix operation. Also, since the Λ ⁻¹ matrix of (12.2) is a diagonal matrix, (1−λ) / (1−λ
^The circuit configuration can be reduced by considering the initial value of each vector element of ( ^{k + 1} ) and storing it in the memory.

(2) With regard to claim 2, the above (10.2)
(H ^F ) ^T H _k-1 = V _k-1 . At this time, (9) can be transformed into the following equation.

[0042]

[Equation 7]

[0043] However, it is ^{Q = (H F) T R} -1 H F. At this time, the error function e _k is given by the following equation from (10.2).

[0044]

[Equation 8]

When weighted as described in claim 1 and input to the replica generation circuit, the replica generation circuit must be composed of a multi-bit multiplier and an adder. Since it can be configured by the Exor gate circuit and the adder, there is an advantage that the circuit can be simplified. In particular, when the modulation multi-value number increases and the alphabet size α of the Viterbi algorithm increases, the replica generator needs α times the transmission line estimator. Therefore, simplifying the replica generator significantly reduces the equalizer configuration. Can be simplified.

(3) With respect to claim 3, the coefficient term of the second term on the right side in the above (15), that is, (1-λ) (1-λ
^By storing ^{k + 1} ) ^-1 Q in the memory, the multiplier can be omitted. There is an advantage that an algorithm can be realized at high speed by omitting a circuit having deep logic such as a multiplier.

[0047]

【Example】

(1) The basic configuration of the first embodiment of the present invention is shown in FIG. In the figure, 271 is an input terminal, 272 is a sampler, 273 is a subtractor, 274 is a square circuit, 275 is a maximum likelihood sequence estimator, 276 is a mapping circuit, 277 is an output terminal, 278 is a replica generator, 279 is a transmission line. Estimator,
280 is an integrator, 281 is a correlator, 282 is a gain vector calculator, 283 is a multiplier, and 284 is a weight coefficient circuit.

A specific example of the present invention is shown in FIG. The figure shows an example of the configuration in which the received signal is sampled at a rate twice the symbol rate and the signals are processed in parallel. In the figure,
1 is an input terminal, 2 is an output terminal, 5 and 6 are subtractors, 3 is a maximum likelihood sequence estimator, 4 is a mapping circuit, 7 is a replica generator, 8 is a transmission path estimator, 9 is a switch circuit, and 20 is Serial / parallel converter, 10 T / 2 delay circuit, 11 integrator,
12 is a gain vector calculator, 13 and 14 are correlators, 1
Reference numerals 7 and 18 are multipliers, 19 is a weighting coefficient circuit, 21 and 22 are squaring circuits, 23 is an adder, and 24 is a 1 / T clock input terminal.

The received signal input from the input terminal at twice the symbol rate is S / P converted into a two-series signal by the serial / parallel converter 20. Each signal and switch circuit 9
After the difference from the estimated value of the received signal is obtained by the subtracters 5 and 6, the signal is converted into electric power by the squaring circuit and these two series of signals are added. The maximum likelihood sequence estimator 3 uses this signal as likelihood information to perform sequence estimation.

On the other hand, the temporary decision value sequence generated at the time of estimating the maximum likelihood sequence is input to the mapping circuit 4 to generate a signal sequence in which the autocorrelation matrix sampled at the speed of 2 / T is a diagonal matrix. This signal is input to the replica generator 7 and simultaneously to the tap estimator 8. next,
The replica, which is the estimated value of the received signal, is generated by convolving the transmission path impulse response estimated one time before with the transmission signal candidate sequence input every T / 2. This replica is S / P-converted by a switch circuit, and an error between the replica and the received signal S / P-converted is generated by subtractors 5 and 6. The tap estimator 8 estimates the impulse response of the transmission path from the output signal sequence of the mapping circuit and the output signals of the subtracters 5 and 6.
In the transmission path estimator for impulse response estimation, the error signal e _k from the subtracters 5 and 6 is first multiplied by the coefficient from the weighting coefficient circuit and input to the correlators 13 and 14. The correlator generates a correlation value between the mapping circuit output series signal and the error signal with coefficient, that is, the second term on the right side of (14). A tap coefficient can be generated by inputting each of these vectors into the integrator 11 and integrating them.

FIG. 16 shows an example of the configuration of the mapping circuit, which is composed of a delay line with taps. The input signal outputs a signal weighted and added by a tap coefficient which is an impulse response in which the autocorrelation matrix is diagonalized.

Reference numerals 155a, 156a and 157a are T / 2 delay circuits, 158a, 159a, 160a and 161a are coefficient units, and 163a is an adder.

(2) FIG. 3 shows the basic construction of another embodiment of the present invention. 287 is an input terminal, 292 is a demodulated signal output terminal, 288 is a sampler, 289 is a subtractor, 290 is a squaring circuit, 291 is a maximum likelihood sequence estimator, 286 is a sampling clock input terminal, 293 is a received signal replica generator, 294 is a transmission path estimator, 297 is a mapping circuit,
298 is a gain vector calculator, 301 is a weighting coefficient circuit, 300 is a multiplier, 299 is a vector correlator, 296
Indicates an integrator that integrates the input vector.

FIG. 4 shows a specific example of the present invention. The same figure is shown in FIG.
Similarly to the above, the received signal is sampled at a rate twice the symbol rate, and the sampled signals are processed in parallel. In the figure, 67 is an input terminal, 68 is an output terminal, 71,
72 is a subtractor, 69 is a maximum likelihood sequence estimator, 74 is a replica generator, 75 is a transmission line estimator, 73 and 84 are switch circuits, 76 is a T / 2 delay circuit, 77 is an integrator, and 78 is a gain vector. Arithmetic unit, 79 and 89 correlators, 83 mapping circuits, 80 81 multipliers, 82 weighting coefficient circuits,
85 and 86 are squaring circuits, 87 is an adder, and 88 is a 1 / T clock input terminal.

FIG. 21 shows a configuration example of a replica generation circuit applied to the present invention. In the figure, 206-1 is a signal input terminal from the maximum likelihood sequence estimator, 206-2 is a signal output terminal, 206-3 is a tap coefficient input terminal from the transmission path estimator, 203 is a T / 2 delay circuit, 204 Is the Exor circuit,
Reference numeral 205 denotes an adder circuit. That is, in the configuration of the present invention, the multiplier can be realized in the replica generation circuit by a simple configuration of the Exor circuit, and therefore the circuit configuration can be reduced as compared with the configuration using a normal multiplier.

(3) FIG. 5 shows the basic construction of still another embodiment of the present invention. 207 is a signal input terminal, 209 is a switch circuit, 208 is a subtractor, 210 is an output terminal, 211 is a square circuit, 219 is a maximum likelihood sequence estimator, 212 is a replica generator, 213 is a transmission path estimator, and 214 is a gain. Vector calculator 215, mapping circuit, 216 correlator,
Reference numeral 217 is an integrating circuit for integrating the input vector, and 218 is a sampling clock input terminal.

FIG. 6 shows a specific example of the present invention.

In the same drawing, the same drawing as in FIG. 2 shows an example of the configuration in which the received signal is sampled at a rate twice the symbol rate, and this is processed in parallel. In the figure, 220
Are signal input terminals, 221, 228 are switch circuits, 22
2, 223 are subtraction circuits, 224, 225 are squaring circuits, 2
26 is a maximum likelihood sequence estimator, 227 is a demodulated signal output terminal, 2
29 is a replica generator, 230 is a transmission path estimator, 236
Is a gain vector calculator, 234 and 235 are mapping circuits, 232 and 233 are vector correlators, 231 is an integrator that integrates input vectors, and 237 is a sampling clock input terminal.

FIG. 22 shows a configuration example of the mapping circuit.
In the figure, 195 is an input terminal, 199 is an output terminal, 1
96 to 198 are delay circuits, and 200 to 202 are memory circuits. The input signal vector from the maximum likelihood sequence estimator is input to each memory that realizes vector operations corresponding to impulse responses having different initial phases, and the output of each memory is used as the output vector of the circuit.

Therefore, by using this configuration, the number of multipliers included in the equalizer can be reduced.
There is an advantage that the delay of the circuit is reduced and a higher speed operation of the equalizer can be realized.

[0061]

FIG. 23 shows the BER characteristics of the adaptive MLSE to which the algorithm of the present invention is applied. A two-wave independent Rayleigh fading model is applied to the transmission path model, the delay dispersion is set to 0.1, and the maximum Doppler frequencies normalized by the clock frequency are set to 2.08 × 10 ⁻⁴ and 4.16 × 10 ⁻⁴ . A 16-state Viterbi algorithm was applied to the MLSE, and the number of taps of the replica generator was 4 and μ was 0.05. The figure also shows the theoretical value of quasi-static Rayleigh fading. Despite the delay dispersion of 0.1, the excellent equalization characteristic that the floor error rate can be 10 ⁻⁴ or less is realized.

Next, FIG. 25 shows the fractional VLMS-M.
7 shows a comparison of the circuit scale of the LSE and the algorithm of the present invention. The scale of the algorithm is evaluated by the number of multipliers because the circuit scale of the product-sum operation multiplier is significantly larger than that of the adder. Since the fractional VLMS algorithm has a matrix multiplication in the tap coefficient updating formula, the number of multiplications increases in proportion to the square of the tap coefficient. However, in the present invention, since the matrix multiplication can be eliminated, a linear function for the tap coefficient is used. Since the number of multiplications is only increased, the circuit scale can be reduced. By applying the configuration described in claim 2, the 64 multipliers can be replaced with Exor, so that the circuit configuration can be further simplified. Furthermore, since the number of multipliers can be reduced by using the configuration described in claim 3, the circuit can be simplified and the circuit operation can be speeded up. As shown in FIG. 25, the configuration of the present invention does not deteriorate the transmission line characteristics as compared with the prior art, and as shown in FIG.
There is an advantage that the circuit configuration can be reduced when SI is used.

[Brief description of drawings]

FIG. 1 shows a configuration (1) of the present invention.

FIG. 2 shows a configuration (2) of the present invention.

FIG. 3 shows a configuration (3) of the present invention.

FIG. 4 shows a configuration (4) of the present invention.

FIG. 5 shows a configuration (5) of the present invention.

FIG. 6 shows a configuration (6) of the present invention.

FIG. 7 is an example of a frame format.

FIG. 8 is a configuration example of a sampling phase selection type.

FIG. 9 is a configuration example (1) based on fractional sampling.

FIG. 10 shows a configuration example (1) of a replica generator.

FIG. 11 shows a configuration example of a matrix calculation circuit.

FIG. 12 shows a configuration example of an integrator.

FIG. 13 is an example of a configuration of a maximum likelihood sequence estimator.

FIG. 14 shows a configuration example (2) of a replica generator.

FIG. 15 shows a configuration example (1) of a mapping circuit.

FIG. 16 is a configuration example of a mapping circuit.

FIG. 17 shows a configuration example of a correlator.

FIG. 18 shows a configuration example of a weight coefficient circuit.

FIG. 19 shows an embodiment (1) of the count setting circuit.

FIG. 20 shows a configuration example (2) of a weighting coefficient circuit.

FIG. 21 shows a configuration example (3) of the replica generation circuit.

FIG. 22 shows a configuration example (2) of a mapping circuit.

FIG. 23 shows BER characteristics.

FIG. 24 shows a configuration of a fractional VLMS algorithm.

FIG. 25 shows a comparison of circuit scales.

[Explanation of symbols]

1,25,42,67,75,89,97,100-
1,100-2,105,128,154,162,1
65,184,189,195,206-1,206-
3,207,220,238,271,287 Input terminals 2,26,43,68,80,99,101,106,
153, 164, 170, 171, 176, 193, 1
99, 206-2, 210, 227, 244, 277,
292 output terminals 5, 6, 23, 28, 45, 46, 49, 71, 72,
87, 98, 106-1, 103-2, 110, 12
6,148-151,163,180,214-21
7,225,226,241,266-269,27
3,289 Adder 177 Divider 17,18,80,81,93-96,120-12
3,132-147,158-161,181,185
~ 188,251,300 Multiplier 9, 20, 27, 44, 51, 64, 73, 90, 17
2,173,224,240,288 Switch circuit 7,32,54,74,235,246,278,29
3 Replica Generator 8, 31, 53, 75, 236, 247, 279, 29
4 Channel Estimator 3,41,65,69,227,243,275,29
1 Maximum Likelihood Sequence Estimator 11, 33, 55, 77, 237, 253, 280, 2
96 integrator 12, 78, 236-1, 282 gain vector calculator 35, 57, 60 Kalman gain calculator 36, 58, 61 P matrix calculation circuit 34, 56, 59 tap coefficient update amount calculator 13, 14, 79 , 89, 238, 239, 252, 2
81,299 Correlator 15,16,83,84,250 Matrix operation circuit 4,66,70,228,276 Waveform shaping filter 19,82 Weighting coefficient circuit 21,22,29,47,48,85,86,230 ，
231, 242, 274, 290 Square circuit 38 Address decoder 37, 62, 90-92, 104, 183 T delay circuit 10, 76, 117-119, 129-131, 155
~ 157,195-197 T / 2 delay circuit 112 path metric memory circuit 114 path memory circuit 108 path metric generator 111 comparison / selection circuit 115 selection circuit 152,162,166,218,263 memory circuit 167,264 counter 168 comparison 169 Measuring number setting circuit 174 Logic "1" output terminal 175 Logic "0" output terminal

Claims (3)

[Claims] 1. A maximum likelihood sequence estimator that performs sequence estimation using the square of an error signal between a received signal sampled at M times the symbol frequency and an estimated value of the received signal as likelihood information, and each sequence candidate signal as input. A mapping circuit that outputs a signal at the sampling rate of the received signal, a transmission path estimator that estimates the transmission path characteristics from the mapping circuit output signal and the error signal, and convolution of the transmission signal candidate sequence with the tap coefficient that is the output signal In the adaptive equalizer composed of a replica generator that outputs the estimated value of the received signal at, the transmission path estimator is a weighting coefficient having an exponential attenuation characteristic with time in a vector whose element is the mapping circuit output. A gain vector calculator that generates a gain vector by multiplying by, a correlator that calculates the correlation between the gain vector and the error signal, and a correlation The output signal is added as an update amount of the tap coefficient to the tap coefficient one hour before, and the adder is configured to output the addition result as the tap coefficient. The mapping circuit diagonalizes the autocorrelation matrix of the waveform shaping filter output. An adaptive equalizer comprising a delay line filter with a tap for convoluting the transmission signal candidate sequence with a vector, which is a product of a matrix and a vector having an impulse response of the filter as an element. 2. A maximum likelihood sequence estimator for performing sequence estimation using the square of an error signal between a received signal sampled at M times the symbol frequency and an estimated value of the received signal as likelihood information, and an error between each sequence candidate signal. In a transmission line estimator that estimates the transmission line characteristic from the signal, and an adaptive equalizer that is configured by a replica generator that outputs the estimated value of the reception signal by convolving the transmission signal candidate sequence with the tap coefficient that is the output, The transmission path estimator is a mapping circuit that inputs the sequence signal candidate, and a gain vector calculator that generates a gain vector by multiplying the output vector by a weighting coefficient having an exponential attenuation characteristic with time, A correlator that finds the correlation between the gain vector and the error signal and the correlator output signal are added to the tap coefficient one hour before as the update amount of the tap coefficient, and the addition result is The mapping circuit multiplies the inverse matrix R of the autocorrelation matrix of the waveform shaping filter by the matrix having the impulse response of the waveform shaping filter as an element and its transposed matrix from the left and right respectively. An adaptive equalizer, which is configured by a tapped delay line filter that outputs a vector that is a product of the matrix and a vector having the transmission signal candidate as an element. 3. A maximum likelihood sequence estimator that performs sequence estimation using the square of an error signal between a received signal sampled at M times the symbol frequency and an estimated value of the received signal as likelihood information, and an error between each sequence candidate signal. In a transmission line estimator that estimates the transmission line characteristic from the signal, and an adaptive equalizer that is configured by a replica generator that outputs the estimated value of the reception signal by convolving the transmission signal candidate sequence with the tap coefficient that is the output, The transmission path estimator has a mapping circuit that receives the sequence signal candidate, a correlator that obtains a correlation between the output vector and an error signal, and a tap coefficient that is one hour before using the correlator output signal as an update amount of the tap coefficient. Is added and the addition result is output as a tap coefficient. The mapping circuit adds an inverse matrix R of the autocorrelation matrix of the waveform shaping filter to the waveform The matrix obtained by multiplying the matrix having the pulse response as an element and the transposed matrix from the left and right is multiplied by a weighting coefficient having an exponential decay characteristic with time, and stored. An adaptive equalizer comprising a delay line filter with a tap that outputs a vector that is a product of