JPH07235619A - Low rc multiplexing level interconnection skill for high characteristic integrated circuit - Google Patents

Abstract

PURPOSE: To make an RC interconnection delay smaller than that of a multi- level metallization device, based on aluminum, by combining a free space intermediate level dielectric and a copper metallization. CONSTITUTION: A first flattened intermediate level oxide dielectric (ILD1) 6 is deposited. A mask for a negative image of a hexagonal pattern 1 is used to form a pattern of resist. When aligned silicon nitride is deposited by a CVD process, hexagonal islands surrounded and sealed by the silicon nitride are formed. Grooves are made in the intermediate level oxide dielectric ILD1 by an etching process. Then a copper blanket layer is deposited thereon. The above operation is repeated to sequentially laminate second, third and fourth intermediate level oxide dielectric layers. Metallization based on aluminum deteriorates electrical characteristics due to an RC induced propagation delay of a parasitic resistive element and parasitic capacitive element. However, the use of copper enables reduction in the RC interconnection delay.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The invention relates to low RC multilevel interconnect technology for high performance integrated circuits.

[0002]

2. Description of the Related Art Interconnect parasitic resistance (R) elements and interconnect parasitic capacitance (C) elements are
Semiconductor technology (complementary metal, oxide, semiconductor, ie C
MOS, bipolar, bipolar complementary metal / oxide /
In semiconductors, i.e. BiCMOS), dimensions of less than 0.5 micrometer will be a significant issue. Parasitic resistance and parasitic capacitance elements associated with aluminum-based (or refractory metal-based) metallizations will degrade the electrical properties of the circuit due to their RC-induced propagation delays. Let's do it. In addition, these interconnect parasitics increase overall chip power consumption and increase the amount of signal crosstalk. As a result, consideration and development of suitable low RC multi-level interconnect technology is of paramount importance to advanced semiconductor technology below 0.5 μm for ultra large scale integration (ULSI) device applications.

Low RC high performance interconnect devices require low resistance metal lines or low dielectric constant dielectrics, or preferably both at the same time. Most prior art to date has focused on the development of low resistance metallization devices, with less emphasis on reducing parasitic capacitance. These prior arts include the following technologies. Copper metallization by physical vapor deposition (PVD), chemical vapor deposition (CVD), or non-electrolytic deposition (volume resistivity = 1.7 μΩcm). Gold metallization by non-electrodeposition deposition or other technique. A low temperature aluminum-based metallization device, such as liquid nitrogen temperature (77K) (the resistivity of Al at 77K is less than 1/5 compared to that of Al at 25 ° C). Superconducting transmission line interconnect.

Despite the high circuit characteristics provided by these other metal interconnect devices, room temperature aluminum-based interconnects have been shown to be used for silicon integrated circuits.
Still the main metallization. This is because the process steps for aluminum-based interconnects are well established and mature process steps.

Little has been done in the field of low-k dielectrics for integrated circuit (IC) metallization. Undoped and doped silicon dioxide has been the predominant intermediate level dielectric material used in silicon-based IC technology. Some fast gallium arsenide (GaAs)
The technology used a single level air bridge to reduce the delay due to device interconnections. However, conventional air-bridge technology has been incompatible with advanced silicon technology, with multiple metal interconnect levels and hermetically sealed chip packages.

As a result, there is a need for a low RC high performance interconnect technology that is compatible with standard semiconductor technology and hermetically sealed chip packages and that can be implemented in the manufacturing process. The low RC interconnect technology that can be implemented in the manufacturing process should be readily applicable to advanced semiconductor technologies with multiple (eg, two or more) planarized layers of metal. The overall device fabrication yield and chip reliability must be at least as good as conventional metallization techniques.

[0007]

SUMMARY OF THE INVENTION The present invention allows the creation of a free space void (.epsilon.r = 1) intermediate level dielectric between adjacent metal levels of a multilevel metallization device. The metal wire is aluminum (A
l), tungsten (W), copper (Cu), gold (Au)
It can be made of any suitable conductive metal such as. With the metallization of the present invention,
Excellent mechanical stability and good overall reliability are obtained. The complexity of the manufacturing process is comparable to that of conventional metallization techniques and is compatible with conventional metallization techniques. The process described below is based on using copper metallization made by chemical vapor deposition. However, the multi-level metallization fabrication process of the present invention is fully compatible with any metal material equipment and various metal deposition techniques. Copper is a CMO of 0.5 μm or less
It is the preferred material for S / Bi CMOS and bipolar technologies. It has a low electrical resistivity of copper (aluminum has an electrical resistivity of 2.7 μΩcm,
The electrical resistivity of copper is 1.7 μΩcm). By combining the free space mid-level dielectric of the present invention with copper metallization, the RC interconnect delay is
It can be reduced by (2.7 / 1.7) x 3.9 = 6 times compared with the current aluminum-based multilevel metallization system. It should be noted that the free space mid-level dielectric technique of the present invention has a greater impact on RC value reduction and circuit performance than replacing aluminum with a low resistivity material such as copper.
A simulation of interconnect delays has shown that the lower dielectric constant of the mid-level dielectric improves the circuit performance by far more than the reduction of the metal resistivity. The interconnection technology of the present invention also
Besides reducing the delay associated with interconnect parasitic RC values, it will significantly reduce chip-wide power consumption and signal crosstalk (both interlevel crosstalk and in-plane crosstalk).

[0008]

EXAMPLES Assumptions for the manufacturing process described below are as follows. (1) Copper is used as the metal. (Metals such as aluminum and tungsten can also be used.)

(2) Silicon nitride is used as a passivation / encapsulation layer over copper.

(3) Disposable intermediate level dielectrics (monocrystalline silicon or polycrystalline silicon can also be used as a disposable intermediate level dielectric material) as silicon dioxide (impurized or impure). Is not added, or a combination thereof is used.

(4) Silicon nitride is used as an intermediate level mechanical support material. (Silicon dioxide can also be used for mechanical support if a material such as silicon is used as the disposable intermediate level material.)

(5) This step is carried out by phosphorus silicate glass (PSG) or boron phosphorus silicate glass (BP).
SG) Utilize well-established planarization techniques such as recirculation and / or resist etch back.

The preferred processing steps are as follows: This process step is explained under the assumption that copper is used as the metallic material. (Aluminum-based conductors can be used to perform almost similar processing steps.)

(1) In FIG. 1, a cross-sectional view of the structure resulting from the following processing steps completes device fabrication by transistor level. This structure is metal 0,
It has local interconnects, etc. This structure completes device fabrication prior to the first intermediate level dielectric.

(2) In FIG. 1, a cross-sectional view of the structure resulting from the following processing steps shows a thin (eg, 1000 Å to 2000 Å) layer 2 of silicon nitride (low pressure) on a substrate 4. Chemical vapor deposition LPCV
D, plasma enhanced chemical vapor deposition PECVD, or photochemical deposition). This layer will later act as an etch stop layer to protect the field oxide, oxide spacers, etc.

(3) Still referring to FIG. 1, a first planarized intermediate level oxide dielectric (ILD1) is deposited. This can be either low temperature ECR deposition (in-situ planarization) or resist etch back (REB).
Can be carried out by conventional LPCVD / PECVD. ILD1 has a total thickness of 0.5 μm to 2
Created to be around μm. The next steps are microlithographic processing steps (ie, rotating the resist, preheating the resist, exposing).
And the step of developing).

(4) Use a mask for the negative image of the hexagonal pattern 1 (shown in FIG. 2b) and make a resist in the pattern. (This is
Assuming positive photoresist is used,
Will be a dark field mask. ) Perform alien oxide etching using optical end time detection or temporal end time detection. The underlying nitride layer is used as an etch stop to stop the plasma etch process step. (Adjust overetch based on optical emission end time detection.) Remove photoresist layer. A cross-sectional view of the resulting structure is shown in FIG. ILD
The hexagonal pattern 1 etched in 1 has a unit cell having a diagonal dimension of several microns to several tens of microns. Line width of hexagonal edge (width of groove in oxide)
Can be chosen to be the same as, or somewhat larger than, the minimum device characteristic dimension (eg, 1 μm). A line width smaller than that is preferable.

(5) Aligned silicon nitride deposition is performed using a chemical vapor deposition (CVD) process step or a plasma enhanced chemical vapor deposition (PECVD) process step. One good example is ECR (electron cyclotron resonance) plasma deposition. As shown in FIG.
This will fill the trenches (hexagonal trenches) in the oxide created by etching and leave the nitride 2 on its surface. FIG. 4 is a cross-sectional view of the obtained structure. The resulting structure is a hexagonal island surrounded and encapsulated by silicon nitride.

(6) Using a Metal 1 mask (negative image as shown in FIG. 2b), and after photoresist patterning and trench etching, a cross-sectional view of the resulting structure is shown in FIG. It is shown. The microlithography step uses a negative image of the metal pattern (dark field mask if positive photoresist is used). To create a groove 8 in the intermediate level oxide dielectric ILD1 having a depth of about 0.5 μm to 1 μm,
Perform anisotropic plasma etching. These grooves 8
Will contain the final metal 1 structure. Remove the photoresist.

(7) Perform the microlithography step of hole 1. Hole 1 (metal 1 to metal 0) is used to pattern photoresist. An anisotropic plasma nitride / oxide / nitride etch is performed to open the contact holes. Hole 9 is shown in FIG. FIG. 6 is a cross-sectional view.

(8) As shown in FIG. 6, a matched nucleation / adhesive layer of a suitable material (eg, TiN, Ti, Cr, etc.) is deposited by chemical vapor deposition (CVD) or physical. Deposition by pressure vapor deposition (PVD). The thickness of this layer is about 250 Å to 1000 Å.

(9) FIG. 7 is a cross-sectional view of the structure resulting from subsequent processing steps. As shown in FIG. 7, a blanket layer of copper (resistivity: 1.7 μΩcm) is deposited by CVD or other technique. Deposition is carried out such that the thickness of this deposit is about 0.5 μm or more. This will fill the holes and dielectric trenches and will result in a fairly flat copper surface.

(10) A blanket anisotropic copper etching process using a suitable reactive ion etching (RIE) (eg, high temperature RIE in a chlorine environment) process step or a sputter etching process step. Back is executed. Optical end-time detection (the surface reflectance will change abruptly when the adhesive layer on the flat surface is exposed) is used to ensure that proper over-etching is achieved and the etching process steps are performed. Time is fixed. An anisotropic plasma etch back is then performed to remove the exposed adhesive layer. A selective anisotropic plasma nitride etch is performed to remove the exposed nitride layer from the top surface. FIG. 8 is a drawing of the resulting structure. Instead of a blanket plasma etch back, chemical mechanical polishing can be used to create the metal pattern. This stage of the process results in the formation of a flat structure with 1 metal line and a hole pattern filled with copper 12.

(11) A second intermediate level oxide dielectric (ILD2) is deposited by CVD or PECVD to the required thickness. No further planarization step is necessary. This is because the metal 1 / ILD1 surface is already fairly flat. A low temperature dielectric deposition step with plasma (eg T ≦ 300 ° C.) is preferred. ILD2
PECVD is used to deposit a thin (eg, 1000 Å) layer of silicon nitride.

(12) Steps 4 to 10 are repeated.
However, in this case, a mask for the negative image of hexagonal pattern 2 (shown in Figure 2a) is used.
The metal and hole patterning step must use metal 2 and hole 2 mask (metal 2 to metal 1). Hexagonal pattern 2 is similar to hexagonal pattern 1, but is aligned offset by half the size of the hexagonal unit cell.

(13) Deposit a third intermediate level oxide dielectric (ILD3).

(14) Steps 4 to 10 are repeated.
Use a mask for the negative image of hexagonal pattern 1 (shown in Figure 2b). In addition, the metal and hole patterning step involves the metal 3 and the hole 3 (from metal 3 to metal 2)
You must use a mask.

(15) Deposit a fourth intermediate level oxide dielectric (ILD4).

(16) Steps 4 to 10 are repeated.
Use a mask for the negative image of hexagonal pattern 2 (shown in Figure 2b). In addition, the metal and hole patterning step involves the metal 4 and hole 4 (from metal 4 to metal 3)
You must use a mask. A cross-sectional view of the structure obtained using steps 11-16 is shown in FIG. This cross section is for any metal and hole layout design pattern.

(17) Perform a temporal wet HF oxide etching treatment step or a vapor phase HF oxide etching treatment step. This allows selective selection of all mid-level oxide dielectrics in the multi-level interconnect structure without removing the hexagonal nitride support structure and without damaging the multi-level metal structure. Will be removed. 10 and 11 are simplified views showing a cross section of a structure created by the process steps. 10 is a cross sectional view taken along the line AA shown in FIG. 2b, and FIG. 11 is a cross sectional view taken along the line BB shown in FIG. 2b.

Another process step for multi-level metallization is as follows. In the following, further processing steps for multi-level metallization are disclosed. 12-23 are sequential cross-sectional views of structures obtained by sequential process steps. Figure 1
Corresponding symbols are used for the elements throughout 2 to FIG.

(1) Complete device fabrication down to the transistor level (assuming process steps for CMOS devices with silicided gate and source / drain regions). This process can use conventional transistor level silicide interconnects, and silicide local interconnects, or metal nitride local interconnects.

(2) Deposit a layer of silicon nitride 2 (eg, 1000 angstroms to 2000 angstroms), preferably by a plasma enhanced chemical vapor deposition (PECVD) process or a photochemical process. A buffer layer of silicon dioxide (lower layer) for stress relief can be used prior to this nitride deposition. amorphous·
An optional layer of silicon or polysilicon (about 1000 Å) can also be deposited on the nitride (etch stop).

(3) LPCVD and / or PEC
VD allows for interlevel oxide dielectric (doped or undoped, PSG / B
PSG, etc.) 6 is deposited. If necessary, use glass reflux and / or resist etch back to planarize the surface (about 1 μm oxide).
The resulting structure is shown in FIG. The next stage is the microlithographic patterning stage.

(4) Use a mask for the negative image of "Hexagonal Pattern 1" (shown in Figures 2b and 2b1). The size of the hexagonal unit cell diameter is
It can be in the range of about a few microns to about a few tens of microns. The hexagonal line width is the smallest characteristic dimension (for example, 0.
It can be chosen to be as small as 0.35 μm to 1 μm) for the 35 μm technology and as large as several times this minimum characteristic dimension. A small hexagonal line width is preferred. Then it is exposed and the resist is developed.

(5) Perform anisotropic plasma oxide etching. Stop at the bottom etch stop layer (nitride layer or silicon / nitride double layer). Remove the resist. This results in vertical trenches surrounding the hexagonal oxide islands having a hexagonal unit cell pattern, as shown in Figure 2b.

(6) Low pressure chemical vapor deposition of nitride (LP
CVD) (aligned PECV such as remote plasma deposition
D-nitride can also be used). The thickness of the deposited nitride is at least 1 / the width of the hexagonal groove.
Make it larger than 2. This will completely fill the vertical mid-level trench with silicon nitride. Furthermore, the nitride layer covers the entire flat surface. For example, 0.
For 50 μm wide trenches, 3000 Å of nitride can be deposited to completely fill the vertical trenches around the intermediate level oxide islands. The next process steps are microlithography and patterning.

(7) Use hole mask (metal 1 to metal 0) and pattern photoresist. A plasma oxide etch is performed to open a hole (also called a hole) 9 in the lower Si3 N4 which acts as an etch stop. See Figure 16.

(8) Deposit a thin (about 250 angstroms to 500 angstroms) nitride layer 20.
In order to remove this nitride from the bottom of the open hole, RI
Perform E (Reactive Ion Etching). This etch will remove some of this nitride from the upper surface, but will leave at least about 1000 angstroms (even with a 50% to 100% overetch). This nitride will remain on the sidewalls of the hole and will encapsulate the plug of the hole. See FIG.

(9) CVD or physical vapor deposition (P
VD) deposits a nucleation and adhesion layer 10 such as TiN or pure titanium (Ti). See FIG.

(10) Deposit a blanket layer 12 of copper by CVD. This layer fills the holes and forms a blanket layer (eg, 6000 Å) on the flat surface.

(11) A layer of silicon nitride (about 2500 angstroms) by LPCVD or PECVD.
Deposit. This layer will act as the upper encapsulation / passivation layer.

(12) Using metal 1 mask, pattern photoresist and etch pattern in top nitride layer. Silane / ammonia /
This pattern is transferred to copper by anisotropic etching using a process such as high temperature (about 250 ° C.) RIE in chlorine plasma. Continue etching through the lower layer of adhesive (TiN) by a suitable etching step. This etching is continued until the exposed nitride layer is removed from the bottom surface. This will still leave some nitride on the metal lines.

(13) Perform a consistent deposition of silicon nitride 14 (about 250 angstroms to 500 angstroms) by LPCVD or PECVD nitriding process. Then, a RIE process step is performed to remove excess silicon nitride from the bottom flat surface. Thereby, the copper interconnect line is completely encapsulated with silicon nitride.

(14) Second intermediate level oxide (ILD
1) 15 is deposited, and planarization is performed when necessary by resist etch back or other technique.

(15) Go to Step 4. However, in this case, for the lower level hexagonal pattern 1 (displaced by half the size of the unit cell), we have the hexagonal unit cells in offset positions (see FIGS. 2b and 2b ¹⁾ . Use a mask for the negative image of hexagonal pattern 2 (as shown).

(16) Perform the same steps as described in steps 5 to 13 using hole 2 and metal 2 mask. These steps will create metal 1 to metal 2 and metal 2 interconnects through the plugs.

(17) Repeat step 4 with mask for negative image of hexagonal pattern 1. Then step 16 is repeated using hole 3 and metal 3 mask. This will create a metal 3 to metal 2 interconnect and a metal 3 interconnect through the plug.

(18) Repeat step 4 with mask for negative image of hexagonal pattern 2. Then step 16 is repeated using holes 4 and a metal 4 mask. This will create a metal 4 to metal 3 interconnect and a metal 4 interconnect through the plug. In this example, metal 4 is the last interconnect level in the multiple interconnect device.

(19) A wet or vapor phase HF oxide removing step is performed. This will remove all intermediate level oxide dielectric layers in the entire multilevel interconnect structure. This etching step performs a highly selective oxide removal and will remove very little for exposed nitride structures. As a result of this step, the multilevel copper interconnect structure is fully encapsulated (with silicon nitride encapsulation). The interconnect structure is mechanically supported by a multi-level hexagonal silicon nitride cell. The mid-level dielectric is free space.
10 and 11 are cross-sectional views of the structure created by the process steps.

It is noted that the last step does not damage or remove any exposed material layers other than the intermediate level oxide dielectric. The transistor level, including the field oxide, is protected by the nitride layer remaining on the active device.

Passivated continuous coating of silicon nitride
Making a Sealed Chip Package The formation of a passivated cover layer and the making of a sealed package of chips were also performed using the free space dielectric multilevel interconnect technology of the present invention. As a result, 2
One simple technique is disclosed for making a passivated continuous coating of silicon nitride or silicon oxynitride in either of the two manufacturing steps. This passivation cover layer is needed to create the bond pad openings and to protect the chip from the environment and from sources of contamination. This process module is added to the original interconnect manufacturing process or the final wet or vapor phase H 2
In addition to the simplified / preferred process before the F process step. The protective coating (PO) layer is created, the pad openings are created, and the hermetically sealed package is created as follows.

(A) Deposit a relatively thick (0.5 μm to 1 μm) layer of silicon nitride (or silicon oxynitride, preferably nitride) by LPCVD or PECVD (preferably low temperature PECVD). This is
It is performed after the creation of the topmost metal level (after step 18 / before step 19 in another step, after step 16 of the first step and before step 17).

(B) P. O. Microlithography
A mask is used and photoresist is patterned to open areas corresponding to the bond pads and also a grid-like structure similar to the structure shown in FIG. FIG. 24 is a plan view of a grid for a nitride cladding layer overlying a hexagonal nitride support structure prior to the passivation cladding sealing step. The openings in this lattice structure have the smallest dimensions (eg 0.35 μm for 0.35 μm technology). For simplicity, it is assumed that the lines and spaces all have the smallest characteristic dimension (0.35 × 0.35 μm ² grid square). The pattern is then patterned from photoresist to nitride P. O. An anisotropic nitride etch is performed to transfer to the layer. Remove the photoresist. This is because the hexagonal cell area is much larger than the grid cell area.

(C) A wet or vapor phase temporal HF etching process step (the above-mentioned step 17 of the original step and step 19 of another step) is executed. By this,
Without damaging the nitride structure (hexagonal array beam, patterned top nitride, etc.)
And will remove the interlevel oxide dielectric from the entire multilevel metal structure without damaging the metal structure. The lattice structure on top of the nitride allows full etching of all ILD layers. The structure after etching is mechanically stable enough.

(D) Perform a consistent (preferably low temperature) deposition of silicon nitride by LPCVD or PECVD (eg, ECR plasma deposition). This layer can also be oxynitride. By adjusting the deposition time, the thickness is made greater than half the thickness of the grating opening (0.2 μm thickness for 0.35 μm grating opening). This conformal deposition results in a matched nitride or oxynitride conformal thin passivation coating (about 0.2 μm thick) over the entire multilevel metal structure including metal lines and hole plugs.
m) will be created. It also has a top P.D. due to aligned sidewall deposition. O. Completely seal the nitride lattice opening. A thin layer of nitride (~ 0.2 μm) is also deposited on top of the top planar surface, including exposed bond pads.

(E) A timed isotropic blanket plasma nitride etch is performed to remove approximately 0.2 μm to 0.3 μm of silicon nitride. This re-exposes the bond pad, but P. O.
The nitride layer will not be removed. P. O. Of nitride
Only 0.2 μm to 0.3 μm will be removed. As a result, a 0.5 [mu] m-1 [mu] m nitride layer (fully encapsulated) will remain (excluding the bond pads) on top of the entire structure.

(F) Connect the bonding pads.

(G) Proceed to the step of manufacturing a hermetically packaged chip. This step can be carried out in a controlled atmosphere such as air or nitrogen. The space, or gap, in the multilevel metal structure can be filled with a suitable gas at 1 atmosphere, or at low pressure, or at least 1 atmosphere (having a high breakdown electric field).

The following points should be noted. (1) This process is carried out in the uppermost P. O. No additional mask is used to complete the process of sealing the nitride. P. O. The mask also includes P.I. O. Used to create a grid structure on a layer. The grid is initially used to perform a selective oxide removal process, and the grid is finally sealed by another matched nitride deposition process.

(2) Breakdown of gas. The structure must be designed to prevent free space gas breakdown between the metal layers in the structure. The dielectric breakdown of 1 atmosphere of air is about 31
It is kV / cm (3.1V / μm). At 1 atm
The dielectric breakdown of CO2 is 1.2 times that of air. For N ₂ , this magnification is
It is 1.16. The dielectric strength of a gas increases with increasing pressure. At 2 to 3 atmospheres, the dielectric strength of N ₂ is
It is about 1.15 times the dielectric strength of air. As a result, the preferred method for hermetic packaging is to perform the packaging in a high pressure controlled N ₂ atmosphere. This pressure can be in the range of 1 atm to 5 atm (or higher pressure). This prevents micro-discharge in multi-level metal structures with N ₂ filled spaces.

In a multilevel metal structure, it is not preferred to use a near-vacuum state as the free space dielectric. This is because field-induced electron emission can occur in chips that are packaged in a vacuum. However, at high vacuums it is possible to obtain dielectric breakdown fields as high as 5.4 MV / cm. (Beyond this electric field, tunneling breakdown will occur.)

Therefore, the preferred choice of free space dielectric medium is as follows. (1) A high-pressure (for example, 1 atm to 5 atm) medium of nitrogen. (2) High vacuum (P ≦ 10 ⁻⁶ Torr) medium.

If these conditions are taken into account, the breakdown of the gas in this metal structure will be no problem.

Although the present invention has been described in detail with reference to preferred and certain modified embodiments, these are for illustration purposes only and mean that the invention is limited to these embodiments. Not a thing. Various modifications to the details of these embodiments of the invention, as well as other embodiments of the invention, will be apparent or readily devised by those skilled in the art upon reference to the above description. Could be All such modifications and other embodiments are intended to be included within the scope of the present invention.

With respect to the above description, the following items will be further disclosed. (1) (a) creating a plurality of processable dielectric islands in a repeating pattern between conductor levels; and (b) surrounding the islands with a material for mechanically supporting them. (C) selectively removing the disposable dielectric islands and leaving the mechanical support structure to create a free space intermediate level dielectric; and (d) Staggering the pattern for each successive layer of the first dielectric material and repeating steps (a)-(c) a predetermined number of times;
(E) selectively etching and removing the first dielectric material; and a structure for forming a multi-level metallization device on an integrated circuit fabricated on a substrate. Processing steps.

(2) In the processing step described in item 1,
The processing step, wherein each of the islands has a hexagonal shape.

(3) In the processing step described in item 1,
The processing step, wherein the substrate is selected from the group of semiconductor materials including silicon, gallium arsenide, and germanium.

(4) In the processing step described in item 1,
The processing step further comprising disposing a passivation coating layer on the substrate.

(5) In the processing step described in item 4,
(B) disposing a layer of a third dielectric material adjacent to the last created metallization layer; and (b) a grid substrate position in the third dielectric material. Etching a region in the third dielectric material according to a pattern of a mask so as to etch a region corresponding to the contact pad and a region corresponding to the bond pad location;
(C) selectively etching the first dielectric material; (d) placing a matching layer over the structure created by the processing steps; and sealing the grating openings. And (e) etching the matching layer to remove the matching layer from the bond pad.

(6) In the processing step described in item 5,
(A) connecting the bond pad to a conductor,
(B) producing a sealed package in a controlled atmosphere selected from the group including air, nitrogen, and vacuum.

(7) In the processing step described in item 1,
Prior to step (d), the processing step wherein the patterned metal layer is provided in etched trenches and in holes of the first dielectric material.

(8) In the processing step described in item 1,
Prior to step (d), the processing step, wherein the patterned metal layer is provided adjacent to the substantially planar surface of the first dielectric material.

(9) In the processing step described in item 1,
The processing step, wherein the metal layer is selected from the group including copper, aluminum, tungsten, and alloys thereof.

(10) In the processing step according to item 1, the adhesive layer is disposed adjacent to the metal layer.

(11) Having a plurality of active devices adjacent to a honeycomb structure having a metal layer held by a dielectric material, said metal and dielectric materials both carrying air, nitrogen, and vacuum. A multi-level metallization structure sealed in an atmosphere selected from a group of containing.

(12) Advanced sub-0.5 micron semiconductor technology discloses high performance "low RC" multilevel interconnect technology. The disclosed structure and its manufacturing method have a number of important features: (1) various metal devices (A).
l, Cu, W, etc.), (2) use of free-space intermediate-level dielectrics, (3) compatible with standard semiconductor manufacturing processes, (4) excellent mechanical stability And (5) compatible with the chip hermetic packaging technology. Compared to traditional aluminum-based interconnect technologies, this new interconnect technology
The "C" delay can be reduced by a factor of 6. The disclosed interconnect technology provides improvements in key chip characteristics such as low power consumption and high operating frequency. This technology
It is based on manufacturing processes for manufacturing multilevel interconnects with free space dielectrics, and scalable technology.

This application is based on Maildard M. et al. Mosley name
It is a continuation application of application serial number 07 / 816,456 of the title "advanced low RC multi-level interconnection technology for high performance integrated circuits" which was accepted on December 31, 1991.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of an exemplary semiconductor structure manufactured by the process steps of the present invention.

FIG. 2a is a cross-sectional view of an exemplary semiconductor structure manufactured by the process steps of the present invention. b is a diagram of two superimposed hexagonal mask patterns used in the fabrication of hexagonal nitride support structures that separate different metal interconnect levels.

FIG. 3 is a cross-sectional view of an exemplary semiconductor structure manufactured according to the process steps of the present invention.

FIG. 4 is a cross-sectional view of an exemplary semiconductor structure manufactured by the process steps of the present invention.

FIG. 5 is a cross-sectional view of an exemplary semiconductor structure manufactured by the process steps of the present invention.

FIG. 6 is a cross-sectional view of an exemplary semiconductor structure manufactured by the process steps of the present invention.

FIG. 7 is a cross-sectional view of an exemplary semiconductor structure manufactured by the process steps of the present invention.

FIG. 8 is a cross-sectional view of an exemplary semiconductor structure manufactured according to the process steps of the present invention.

FIG. 9 is a cross-sectional view of an exemplary semiconductor structure manufactured by the process steps of the present invention.

FIG. 10 is a schematic representation of a cross section of a device structure made by the process steps of the present invention.

FIG. 11 is a schematic representation of a cross section of a device structure made by the process steps of the present invention.

FIG. 12 is a cross-sectional view of an exemplary semiconductor structure manufactured by the process steps of the present invention.

FIG. 13 is a cross-sectional view of an exemplary semiconductor structure manufactured by the process steps of the present invention.

FIG. 14 is a cross-sectional view of an exemplary semiconductor structure manufactured by the process steps of the present invention.

FIG. 15 is a cross-sectional view of an exemplary semiconductor structure manufactured according to the processing steps of the present invention.

FIG. 16 is a cross-sectional view of an exemplary semiconductor structure manufactured according to the process steps of the present invention.

FIG. 17 is a cross-sectional view of an exemplary semiconductor structure manufactured by the process steps of the present invention.

FIG. 18 is a cross-sectional view of an exemplary semiconductor structure manufactured by the process steps of the present invention.

FIG. 19 is a cross-sectional view of an exemplary semiconductor structure manufactured according to the processing steps of the present invention.

FIG. 20 is a cross-sectional view of an exemplary semiconductor structure manufactured by the process steps of the present invention.

FIG. 21 is a cross-sectional view of an exemplary semiconductor structure manufactured according to the processing steps of the present invention.

FIG. 22 is a cross-sectional view of an exemplary semiconductor structure manufactured according to the processing steps of the present invention.

FIG. 23 is a cross-sectional view of an exemplary semiconductor structure manufactured according to the processing steps of the present invention.

FIG. 24: Plane of a grid pattern for a nitride or oxynitride passivation overlay superimposed on top of a hexagonal nitride support structure prior to the passivation overlay sealing step. Fig.

FIG. 25: Plane of a lattice pattern for a nitride or oxynitride passivation overlay overlying the top of a hexagonal nitride support structure prior to the passivation overlay sealing step. Fig.

[Explanation of Codes] 2 Silicon Nitride 4 Substrate 6 Oxide Derivative 8 Groove 9 Hole 10 Adhesive Layer 12 Bufunket Layer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H01L 27/06 9170-4M H01L 27/06 321 Z

Claims (2)

[Claims] 1. A step of forming a plurality of processable dielectric islands in a repeating pattern between conductor levels, and (b) a material for mechanically supporting the islands. And (c) selectively removing the disposable dielectric islands to create a free space intermediate level dielectric and leaving the mechanical support structure. ) Staggering the pattern of each successive layer of the first dielectric material and repeating steps (a)-(c) a predetermined number of times;
(E) selectively etching and removing the first dielectric material; and a structure for forming a multi-level metallization device on an integrated circuit fabricated on a substrate, Processing steps. 2. A plurality of active devices adjacent a honeycomb structure having a metal layer held by a dielectric material, the metal and dielectric materials both including air, nitrogen, and vacuum. A multi-level metallization structure that is hermetically sealed in a selected atmosphere.