JPH07234817A - Address converting method - Google Patents

Abstract

PURPOSE:To reduce the generation of a TLB miss by performing address conversion for the periphery of one page when the address of the page is converted, and storing peripheral page conversion table information in a TLB. CONSTITUTION:Once an acknowledgement signal 11 is asserted, a TLB (conversion index buffer mechanism) access signal 12 is asserted for two cycles and TLB indexing is carried out for an (n)th page. In the address converting process stage for the (n)th page, the conversion table information on its peripheral page is stored in the TLB unless the conversion table of pages in the periphery of the (n)th page is stored in the TLB. When the address conversion of a peripheral page becomes necessary in the near future, the conversion table information obtained by the address conversion of the peripheral page need not be transferred from a main storage and stored in the TLB to enable speedy processing. In this case, an (n+1)th page is specially selected as the peripheral page.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to dynamic address translation by the page address method and translation index buffer mechanism (Tran).
slation Lookaside Buffer:
Hereinafter referred to as TLB).

[0002]

2. Description of the Related Art In a conventional ordinary computer,
Many virtual memory systems are used. In a computer adopting such a virtual memory system, when the processing device accesses the data stored in the main memory,
Access is performed using a predetermined logical address separately from an address (hereinafter, referred to as a real address) indicating the location of the data in the main memory. Therefore, a means for converting this logical address into a real address is generally required.

Further, in the multiple virtual memory system, a plurality of address spaces are provided and only one job exists in one virtual space. Therefore, in this multiple virtual storage system, as many virtual spaces as the number of jobs that operate simultaneously are prepared. Then, the process of associating the address of the virtual space with the real address is performed for each virtual space. The result of such association is stored in the address conversion table on the main memory managed by the operating system.

In a computer having such address conversion means, in order to speed up the conversion, so-called TLB (Translation Lookas) is used.
ide Buffer) is provided.

FIG. 5 is a block diagram of a general address conversion part in a processor of a computer system using the virtual memory system having the TLB. As shown in FIG. 5, the logical address that is the target of address translation is stored in the logical address register 2 via the logical address bus 1. At the same time as this storage, a TLB entry is determined by using a part of the bits of the logical address, and the TLB 5 is indexed based on this entry. In the example shown in FIG. 5, 6 to 19 bits are used for indexing in TLB5.
The TLB 5 outputs the conversion information by performing this index. This conversion information is compared with a predetermined bit in the logical address in the comparison circuit 6. In the example shown in FIG. 5, 1 to 14 bits of the logical address are compared with this conversion information.

As a result of this comparison, if they match, this state is called a "TLB hit", and if they do not match, this state is called a "TLB miss". In the case of a TLB hit, the data in the TLB 5 is used as the upper bits of the real address, the lower bit of the logical address is used as the lower bit of the real address, and the real address register 7 is used.
Stored in. In this way, the real address register 7
The real address stored in is output to the real address bus 8. On the other hand, as a result of the comparison, if the TLB miss is detected, the TLB 5 is not used, the conversion table information is fetched from the main memory (not shown), and the conversion table information is transferred via the data bus 3 to the data register 4. To store. Then, the conversion table information stored in the data register 4 is stored in the TLB 5. As a result, the address conversion by the TLB 5 is performed from the next memory access.

As described above, when an instruction is executed in the computer, whether or not the conversion table information corresponding to the address where the corresponding instruction or operand is stored is already stored in the TLB 5 before the execution. It is checked, and if it is stored in the TLB 5, the address conversion is performed as described above using the conversion table information in the TLB 5. On the other hand, if the conversion table information related to the TLB5 is not stored, the conversion table information stored in the main memory is fetched, the address conversion is performed using the conversion table information, and the conversion table information is stored in the TLB5. Store in.

FIG. 6 shows a time chart for explaining an example of the conventional address conversion operation. The time chart shown in FIG. 6 is a time chart of main signals by conventional address conversion using a two-stage page address conversion method in a two-phase clock type computer system.

First, when an instruction request signal 10 is asserted in order to execute an instruction, internal processing is busy.
Otherwise, the acknowledge signal 11 is asserted.
Immediately after the acknowledge signal 11 is asserted, the TLB access signal 12 executes the index in the TLB. The result of this indexing is reported by the TLB hit signal 13 or TLB miss signal 14. The time chart shown in FIG. 6 shows an example in the case of a TLB miss, and the TLB miss signal 14 is asserted as shown in the figure. This TLB
The assertion of the miss signal reveals that the translation table information must be fetched from main memory. Therefore, the address translation in progress signal 15 is asserted and the translation table fetch request signal 16 is asserted. When the bus transfer priority is accepted by asserting the conversion table fetch request signal 16 (that is, when the bus usage right is given), the bus transfer priority acknowledge signal 17 is asserted. This allows STE, PTE or KEY on the data bus.
Is started, and the bus transfer end signal 18 is asserted to end the transfer of STE, PTE or KEY. The type of data flowing on the data bus is ST
The determination is made by asserting any of the E fetch signal 19, the PTE fetch signal 20, and the KEY fetch signal 21.

The basic address conversion method is described in detail in Setsuo Osuga, Hideaki Chikaya, "Knowledge of Hardware", Ohmsha.

[0011]

As described above, in the conventional information processing apparatus, address translation for an arbitrary page is performed only when the page is actually used. Further, when a TLB miss occurs during address translation and the translation table information of that address is fetched from the main memory and stored in the TLB, the main memory used for fetching and the TLB are A certain waiting time is required until the priority of the bus in between can be taken. As described above, there is a problem that the overhead time preceding the actual processing becomes large and the performance of the instruction processing deteriorates. On the other hand, as shown in the period T in FIG. 6, there is a problem that internal processing and paths are in an idle state until the next instruction is requested, resulting in poor efficiency.

The present invention has been made in view of the above problems, and an object thereof is to reduce the overhead of address translation when the address translation is performed after the page is actually used, and the address translation is performed. Is to improve the instruction processing performance.

[0013]

In order to solve the above-mentioned problems, the first aspect of the present invention includes first address conversion means for performing address conversion by a page address conversion method using an address conversion table on a main memory, An address on a computer having a second address translation unit that performs address translation faster than the first address translation unit by using a translation index buffering mechanism that stores a table of some pages of the address translation table. In the translation method, when the address to be translated is included in the page stored in the translation index buffer mechanism, a first address translation step of performing address translation by the second address translation means, If the address of interest is not included in the page stored in the translation lookaside buffer, then the first The address conversion means reads a table of pages required for address conversion from the address conversion table on the main memory, performs address conversion using the read page table, and converts the read page table into the conversion. A second address translation step of storing in the index buffer mechanism, which is a step that is subsequently executed after the first address translation step or the second address translation step, wherein the address to be translated is It is checked whether or not the n + 1 page adjacent to the included n page is stored in the conversion index buffering mechanism. If the result of this check is that it is not stored, the table of the n + 1 page is stored in the main memory. Storing and storing in the conversion index buffering mechanism. It is a scan conversion method.

In order to solve the above-mentioned problems, the second aspect of the present invention includes a first address translation means for performing address translation by a page address translation method using an address translation table on a main memory, and an address translation table. An address translation method on a computer having a second address translation unit that performs address translation faster than the first address translation unit using a translation index buffering mechanism that stores a table of pages When the address that is included in the page stored in the translation index buffer mechanism, the first address translation step of performing address translation by the second address translation unit, and the address that is the translation target, If not included in the page stored in the translation index buffer mechanism, the first address translation means , A page table necessary for address conversion is read from the address conversion table in the main memory, address conversion is performed using the read page table, and the read page table is used as the conversion index buffer mechanism. A second address translation step of storing, a step that is executed subsequent to the first address translation step or the second address translation step, the n pages including the address to be translated. It is checked whether or not an n-1 page adjacent to is stored in the conversion index buffer mechanism. If the result of this check is that it is not stored, the table of the n-1 page is stored in the main memory. A storage step of reading and storing in the translation index buffering mechanism. .

In order to solve the above problems, a third aspect of the present invention includes a first address conversion means for performing address conversion by a page address conversion method using an address conversion table on a main memory, and the address conversion table. An address translation method on a computer having a second address translation unit that performs address translation faster than the first address translation unit using a translation index buffering mechanism that stores a table of pages When the address that is included in the page stored in the translation index buffer mechanism, the first address translation step of performing address translation by the second address translation unit, and the address that is the translation target, If not included in the page stored in the translation index buffer mechanism, the first address translation means , A page table necessary for address conversion is read from the address conversion table in the main memory, address conversion is performed using the read page table, and the read page table is used as the conversion index buffer mechanism. A second address translation step of storing, which is a step that is executed subsequently to the first address translation step or the second address translation step, wherein the address to be translated is In the determining step of determining the position within the included n page, and in the determining step, the address to be converted is within the n page,
When it is determined that the page exists in the second half, n + 1 pages are
It is checked whether or not it is stored in the conversion index buffering mechanism. If the result of this check is that it is not stored, then n
A next page storing step of reading a + 1-page table from the main memory and storing it in the conversion index buffer mechanism;
In the determination step, if it is determined that the address to be translated exists in the first half of the n pages, it is checked whether or not n−1 pages are stored in the translation index buffer mechanism, If the result of this check is that it is not stored, a step of storing the previous page for reading the table of the n−1 page from the main memory and storing it in the translation index buffering mechanism is included. Is the way.

In order to solve the above-mentioned problems, a fourth aspect of the present invention is the address translation method of the first aspect of the present invention, wherein the storing step continues after the first address translation step or the second address translation step. Is executed to check whether or not n pages including the address to be translated are stored in the translation index buffering mechanism for pages in the direction of n + 1 page, and finds an unstored page. Up to the step of checking, when a page not stored in the conversion index buffer mechanism is found, a table of the page is read from the main memory and stored in the conversion index buffer mechanism. This is the address translation method.

In order to solve the above-mentioned problems, the fifth aspect of the present invention is the address translation method of the second aspect of the present invention, wherein the storing step continues after the first address translation step or the second address translation step. Executed, and sequentially checks whether or not n pages including the address to be translated are stored in the translation index buffer mechanism with respect to pages in the n−1 page direction, and unstored pages Is found until a page not found in the conversion index buffer is found, the table of the page is read from the main memory and stored in the conversion index buffer. The address translation method is characterized by.

In order to solve the above-mentioned problems, a sixth aspect of the present invention is the address translation method of the third aspect of the present invention, wherein the next page storing step is the first address translation step or the second address translation step. Subsequent execution is performed to sequentially check whether or not the page preceding the n-th page containing the address to be translated is stored in the translation index buffer mechanism, and checks until an unstored page is found. And a page not stored in the conversion index buffer mechanism is found, the table of the page is read from the main memory, stored in the conversion index buffer mechanism, and stored in the previous page. A step is executed after the first address translation step or the second address translation step, and A page after the n-th page containing the address to be stored is sequentially checked whether or not it is stored in the conversion index buffering mechanism, and a check is performed until an unstored page is found. When a page not stored in the buffer mechanism is found, the table of the page is read from the main memory and stored in the translation index buffer mechanism.

In order to solve the above problems, a seventh aspect of the present invention is the address translation method of the first or second or third or fourth or fifth or sixth aspect of the present invention, wherein the storing step or the previous page storing is performed. When a request for address conversion of another page is made during execution of the process in the step or the next page storing step, the process in the storing step, the previous page storing step or the next page storing step is stopped, and the other This is an address conversion method characterized in that page address conversion is executed.

[0020]

From the first aspect of the present invention to the third aspect of the present invention,
When the translation table of the peripheral page of the n-th page is not stored in the translation index buffer mechanism in the address translation processing stage for the n-th page, the translation table information of the peripheral page is stored in the translation index buffer mechanism. Therefore, when the address conversion of the peripheral page is required in the near future, it is not necessary to transfer and store the conversion table information by the address conversion of the peripheral page from the main memory to the conversion index buffer mechanism, which enables quick processing. Become.

In particular, the first aspect of the present invention selects the (n + 1) th page as the peripheral page, and the second aspect of the present invention selects the (n-1) th page as the peripheral page.

Further, according to the third aspect of the present invention, whether or not the logical address that has caused the address translation for the nth page exists as the peripheral page in the n-1 page direction of the nth page or in the n + 1 page direction. Either the (n-1) th page or the (n + 1) th page is automatically selected as the peripheral page, depending on whether to perform it.

Further, in the fourth to sixth inventions, a page which is a peripheral page of the nth page and whose conversion table is not stored in the conversion index buffering mechanism is searched for, and this page is searched. Store the translation table in the translation lookaside buffer. The directions for searching pages correspond to the fourth invention to the sixth invention, and the first invention to the third invention, respectively.

In the seventh aspect of the present invention, in the first to sixth aspects of the present invention, the process of storing the conversion table for the middle page in the conversion index buffer mechanism causes memory access to other pages. In some cases it will be discontinued. Therefore, the execution of the processing of the program is not kept waiting.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings.

Example 1.1 This example 1.1 is a preferred example of the first aspect of the present invention. FIG. 1 shows a time chart of main signals at the time of address conversion in the computer system according to the present embodiment 1.1.

The computer system according to this embodiment is a two-phase clock type computer system and employs a two-stage page address conversion system.

First, when there is an instruction request for address A belonging to the nth page, the instruction request signal 10 is asserted. At this time, if the internal processing is not Busy, the acknowledge signal 11 is asserted and the internal processing is started. Immediately after the acknowledge signal 11 is asserted, the TLB access signal 12 is asserted for two cycles. By asserting the TLB access signal in the first cycle, the n-th page TLB index is executed. The result of this TLB index is reported as TLB hit signal 13 or TLB miss signal 14. In the example shown in FIG. 1, TL
An example of the case where a B mistake occurs is described. Therefore, the TLB miss signal 14 is asserted, and the conversion table information needs to be fetched from the main memory.

In order to fetch the conversion table information from the main memory, the address conversion in progress signal 15 is asserted and the conversion table fetch request signal 16 is asserted. When the bus transfer priority is accepted by asserting this signal, the bus transfer priority acknowledge signal 17 is asserted, and the transfer of STE, PTE or KEY on the data bus is started. Then, by asserting the bus transfer end signal 18, STE, PTE, or KEY
Transfer is completed. Further, similar to the conventional operation described above, the STE fetch signal 19 and the PTE fetch signal 20
Alternatively, it is indicated by asserting one of the KEY fetch signals 21.

On the other hand, by asserting the acknowledge signal 11, the content 22 of the page holding register is changed to the (n +) th.
Since the information of the first page is held and the TLB access signal 12 of the second cycle is asserted, the index for the (n + 1) th page is started. And this result is T
Reported as LB hit signal 13 or TLB miss signal 14. In the first embodiment, the case of TLB miss will be described. That is, after the nth page, the n + th page
A TLB miss occurs even in one page, and the TLB miss signal 14 is asserted for two consecutive cycles. When the TLB miss signal 14 for the (n + 1) th page is asserted, the translation table information needs to be fetched from the main memory. However, since the address translating signal 15 for the nth page has already been asserted, the (n + 1) th page. Address translation cannot be performed for pages.
Therefore, the address translation request signal 23 is asserted, and the end of the address translation for the nth page is waited for.

When the address conversion for the nth page is completed, the address conversion in progress signal 15 is negated. As a result, the request by the address translation request signal 23 is immediately accepted and the address translation request signal 23 is negated. As a result, the address translating signal 24 is asserted and the translation table fetch request signal 16 is asserted. When the bus transfer priority is accepted by asserting the conversion table fetch request signal 16, the bus transfer priority acknowledge signal 17 is asserted, and the transfer of STE, PTE or KEY is started on the data bus. Then, by asserting the bus transfer end signal 18, the transfer of STE, PTE, or KEY is ended. Further, like the conventional operation described above, it is indicated by asserting one of the STE fetch signal 19, the PTE fetch signal 20, and the KEY fetch signal 21.

Embodiment 1.2 In Embodiment 1.1, it is checked whether or not there is a TLB hit for the (n + 1) th page when the address translation for the nth page is performed, and a TLB miss is detected. In that case, the address translation information for the (n + 1) th page is stored in the TLB.

On the other hand, in the present embodiment 1.2, when the address conversion for the nth page is performed, the n-1th
It was inspected whether a TLB hit was made to the page. Similarly in the case of the second embodiment, when a TLB miss occurs, the address translation information for the (n-1) th page is stored in the TLB.

Embodiment 2 A preferred embodiment of the third invention will be described. For example, in FIG.
, The first to 19th bits of the logical address (this is the address (1: 1
When the page information is decided by the expression (9), the 20th bit of the logical address (this is
If the address (represented like 20) is 0, it can be seen that the location of the address is the first half of the nth page,
Further, when the logical address (20) = 1, it can be seen that the location of the address is the latter half of the nth page.

The location of the logical address is the latter half of the page,
That is, when it exists at a position close to the page n + 1, the same processing as that in the above-mentioned Embodiment 1.1 is performed. That is,
It is determined whether or not a TLB miss occurs for the (n + 1) th page.

On the other hand, when the location of the logical address is in the first half of the page, that is, at a position close to the (n-1) th page, the same processing as that in the above-mentioned Example 1.2 is performed. That is, it is determined whether or not a TLB miss occurs on the (n-1) th page.

Embodiment 3.1 FIG. 2 is a time chart showing an address conversion method according to a preferred embodiment 3.1 of the fourth invention. This time chart is a time chart of main signals by conventional address conversion using a two-stage page address conversion method of a two-phase clock type computer system.

When there is an instruction request signal for an instruction at an address belonging to the nth page, the instruction request signal 1
0 is asserted. When the instruction request signal 10 is asserted, if the internal processing is not busy, the acknowledge signal 11 is asserted and the internal processing is started. Immediately after the acknowledge signal 11 is asserted, the TLB access signal 12 is asserted for two cycles. By asserting the TLB access signal 12 in the first cycle, the TLB index for the nth page is executed, and the result is reported as the TLB hit signal 13 or the TLB miss signal 14. In the example shown in FIG. 2, an example in which a TLB miss has occurred is described. Therefore, the TLB miss signal 14 is asserted, and the conversion table information needs to be fetched from the main memory.

In order to fetch the conversion table information from the main memory, the address conversion in progress signal 15 is asserted and the conversion table fetch request signal 16 is asserted. When the bus transfer priority is accepted by asserting this signal, the bus transfer priority acknowledge signal 17 is asserted, and the transfer of STE, PTE or KEY on the data bus is started. Then, by asserting the bus transfer end signal 18, STE, PTE, or KEY
Transfer is completed. Further, similar to the conventional operation described above, the STE fetch signal 19 and the PTE fetch signal 20
Alternatively, it is indicated by asserting one of the KEY fetch signals 21.

On the other hand, by asserting the acknowledge signal 11, the content 23 of the page holding register is changed to the (n +) th.
Since the information of the first page is held and the TLB access signal 12 of the second cycle is asserted, the index for the (n + 1) th page is started. And this result is T
Reported as LB hit signal 13 or TLB miss signal 14. In the present Example 3.1, since there is a TLB hit in the (n + 1) th page, the TLB hit signal 13 is asserted. TLB hit signal 13
Is asserted, the contents of the page holding register 23
Indicates information on page n + 2, and the TLB index for page n + 2 is implemented. The result is the TLB hit signal 13 or the TLB miss signal 14
Is reported by being asserted. In the third embodiment, since the TLB miss is for the (n + 1) th page, the TLB hit signal 13 is asserted.
When the TLB miss signal 14 for the (n + 2) th page is asserted, the translation table information has to be fetched from the main memory, but since the address translating signal 15 for the (n) th page has already been asserted, the (n + 2) th.
Address translation cannot be performed for pages. Therefore, the address translation request signal 23 is asserted, and the end of the address translation for the nth page is waited for.

When the address conversion for the nth page is completed, the address conversion in progress signal 15 is negated. As a result, the request by the address translation request signal 23 is immediately accepted and the address translation request signal 23 is negated. As a result, the address translating signal 24 is asserted and the translation table fetch request signal 16 is asserted. When the bus transfer priority is accepted by asserting the conversion table fetch request signal 16, the bus transfer priority acknowledge signal 17 is asserted, and the transfer of STE, PTE or KEY is started on the data bus. Then, by asserting the bus transfer end signal 18, the transfer of STE, PTE, or KEY is ended. Further, like the conventional operation described above, it is indicated by asserting one of the STE fetch signal 19, the PTE fetch signal 20, and the KEY fetch signal 21.

Embodiment 3.2 In the above-mentioned embodiment 3.1, an example in which the page in the (n + 1) th page direction, that is, the backward direction is searched for whether or not it is registered in the TLB has been shown. Similarly to the above-described Example 1.2, it is preferable to search the n−1th page direction, that is, the page in the forward direction as to whether or not the page is registered in the TLB.

Embodiment 3.3 Also, as in the case of Embodiment 2 above, based on whether the logical address causing the address translation of the nth page is in the first half or the second half of the nth page. It is also preferable to determine the search direction.

Embodiment 4 FIGS. 3 and 4 are time charts for explaining the address conversion method of the fifth preferred embodiment of the present invention. This time chart is a time chart of main signals by conventional address conversion using a two-stage page address conversion method of a two-phase clock type computer system.

First, when there is an instruction request signal for an instruction at an address belonging to the nth page, the instruction request signal 10 is asserted. As a result, after the address conversion of the n-th page, there is an instruction request for the address belonging to the k-th page during the address conversion of the (n + 2) th page, and when the instruction request signal 10 is asserted, the bus transfer cancel signal 25 is immediately issued. Is asserted and the bus transfer in progress is canceled. Along with this, the n +
Address conversion in progress signal 2 which indicates that the address conversion of page 2 is in progress
4 is negated.

As a result, it is possible to regard that the address conversion regarding the (n + 2) th page that has been executed is not executed from the beginning. As a result, immediately kth
It is possible to move on to performing address translation for the page.

In FIG. 4, similarly, first, there is an instruction request signal of an instruction at an address belonging to the nth page, whereby the address translation of the nth page is performed after performing the address translation of the nth page. In order
When the address translation request signal 23 is asserted, there is an instruction request for an address belonging to the k-th page, and when the instruction request signal 10 is asserted, the address translation request signal 23 is negated immediately. As a result, the address conversion for the (n + 2) th page can be regarded as a request for no conversion being requested from the beginning, and the process immediately shifts to the execution of the address conversion for the kth page.

[0048]

As described above, according to the first to sixth aspects of the present invention, when the address conversion of a certain page is performed, the address conversion for the peripheral pages is also performed,
The peripheral page conversion table information is stored in the TLB.

That is, according to the present invention, it is possible to perform address conversion prior to an instruction request, so that there is an effect of reducing TLB misses when actually accessing a memory.

Therefore, the overhead of address translation due to a TLB miss is eliminated, and the device can be operated efficiently.

Further, according to the seventh aspect of the present invention, the operation of performing the address conversion prior to the instruction request is stopped when an instruction request for another page or the like occurs, so that the apparatus original There is no fear of affecting the processing.

[Brief description of drawings]

FIG. 1 is a time chart showing an address conversion operation according to a preferred first embodiment of the present invention.

FIG. 2 is a time chart showing the operation of address conversion according to the preferred third embodiment of the present invention.

FIG. 3 is a time chart showing an operation of address conversion according to a preferred fourth embodiment of the present invention.

FIG. 4 is a time chart showing the operation of address conversion according to the preferred fourth embodiment of the present invention.

FIG. 5 is a configuration diagram of a general address conversion unit.

FIG. 6 is a time chart showing a conventional address conversion operation.

[Explanation of symbols]

1 logical address bus 2 logical address register 3 data bus 4 data register 5 translation lookaside buffer (TLB) 6 comparison circuit 7 real address register 8 real address bus 9 clock signal 10 instruction request signal 11 request acknowledge signal 12 TLB access (start) Signal 13 TLB hit signal 14 TLB miss signal 15 Address conversion in progress signal 16 Conversion table fetch request signal 17 Bus transfer priority acknowledge signal 18 Bus transfer end signal 19 STE fetch signal 20 PTE fetch signal 21 KEY fetch signal 22 Page holding register contents 23 Address conversion request signal 24 Address conversion in progress signal for address conversion according to page holding register contents 25 Bus transfer cancel signal

Claims (7)

[Claims] 1. A first address translation means for performing an address translation by a page address translation method using an address translation table on a main memory, and a translation index buffer storing a table of some pages of the address translation table. A second address translation means for performing address translation faster than the first address translation means using a mechanism, wherein an address to be translated is stored in the translation lookaside buffer mechanism. If it is included in the page stored in the translation index buffer mechanism, the first address translation step of performing the address translation by the second address translation means, and the address to be translated is included in the page stored in the translation index buffer mechanism. If it is not included, the first address conversion means is the address conversion table on the main memory. A second address translation step of reading a table of pages necessary for address translation, performing address translation using the read page table, and storing the read page table in the translation index buffer mechanism. , Which is a step subsequent to the first address translation step or the second address translation step, wherein n + 1 pages adjacent to the n page containing the address to be translated are A storage step of checking whether or not the table is stored in the index buffer, and if the result of this check is that it is not stored, the table of page n + 1 is read from the main memory and stored in the conversion index buffer. An address translation method comprising: 2. A first address translation means for performing an address translation by a page address translation method using an address translation table on a main memory, and a translation index buffer storing a table of some pages of the address translation table. A second address translation means for performing address translation faster than the first address translation means using a mechanism, wherein an address to be translated is stored in the translation lookaside buffer mechanism. If it is included in the page stored in the translation index buffer mechanism, the first address translation step of performing the address translation by the second address translation means, and the address to be translated is included in the page stored in the translation index buffer mechanism. If it is not included, the first address conversion means is the address conversion table on the main memory. A second address translation step of reading a table of pages necessary for address translation, performing address translation using the read page table, and storing the read page table in the translation index buffer mechanism. , Which is a step subsequent to the first address translation step or the second address translation step and which is adjacent to the n page containing the address to be translated, It is checked whether or not it is stored in the conversion index buffering mechanism. If the result of this check is that it is not stored, the table of page n-1 is read from the main memory and stored in the conversion index buffering mechanism. An address translation method comprising: 3. A first address translation means for performing an address translation by a page address translation method using an address translation table on a main memory, and a translation index buffer storing a table of a part of the page of the address translation table. A second address translation means for performing address translation faster than the first address translation means using a mechanism, wherein an address to be translated is stored in the translation lookaside buffer mechanism. If it is included in the page stored in the translation index buffer mechanism, the first address translation step of performing the address translation by the second address translation means, and the address to be translated is included in the page stored in the translation index buffer mechanism. If it is not included, the first address conversion means is the address conversion table on the main memory. A second address translation step of reading a table of pages necessary for address translation, performing address translation using the read page table, and storing the read page table in the translation index buffer mechanism. , Which is a step that is executed subsequent to the first address translation step or the second address translation step, wherein the address to be translated is the position within the n page that includes this address. In the determining step of determining, and in the determining step, if it is determined that the address to be translated exists in the latter half of the n pages, whether or not n + 1 page is stored in the translation index buffer mechanism. Is checked, and if the result of this check is that it is not stored, the table of n + 1 pages is In the next page storing step of reading from the main memory and storing in the conversion index buffering mechanism, and in the determining step, when it is determined that the address to be translated exists in the first half of the n page, n− It is checked whether or not one page is stored in the conversion index buffering mechanism. If the result of this check is that it is not stored, the table of the n-1 page is read from the main memory and the conversion index is read. And a step of storing a previous page for storing in a buffer mechanism. 4. The address translation method according to claim 1, wherein the storing step is executed subsequent to the first address translation step or the second address translation step, and includes the address to be translated. a step of sequentially checking whether or not n + 1 pages are stored in the translation index buffering mechanism, and performing an inspection until an unstored page is found. When a page not stored in the mechanism is found, the table of the page is read from the main memory and stored in the conversion index buffer mechanism. 5. The address translation method according to claim 2, wherein the storing step is executed after the first address translation step or the second address translation step, and includes the address to be translated. A step of sequentially checking whether or not n-th page in the direction of n−1 page is stored in the conversion index buffering mechanism, and checking until a page not stored is found. When a page not stored in the mechanism is found, the table of the page is read from the main memory,
An address translation method characterized by storing in the translation index buffer mechanism. 6. The address translating method according to claim 3, wherein the next page storing step is executed after the first address translating step or the second address translating step, and the address to be translated is A step of sequentially inspecting, for the included n pages, whether or not the pages in the direction of n + 1 page are stored in the conversion index buffering mechanism, and performing an inspection until an unstored page is found. When a page not stored in the index buffer is found, the table of the page is read from the main memory and stored in the translation index buffer, and the previous page storing step includes the first address translation. Step or the second address translation step, which is subsequently executed and includes the address to be translated. A step of sequentially checking whether or not n-1 pages are stored in the conversion index buffering mechanism with respect to n pages, and performing a check until an unstored page is found. When a page not stored in the translation index buffer mechanism is found, a table of the page is read from the main memory and stored in the translation index buffer mechanism. 7. The address translation method according to claim 1, 2 or 3 or 4 or 5 or 6, wherein another page is executed while the processing in the storing step, the previous page storing step or the next page storing step is being executed. Address conversion request is generated, the processing in the storing step, the previous page storing step, or the next page storing step is stopped, and the address conversion of the other page is executed. .