JPH0723396A - Encoding device for digital picture signal - Google Patents

Abstract

PURPOSE:To reduce both memory capacity and block distortion by storing only picture elements other than the picture elements of a block boundary and interpolating the picture elements on the block boundary by picture elements other than the picture of an adjacent block boundary in a device for dividing a picture signal into plural blocks and encoding at every divided block. CONSTITUTION:A digital picture signal is divided into plural blocks which is constituted of prescribed number of picture elements and is encoded/decoded at every block. A locally decoded signal X1 obtained by an adder 107 is inputted to a selector circuit 110, a locally decoded signal other than boundary picture elements of a block generating block distortion is selected and supplied to a frame memory 108 so as to reduce the memory capacity per block. After the elapse of a prescribed storage period, the stored contents are outputted to a block boundary picture element interpolating circuit 111 and a predictor 109 interpolates block boundary picture elements necessary for compensating the movement at every block by using picture elements other than an adjacent block boundary which are outputted from the memory 108. Consequently memory capacity can be reduced and block distortion can also be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for dividing a digital image signal into blocks composed of a plurality of pixels, subjecting each block to block coding, and compression coding and decoding. The present invention relates to a digital image signal encoding and decoding apparatus that performs compression encoding and decoding by utilizing inter-field correlation.

[0002]

2. Description of the Related Art Conventionally, an encoding apparatus and a decoding apparatus for compressing data by using frame or field correlation of various digital image signals have been proposed. One example thereof is shown in FIGS. 6 and 7. Things are generally known. FIG. 6 is a block diagram of the encoding device, and FIG. 7 is a block diagram of the decoding device.

In FIGS. 6 and 7, 101 is a subtractor, 1
Reference numeral 02 is an orthogonal transformer represented by DCT, 103 is a quantizer, 104 is a variable length encoder represented by Huffman coding, 105 is an inverse quantizer, 106 is an inverse orthogonal transformer, 107 is an adder, 108 is a frame memory,
109 is a predictor, and 112 is a variable length decoder. The operation of the conventional example will be described below with reference to the drawings.

First, the operation of the coding apparatus shown in FIG. 6 will be described. In FIG. 6, a digital image signal that has been divided into blocks each including a plurality of pixels is input to an input terminal 100 after the time axis is rearranged. The rearrangement of the time axis is performed according to the prediction structure between frames. For example, an example of a prediction structure between frames is schematically shown in FIG.

In FIG. 3, (1), (2), and (3) indicate one frame of the image signal. The arrow indicates that the frame of (1) is encoded within the frame and the frame of (2) indicates (1). ) And (3) frames are predicted and coded,
The frame (3) indicates that the frame is predicted and encoded from the frame (1). The same applies to decryption.
The temporal flow of the image signal is a flow of (1) → (2) → (3) frames, but at this time, the image signal is temporally (1) → (3) → ( 2) The data is rearranged and input in the order of frames. This rearrangement is performed using, for example, a frame memory.

The subtractor 101 is provided for each of the digital image signals X _o included in the above-described block.
From the image signal X _p predicted by the predictor 109 that performs motion compensation for each block, and the prediction error signal E =
X _o −X _p is output to the orthogonal transformer 102. Orthogonal transformer 1
02 orthogonally transforms the prediction error signal E for each block and outputs it to the quantizer 103. The quantizer 103 quantizes the orthogonally transformed signal and outputs the quantized signal Q to the variable-length encoder 104 and the inverse quantizer 105. The variable length encoder 104 encodes the quantized signal Q and outputs the encoded signal from the output terminal 113 to the transmission path.

On the other hand, the inverse quantizer 105 outputs the quantized signal Q
The inversely quantized signal is output to the inverse orthogonal transformer 106.
The inverse orthogonal transformer 106 performs the inverse orthogonal transformation for each block.
And outputs it to the adder 107. The adder 107
The signal obtained by the orthogonal transformer 106 and one frame before
Prediction signal X_pAnd are added, and the locally decoded signal X_lThe frame
Output to Molly 108. This locally decoded signal X_lIs
After being stored in the frame memory 108 for a predetermined period, the predictor
It is input to 109. The predictor 109 is new for each block.
Motion-compensated prediction signal X_pSubtractor 101 and
Output to the adder 107. In fact, the predictor 109
Block using frame, current frame, and back frame
Each motion vector is detected, and this motion vector and local
Decoded signal X _lMotion compensation of the current frame based on
ing.

Next, the decoding apparatus will be described with reference to FIG. In FIG. 7, the input terminal 114 receives an encoded signal encoded on the encoding side from the transmission line. In terms of time, the frame numbers (1) → (3) → shown in FIG.
It will be input in the order of (2). The encoded signal is decoded by the variable length decoder, inversely quantized by the inverse quantizer 105, and inversely orthogonally transformed by the inverse orthogonal transformer 106. The adder 107 adds the signal obtained by the inverse orthogonal transformer 106 and the prediction signal X _q one frame before to obtain the decoded signal X _r.
Is output to the output terminal 115 and the frame memory 108.

This decoded signal X _r is _stored in the frame memory 1
After being stored for a predetermined period such as one frame period or two frame period at 08, it is input to the predictor 109.
The predictor 109 outputs the motion-compensated prediction signal X _q newly for each block to the adder 107. The configuration on the decoding side is basically the same as the local decoding part on the encoding side, and X
_p = X _q and X ₁ = X _r .

[0010]

However, in order to detect a motion vector with the conventional configuration as described above, the frame memory requires two frames, the previous frame and the subsequent frame, and thus the memory capacity is very large. Further, the local decoded signal X _l and the decoded signal X _r stored in the frame memory 108 are signals including block distortion peculiar to block coding, and block distortion is added to a prediction signal used for motion compensation. Has the drawback that

In view of the above points, the present invention reduces the memory capacity by storing only pixels other than block boundaries in the storage means, and interpolates pixels at block boundaries from pixels other than block boundaries between adjacent blocks. It is an object of the present invention to provide an encoding device and a decoding device for a digital image signal that reduces block distortion occurring in a prediction signal used for motion compensation.

[0012]

In view of the above, the present invention has a storage means for storing a pixel value other than a block boundary among a plurality of pixels locally decoded for each block for a predetermined period.
Interpolation means for interpolating the pixel value at the block boundary from the pixel value stored by the storage means, motion compensation is predicted using the pixel value stored by the storage means and the pixel value interpolated by the interpolation means. And a configuration including means.

[0013]

In order to achieve the above-mentioned object, the present invention, after converting the digital image signal into blocks and encoding or decoding,
When only the pixels other than the block boundary are stored in the storage unit and the prediction signal used for the motion compensation is created, the pixel of the block boundary is interpolated by the pixel other than the block boundary between the adjacent blocks by the interpolation unit. .

[0014]

Embodiments of the present invention will be described below with reference to the drawings. 1 is a block diagram of a digital image signal encoding apparatus according to an embodiment of the present invention, and FIG. 2 is a block diagram of a digital image signal decoding apparatus according to an embodiment of the present invention. In this embodiment, the image signal is sampled so that the number of pixels in one frame is 720 pixels × 480 pixels and quantized with 8 bits, and the quantized two-dimensional digital image signal is converted with 8 × 8 pixels. A case will be described as an example in which the blocks are divided into blocks and the blocks are encoded and decoded.

1 and 2, the pixel selection circuit 11
0, the block boundary pixel interpolation circuit 111 is the same as the conventional example. The operation of the blocks different from the conventional example will be described in detail below with reference to FIGS.

First, the coding apparatus shown in FIG. 1 will be described. In FIG. 1, the locally decoded signal X _l obtained by the adder 107 is input to the pixel selection circuit 110. The pixel selection circuit 110 internally includes a counter that counts the number of pixels based on the horizontal synchronizing signal and the vertical synchronizing signal of the image signal, and according to the count value of this counter, except for the boundary pixels of the block where block distortion occurs. Only the locally decoded signal of is selected and output to the frame memory 108.

FIG. 4 schematically shows one block of pixels of the locally decoded signal. The total number of pixels in one block is 64,
28 pixels at the block boundary indicated by the white circle 400 and 4 pixels
Pixels other than the block boundary indicated by 01 are composed of 36 pixels. Only the pixels indicated by 401 other than the block boundary are output to the inner frame memory 108 and stored in the frame memory 108.

With such a configuration, the memory capacity per block, which used to be 64 bytes in the past, is 36 bytes, and one frame is 34560.
It is possible to reduce the memory capacity of 0 bytes to 194400 bytes, which is almost half. The locally decoded signal indicated by 401 in FIG. 4 stored in the frame memory 108 is output to the block boundary pixel interpolation circuit 111 after a predetermined storage period such as one frame period or two frame periods.

The block boundary pixel interpolating circuit 111 interpolates the block boundary pixels, which are required when the predictor 109 performs motion compensation for each block, by using pixels other than the block boundaries of the adjacent blocks output from the frame memory 108. To do. FIG. 5 shows an example of the interpolation method.

Pixels at the vertical boundaries of the block ◎ _x are interpolated using the pixel group inside the solid line in FIG. 5 (a), and pixels at the horizontal boundaries of the block ◎ _y are inside the solid line in FIG. 5 (b). Interpolation using pixel groups, pixel at the top of block ◎ _z
With respect to, the interpolation is performed using the black pixel group inside the solid line in FIG. This interpolation is equivalent to operating a low-pass filter on all block boundaries of the locally decoded signal, so that block distortion of the locally decoded signal is reduced.

The block boundary pixel interpolation circuit 111 predicts the pixels other than the block boundaries stored in the frame memory 108 and the interpolated block boundary pixels from the predictor 109.
Output to. The operation on the decoding side is similar to the operation of the local decoding part on the encoding side.

As described above, in this embodiment, when the digital image signal is divided into blocks, coded and decoded, only pixels other than the block boundaries are stored in the memory, and a prediction signal used for motion compensation is created. , Block boundary pixels are interpolated using pixels other than the block boundary between the stored adjacent blocks.

In the present embodiment, the image signal is sampled so that the number of pixels in one frame is 720 pixels × 480 pixels, quantized with 8 bits, and the quantized two-dimensional digital image signal is obtained. The description has been given by taking an example of dividing into blocks each including 8 × 8 pixels and performing encoding and decoding for each block. However, the number of pixels of the image signal, the number of quantization bits, and the number of block divisions can be set arbitrarily. It doesn't matter, but the larger the size of both, the greater the effect of reducing the memory capacity.

Further, as the method of interpolating the pixels on the block boundary, the configuration in which the pixel groups arranged in one dimension are used for the interpolation has been described, but the interpolation method may be performed using the two-dimensional pixel groups.

[0025]

As described above, according to the present invention, since only the pixels other than the block boundaries of the decoded signal are stored in the storage means, the memory capacity of the storage means can be greatly reduced and the block distortion can be reduced. Since the pixels in the generated block boundary portion are interpolated using pixels other than the block boundary of the adjacent block, it is possible to reduce the block distortion of the prediction signal used for motion compensation.

[Brief description of drawings]

FIG. 1 is a block diagram of a digital image signal encoding apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram of a digital image signal decoding apparatus according to an embodiment of the present invention.

FIG. 3 is a diagram schematically showing an example of a prediction structure between frames.

FIG. 4 is a diagram schematically showing pixels of a locally decoded signal of one block.

FIG. 5 is a diagram schematically showing a pixel group of adjacent blocks for interpolating pixels at block boundaries.

FIG. 6 is a block diagram of a conventional digital image signal encoding device.

FIG. 7 is a block diagram of a conventional digital image signal decoding device.

[Explanation of symbols]

 101 Subtractor 102 Orthogonal Transformer 103 Quantizer 104 Variable Length Encoder 105 Inverse Quantizer 106 Inverse Orthogonal Transformer 107 Adder 108 Frame Memory 109 Predictor 110 Pixel Selection Circuit 111 Block Boundary Pixel Interpolation Circuit 112 Variable Length Decoding Chemical device

Claims (3)

[Claims] 1. A digital image signal constituting the same field or the same frame divided into blocks composed of a plurality of pixels is block-coded for each block by utilizing the correlation between frames or between fields by motion compensation. Encoding means to be applied, and among a plurality of pixels locally decoded for each block, pixel values other than block boundaries are set for a predetermined period,
Storage means for storing, and interpolation means for interpolating pixel values at block boundaries from the pixel values stored by the storage means,
An encoding device for a digital image signal, comprising: a pixel value stored by the storage means; and means for predicting the motion compensation using the pixel value interpolated by the interpolation means. 2. A digital image signal, which is divided into blocks composed of a plurality of pixels and is block-encoded for each block, or a digital image signal forming the same frame, is subjected to motion compensation to obtain correlation between frames or between fields. Decoding means for decoding by using, storage means for storing pixel values other than block boundaries among a plurality of pixels decoded for each block for a predetermined period, and block boundaries based on the pixel values stored by the storage means Interpolation means for interpolating the pixel value of, and the pixel value stored by the storage means,
A decoding device for a digital image signal, comprising: means for predicting the motion compensation using the pixel value interpolated by the interpolating means. 3. Interframe or interfield based on motion compensation predicted using a pixel value interpolated by an interpolating means from a pixel value other than a block boundary of a block composed of a plurality of pixels and a pixel value other than the block boundary. An encoding device that compresses and encodes a digital image signal by using the correlation of the pixel value, and a pixel value of a block boundary interpolated from a pixel value other than the block boundary among a plurality of pixels decoded for each block and a pixel value other than the block boundary. A digital image signal encoding / decoding device comprising a decoding device for decoding a digital image signal based on motion compensation predicted using pixel values.