JPH07231566A - Control circuit for active filter - Google Patents

Abstract

PURPOSE:To prevent a harmonic current from increasing over a generation amount by interrupting the active filter (AF) operation when the sum of harmonic component current and compensation current exceeds a preset level during AF operation and controlling the compensation current to zero. CONSTITUTION:After starting AF operation, a harmonic component current ILh and a compensation current Ia are added through second addition 13 to produce a second addition signal Pt which is then converted through a DC converter 19 into a DC signal Pq. A comparator 14 compares the DC signal Pq with a set value Pr and the second addition output signal Pt is fed to a second gate circuit 15. When it is lower than the set value Pr, output signal Ps from the comparator goes Low. Consequently, a first gate circuit 12 is conducted to bring about a normal AF operation mode and the second addition output signal Pt approaches zero as closely as possible thus canceling the harmonic current ILh.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control circuit for an active filter that cancels a harmonic current generated on the load side.

[0002]

2. Description of the Related Art In recent years, electric products having a power conversion device using a semiconductor element such as an inverter air conditioner have become widespread, and accordingly, harmonic interference frequently occurs.
Therefore, the number of cases in which an active filter (active filter) is introduced as a countermeasure against harmonics is increasing.
One specific example will be described below with reference to FIGS. First, in FIG. 2A, (1) is a power supply, (2) is a system bus, (3) is a load, (4) is an active filter (hereinafter referred to as AF), and (5) is for detecting harmonic current. The first current transformer, (6) is the second current transformer for detecting the compensation current. The power source (1) is connected to a load (3) serving as a harmonic generation source via a system bus (2). AF (4) is shown in FIG.
It has a control circuit (7) and a high frequency inverter (not shown) shown in (b), and the harmonic current (I
The compensating current (Ia) of the opposite phase for canceling L) is injected into the system bus (2) by the above-mentioned inverter, and the drive of the inverter is controlled by the control circuit (7). As shown in FIG. 2B, the control circuit (7) determines that the harmonic current (IL) detected by the first current transformer (5) (however, the same symbol as the bus current is used) is to be compensated. A harmonic detector (8) for detecting a harmonic component current (ILh) of a predetermined order and a compensation current (Ia) detected by the second current transformer (6) (however, the same symbol as the bus current is used. ) And a harmonic component current (ILh) are added to the first adder (9),
It is connected to the output side of the first adder and outputs the first addition output signal (ILh
+ Ia) Zero crossing hysteresis comparator (10) for discriminating between positive and negative, and the output side of the comparator is connected. If the output signal is positive, it increases the compensation current (Ia). If negative, the compensation current. An inverter drive unit (11) for controlling the drive of each inverter in the direction of decreasing (Ia).

Here, the equivalent circuit of FIG.
As shown in (c), the above equivalent circuit is one in which the power source (1) is represented by system impedance and the load (3) and AF (4) are each represented by current sources.
It is configured such that the harmonic component current (ILh) generated in (A) on the load (3) side is canceled by injecting it into the system bus (2) from (4) in the anti-B direction.

[0004]

The problem to be solved is to operate the AF (4) when a load (3a) having a low impedance with respect to harmonics such as a capacitor on the load side is added to the system condition. , Load impedance (-X
The harmonic current (IL) expands between c) and the system impedance (Xs), and the AF (4) cannot cancel the harmonic current (IL). That is, for example, as shown in the equivalent circuit of FIG. 2D, the load impedance (-Xc) is connected in parallel to the system impedance (Xs) as seen from the current source side, and the current source {load (3)} If the generated current is (Io), the shunt currents to the system impedance (Xs) and the load impedance (-Xc) are (Is) and (Ic), respectively, and the current direction from the bottom to the top of the figure for each impedance is positive, Is = {-Xc / (Xs-Xc)} ・ Io, Ic = {Xs /
(Xs-Xc)}-Io.

When Xs> Xc, if the current (Io) flows in the positive direction, the shunt current (Is) is in the negative direction (from top to bottom) and the shunt current (Ic) is in the positive direction (from bottom to bottom). Flow to each of the above). Therefore, when the harmonic component current (ILh) flows from the load (3) in the positive direction as the current (Io), the shunt current (Is) that flows in the negative direction (anti-A direction) in the first current transformer (5). 2C, the compensation current (Ia) flows in the opposite direction (direction B) to that of FIG. 2C. Then, since the compensation current (Ia) flows in the positive direction like the harmonic component current (ILh), the shunt current (Isa) flowing through the system impedance (Xs) of the compensation current (Ia) is the same as the shunt current (Is). Direction (counter A direction)
Flow to. As a result, the detection current in the negative direction (anti-A direction) in the first current transformer (5) further increases, so that the compensation current (Ia) further increases and the harmonic component current (ILh) expands. Get out of control.

The load impedance (-Xc) is rarely applied, but when the uncontrollable state as described above occurs, the shunt currents (Is) (Ic) of the system impedance (Xs) and the load impedance (-Xc). ) Both become large, and not only the original harmonic component current cannot be canceled, but
Problems such as heating of the load side capacitor will occur.

When Xs <Xc, if the current (Io) flows in the positive direction, the shunt current (Is) is in the positive direction (from bottom to top),
The shunt current (Ic) flows in the negative direction (from top to bottom). Therefore, when the harmonic component current (ILh) flows from the load (3) in the positive direction, the shunt current (Is) is detected in the positive direction (direction A) in the first current transformer (5), and accordingly ,
Although the detection amount increases, the compensation current (Ia) flows in the same direction (anti-B direction) as in FIG. 2C and cancels the original harmonic component current.

[0008]

According to the present invention, a harmonic detector detects a harmonic component current of a predetermined order from a harmonic current generated on a load side, and a first adder adds the harmonic component current to a compensation current.
In the control circuit of the active filter, which drives and controls the compensation current generating inverter so that the first addition output signal becomes zero, and cancels the higher harmonic component current, in the control circuit between the higher harmonic detector and the first adder input. Connected to the first gate circuit for connecting or disconnecting the two, a second adder for adding the harmonic component current detected by the harmonic detector and the compensation current, and the second gate on one input side. The output of the adder is connected via a DC converter, the output signal of the DC converter is compared with a set value of a predetermined level, and a comparator for binarizing and outputting the second added output signal is compared with the input side. Gate circuit connected to the output of the first gate circuit and the second gate circuit connected to the gate signal input of the first gate circuit via the first inverter, and the active filter operation command signal as one input signal, and the first output side
An AND circuit connected to the gate signal input of the second gate circuit via a timer, and the other input of the AND circuit connected to the output of the second gate circuit with its input side connected to the output of the second gate circuit via a second inverter. And a second timer connected to.

[0009]

According to the above technical means, when it is detected during AF operation that the added value of the harmonic component current and the compensation current is equal to or greater than the set value of the predetermined level, the system condition has a low impedance for the harmonic. Then, it is determined that the harmonic current has expanded due to the addition of the load, and the AF operation is interrupted to control the compensation current to zero so that the harmonic current does not expand beyond the load-side harmonic generation amount. In addition, after a lapse of time determined by the second timer, the AF operation mode is forcibly returned to the normal AF operation mode, the added value at that time is checked, and then the AF operation is continued or interrupted.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a control circuit for an active filter according to the present invention will be described below with reference to FIG. Figure 2 (b)
The same parts as those shown in are denoted by the same reference numerals and the description thereof will be omitted. The difference is that the detection control system shown in the dotted line is added. In the figure, (12) is the first gate circuit, (13) is the second adder, (14) is the comparator, and (15) is the Two gate circuits, (16) is an AND circuit, and (17) and (18) are first and second timers, respectively. The first gate circuit (12) is connected between the harmonic detector (8) and the input of the first adder (9), and is electrically connected or cut off (output low) by the first gate signal (Ga). ) Do. Second adder (13)
Adds the harmonic component current (ILh) detected by the harmonic detector (8) and the compensation current (Ia). Comparators (14)
Is connected to one input side of the output of the second adder (13) via a DC converter (19), and outputs a DC signal (Pq) which is the DC converter output and a set value (Pr) of a predetermined level. And the second addition output signal (Pt = ILh + Ia) is binarized and output. Here, the direct-current converter (19) is formed by connecting a full-wave rectifier (20) and a filter (21) having a large time constant in series.

The second gate circuit (15) has an input side connected to the comparator output and an output side connected to the gate signal input of the first gate circuit (12) via the first inverter (22). The AND circuit (16) uses the high signal (Ha) of the AF operation command as one input signal, and connects the output side to the gate signal input of the second gate circuit (15) via the first timer (17). The second timer (18) has an input side connected to the output of the second gate circuit (15) and an output side connected to the AND circuit (16) via the second inverter (23).
Connect to the other input of.

The operation of the present invention based on the above configuration will be described below. First, since the output signal of the second timer (18) is low at the start of AF operation, it is inverted to high via the second inverter (23) and becomes the other input signal of the AND circuit (16). . Therefore, if a high operation command signal (Ha) is input to one terminal of the AND circuit (16) at the same time as AF operation,
AND circuit output goes high, which is the first timer (17)
The second gate signal (Gb) becomes a second gate signal (Gb) after a lapse of a certain time after being input to the second gate circuit (15), and the second gate circuit (15) becomes conductive. That is, after the AF operation starts, the detection control system within the dotted line in the figure operates after a lapse of a fixed time determined by the first timer (17).

Therefore, after the AF operation is started and a certain time has elapsed, the harmonic component current (ILh) is set by the second adder (13).
And the compensation current (Ia) are added, and the second addition output signal (Pt = ILh + Ia) is converted into a DC signal (Pq) via the DC converter (19) and output. Then, the comparator (14) compares the direct current signal (Pq) with the set value (Pr), binarizes and outputs the second addition output signal (Pt), and inputs it to the second gate circuit (15). . Therefore, the second addition output signal (Pt),
That is, when the DC signal (Pq) is less than or equal to the set value (Pr), the comparator output signal (Ps) becomes low. It appears at the output of the second gate circuit (15) and is inverted to high through the first inverter (22) to become the first gate signal (Ga). As a result, the first gate circuit (12) is turned on to enter the normal AF operation mode, the second addition output signal (Pt) approaches zero as much as possible, and the harmonic component current (ILh) is canceled.

On the other hand, when a load (3a) having a low impedance with respect to harmonics such as a capacitor is added to the load side to expand the harmonic current (IL), the second addition output signal (P
t) increases and becomes greater than zero. Then, the DC signal (Pq) exceeds the set value (Pr) and the comparator output signal (Pr)
s) becomes high, and its output signal (Ps) appears at the output of the second gate circuit (15) and is inverted to low through the first inverter (22) to generate the first gate signal (Ga). Become. As a result, it is detected that the harmonic current (IL) has expanded, and the first gate circuit (12) shuts off to control the compensation current (Ia) to zero. Don't help the expansion.

At the same time, the output signal (high) of the second gate circuit (15) is input to the second timer (18), and when the high signal continues as an input for a set fixed time, the output of the second timer becomes high. Further, it is inverted to low through the second inverter (23) and becomes the other input signal of the AND circuit (16). Then, the output signal of the AND circuit (16) becomes low, the first timer output becomes low, the second gate signal (Gb) becomes low, and the second gate circuit (15) is cut off (output low). Then, it is inverted through the first inverter (22), the first gate signal (Ga) becomes high, and the first gate circuit (12) becomes conductive.
Forced return to operation mode.

When the output signal of the second gate circuit (15) becomes low, the output of the second timer becomes low, which is inverted to high through the second inverter (23) and then the AND circuit. It becomes the other input signal of (16). As a result, after the time determined by the first timer (17) has elapsed, the second gate signal (Gb) becomes high again and the second gate circuit (15) becomes conductive.

Therefore, if the DC signal (Pq) is less than the set value (Pr) in the normal AF operation mode, A is used as it is.
If the DC signal (Pq) is still above the set value (Pr) even after returning to the normal AF operation mode while continuing the F operation mode, the comparator output signal (Ps) becomes high again and the second It appears in the output of the gate circuit (15) as it is, and then it is inverted to low through the first inverter (22) to become the first gate signal (Ga), and the first gate circuit (12) cuts off and compensates. The current (Ia) is controlled to zero.

When the output signal of the second gate circuit (15) becomes high, the second timer (18) operates in the same manner as described above, and after a lapse of a fixed time, the normal AF operation mode is resumed. The above operation is repeated.

[0019]

According to the present invention, when a load having a low impedance with respect to harmonics such as a capacitor is added to the load side to expand the harmonic current, it is detected to compensate for the harmonic cancellation. Since the current is controlled to zero,
It is possible to prevent the harmonic current from expanding beyond the generation amount of the harmonic generation source on the load side and to prevent the heating of the load side capacitor.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a control circuit for an active filter according to the present invention.

FIG. 2A is a block diagram showing an operation example of an active filter. (B) is a block diagram showing an example of a control circuit of a conventional active filter. Figure 2 (c)
It is an equivalent circuit schematic of (a). (D) is an equivalent circuit diagram explaining the subject of this invention.

[Explanation of symbols]

 8 Harmonic Detector 9 First Adder 12 First Gate Circuit 13 Second Adder 14 Comparator 15 Second Gate Circuit 16 AND Circuit 17 First Timer 18 Second Timer 19 DC Converter

Claims (1)

[Claims] 1. A first harmonic wave component current of a predetermined order is detected by a harmonic wave detector from a harmonic current generated on a load side.
In the control circuit of the active filter, which adds the compensation current in the adder and controls the driving of the compensation current generating inverter so that the first addition output signal becomes zero, thereby canceling the harmonic component current, the harmonic detector Connected to the first adder input,
A first gate circuit for connecting or disconnecting the two, a second adder for adding the harmonic component current detected by the harmonic detector and the compensation current, and the second adder output on one input side. A comparator, which is connected through a DC converter, compares the DC converter output signal with a set value of a predetermined level and binarizes and outputs the second addition output signal, and connects the input side to the comparator output. Then, the output side is connected to the gate signal input of the first gate circuit via the first inverter, and the active filter operation command signal is one input signal, and the output side is connected via the first timer. An AND circuit connected to the gate signal input of the second gate circuit; and an AND circuit having an input side connected to the second gate circuit output and an output side connected to the other input of the AND circuit via a second inverter. It is equipped with 2 timers Control circuit of the active filter.