JPH07230435A - Parallel computer with variable structure distinctive system network - Google Patents

Abstract

PURPOSE:To make an efficient communication of various information without lowering the efficiency of the whole parallel computer system. CONSTITUTION:The parallel computer 1 consists of plural processors 2-4 which have memories respectively and a network which connect the processors 2-4 to one another, and performs information processing by transmitting and receiving plural kinds of information including control information among the processors; and the network consists of a data network 5 which sends and receives at least data to be computed and a network 6 of another system which sends and receives at least the control information among the respective processors, which have programmable switches 8 for changing the mode of the connection with the network 6 of another system according to the kind of information sent and received among the processors.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel computer, and more particularly to a parallel computer having a variable-structure-based series network in which a plurality of processors are connected by a two-system network sharing functions.

[0002]

2. Description of the Related Art Conventionally, as a computer system for calculating a large amount of data at high speed, a large number of arithmetic processing units (hereinafter referred to as processors) each having its own memory are connected to each other to communicate various information. There is a distributed storage type parallel computer system that performs information processing (mainly calculation processing) while performing.

However, in the parallel computer system, in order to perform unified processing using a large amount of calculation target data stored in physically distributed memories, in addition to the data directly targeted for calculation. In addition, various types of information will be communicated between each processor.

The types of communication such as calculation target data and control information will be summarized and described below.

(1) Communication of data to be calculated From the viewpoint of the amount of data, the amount of data to be directly calculated is the largest.

(2) Control data communication From the viewpoint of communication priority, a small amount of data to be communicated prior to mass communication such as communication of control information performed by the operating system for resource management of the entire system. There is also communication of information in which timing is important, such as communication of time and clock setting information.

(3) Broadcast-type communication In addition, although there is communication that should be performed by broadcasting such as inquiring about the status of each processor, this type of communication uses the entire network for one communication,
While competing with a large amount of data communication performed on a one-to-one basis, it has a high priority.

(4) Calculation result output data In the calculation target data communication, the communication speed in which the data is transferred between the memory of each processor and the input / output device as the preparation for the calculation or the result It can be separately considered in that it is suppressed by the performance of the output device, that it is an input / output process from the viewpoint of each processor, and that it can be performed independently of the calculation process in progress.

(5) Reset request transmission When a failure occurs in a specific processor, it must be possible to promptly perform reset processing from the processor that has detected the failure.

(6) Dump Output of Memory In order to analyze the cause of a failure, the memory content is dump-outputted to a magnetic tape or the like. However, this communication processing of a large amount of data interferes with the communication processing in the normal processor group. Is not desirable.

(7) Backup communication path When a failure occurs in the data network, it is desirable to perform a degenerate operation by securing some backup communication path in order to avoid the occurrence of an incommunicable portion.

(8) Communication of debug information For debugging of basic software that controls communication processing,
It must be possible to collect debug information while maintaining the state of the data network.

(9) Communication of performance measurement information As a part of the performance measurement of hardware and software, it is necessary to measure the performance of the data network. It is not desirable because the state of will change.

(10) Hardware adjustment information For adjusting the hardware, a means for displaying or changing the state of an arbitrary processor is required.

By the way, performing various types of communications having different types of communications, required transfer performances, or different priorities in a physically single-system network leads to a reduction in communications efficiency, which in turn leads to a parallel computer system. There is a problem of reducing the overall efficiency.

In addition, there are some things which cannot be performed in the same network or are not desirable due to the nature of communication.

Therefore, in order to improve the communication efficiency of these different kinds of information, a separate system network, which is hardware independent from the main system data network used for the communication of data to be calculated, corresponds to the type of communication. do it,
Various proposals have been made to provide the function exclusively.

For example, as an example of the broadcast type communication,
As disclosed in Japanese Patent Application Laid-Open No. 4-287153 (title of the invention: parallel computer system), a network configuration method for economically improving communication efficiency by providing a one-way communication path exclusively for broadcast communication There is.

When a communication path different from the communication path of the data to be calculated is provided, for example, as a technique disclosed in Japanese Patent Laid-Open No. 3-268054 (invention title: high-speed parallel processing system), recognition processing is performed. Regarding a dedicated parallel processing system, there is known a configuration in which three systems of communication paths are independently provided for managing the entire computer system, for control information required for each processing, and for data to be calculated.

Similarly, as an example in which a communication path different from the communication path for the data to be calculated is provided, Japanese Patent Laid-Open No. 6265/1990 is proposed.
As disclosed in Japanese Patent Publication No. 4 (Title of Invention: Programmable Multiprocessor), a memory is used as a network configuration method in which the connection form between processors can be dynamically changed according to the application applied to the computer system. A configuration has been devised in which the interconnection state between processors can be changed by changing the data input to.

Further, as disclosed in Japanese Patent Laid-Open No. 62-263563 (Title of Invention: Network Configuration Method), a torus network in which a plurality of processors are connected in an annular shape is applied to the computer system. Depending on the intended use, by providing a bypass communication path that connects the communication ports associated with each processor,
A technique is known in which a configuration of a network is dynamically changeable.

In this torus-type network, a parallel processing symposium (as a configuration method that enables division reconfiguration of the torus-type network, efficient global operation, and broadcast communication by switching an additional switch between processors Proposed in "Partitioned Reconfigurable Torus Network" on page 175 of the JSPP'93 paper.

[0023]

However, providing a physically separate network for each of the plurality of types of communication inevitably increases the number of wires between the processors.

Further, it can be said that it is not economical considering that there is a low possibility that three or more types of communication will occur simultaneously.

Further, the physical limit of the total number of wirings limits the data transfer performance of the main system data network, which requires high performance, and there is a problem that the efficiency of the entire parallel computer system is lowered.

It is an object of the present invention to provide a parallel computer having a separate system variable structure network that enables efficient communication of various information without reducing the efficiency of the entire parallel computer system.

[0027]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows.

That is, it is composed of a plurality of processors each having a memory and a network for connecting the plurality of processors to each other, and a plurality of types of information including control information is transmitted and received between the plurality of processors to perform information processing. A parallel computer to perform, wherein the network comprises at least a data network for transmitting and receiving calculation target data, and another system network for transmitting and receiving at least control information between the plurality of processors, the plurality of processors, It has a programmable switch which changes the connection form with the said another type | system | group network according to the kind of information transmitted / received between several processors.

Further, at least one of the plurality of processors has an interface for accessing an input / output device, and the torus type connecting the plurality of processors in a ring shape is basically used as the basic type of the separate system network. And a processor having the interface,
The connection form of the plurality of processors and the separate network is managed.

[0030]

According to the above means, the network connecting the plurality of processors is mainly a data network for transmitting and receiving data to be calculated, and another system network for transmitting and receiving a plurality of types of information including control information between the processors. Since the connection form of the separate system network is changed according to the type of information transmitted / received between the processors by the programmable switch of each processor, there are various types without hindering the transmission / reception of the calculation target data. Information can be efficiently communicated.

Further, since the separate network is connected based on the torus type which connects the plurality of processors in an annular shape as a basic type, and this connection form is managed by the processor having the interface for accessing the input / output device, Various information can be efficiently communicated without reducing the efficiency of the entire parallel computer system.

[0032]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a parallel computer system to which the present invention is applied.

The parallel computer system in this embodiment is assumed to be a system consisting of a hierarchical torus network having a plurality of processors connected in an annular shape and having a plurality of layers. Will describe a single layer network for convenience.

In FIG. 1, 1 is a parallel computer system,
2 is a processor A, 3 is a processor B, 4 is a processor C, 5 is a data network, 6 is another network,
Reference numeral 7 is an element network, and 8 is a programmable switch.

In the parallel computer system of this embodiment,
As shown in FIG. 1, the processor A2 is a processor that does not have an interface to an input / output device (not shown), and includes a processor B3 and a processor C4.
Is a processor having an interface to input / output devices.

The processor B3 is a management processor for the element network 7, and the processor C4 is a management processor for the element network 7 in the highest hierarchy.

As shown in FIG. 1, the processor A2, the processor B3, and the processor C4 are connected to the data network 5.

At the same time, the type of communication for executing the separate system network 6 interconnecting the processors A2, B3, and C4 by the programmable switch 8 attached to the processors A2, B3, and C4. It is provided as a network having a variable structure in which the connection form can be dynamically changed in accordance with the above.

In the communication processing relating to the input / output processing, the separate system network 6 communicates a large amount of data to the processors B3 and C4 having the interface to the input / output device.

Further, in order to realize high-speed transfer of a large amount of data, the basic type of the separate system network 6 has a torus type which is an isotropic connection having the simplest structure and the short wiring length between the processors as its elements. Is a hierarchical torus type that is a hierarchical combination of.

The element network 7 includes one of a processor B3 and a processor C4 having an interface to an input / output device, and the processor B3 and the processor C4 manage the structure of the element network 7.

That is, in accordance with an instruction issued from the processor B3 and the processor C4 to the programmable switch 8 in the other processor A2, the connection form is changed according to the type of communication for executing the connection of the element network 7 to the processor group. You can

The processor A2 connected to each element network 7 can call the processor B3 and the processor C4, which are management processors.

The processor C4, which is the management processor of the element network 7 of the highest hierarchy, is provided with a console display (not shown) as a management processor of the entire parallel computer system, and the hardware of the parallel computer system in this embodiment is used. It has a function of adjusting the overall wear.

Further, each processor (processors A2 and B)
3, C4) is for accepting a connection form change request for executing high-priority communication, while relatively low-priority communication such as communication processing related to input / output processing is being executed in the separate system network 6. , Has a function of performing communication interruption processing.

As a result, the data network 5 of the main system is provided for data communication for moving the calculation target data that frequently occurs in any calculation process due to the fact that the memories are distributed among the processors. It can be used exclusively, regardless of the communication status of this large amount of data,
Communication processing, broadcasting processing, input / output processing, failure processing, etc. of the control system can be efficiently executed in parallel with the calculation processing.

The main system data network 5 is
High-performance data transfer can be realized by performing a design optimized for mass data communication between two processors.

Further, even in the conventional parallel computer system, although a separate network for hardware adjustment and diagnosis is provided, according to this embodiment, adjustment,
The separate system network 6, which was used only for diagnosis, can be utilized during normal operation, which is economical.

Details of the main parts of the parallel computer system of this embodiment will be described below.

FIG. 2 and FIG. 3 are diagrams showing a concrete configuration example of each processor of the present embodiment, and FIG. 2 is a diagram showing a configuration example of the processor A2 having no interface to the input / output device. 3 is a diagram showing a configuration example of the processor B3 and the processor C4 having an interface to the input / output device.

As shown in FIGS. 2 and 3, each processor (processors A2, B3, C4) performs arithmetic processing using memories 21 and 31 for storing data and the data stored in the memories. A communication control unit 2 that controls the interface between the units 20 and 30 and the networks 5 and 6.
2, 32, clocks 24, 34 that each processor has independently
And an input / output control unit 35 that serves as an interface to the input / output device, and programmable switch units 23 and 33 that control connection with the separate network 6.

It is assumed that the clocks 24 and 34 and the input / output control unit 35 are connected to the communication control units 22 and 32.

FIG. 4 is a diagram showing an example of the configuration of the element network 7 that constitutes each layer of the separate network 6 having the layer structure of this embodiment.

In FIG. 4, reference numerals 22 and 32 denote communication control units,
23 and 33 are programmable switch units, 35 is an input / output control unit, 40 is a common line, 41 is a call line, 42 is a reset line, and 43 is an upper layer element network.

As shown in FIG. 4, the element network 7
Are common line 40, call line 41, and reset line 42.
And is managed by a processor B3 having an interface to an input / output device.
The remaining processor is composed of the processor A2 having no interface to the input / output device.

The upper layer element network 43 has, as a component, a processor B3 that connects the upper layer element network 43 and the lower layer element network 7 and manages the lower layer element network 7.

The common line 40 is wired in a torus type having a short wiring length because the data network 5 in this embodiment is also used for communication of a large amount of data, but it depends on the type of communication performed on the element network 7. , A connection state with the processors A2 and B3, and a signal line group in which the meaning of the signal line is changed.

The call line 41 notifies the processor B3, which is the management processor, that the processor A2 connected to the element network 7 has made a connection form change request or has received a request and made a connection form change. It is for.

The reset line 42 receives a connection form change request from the call line 41 or the upper layer element network 43, and notifies the connection processor of the connection form to be changed next with respect to the connection state of the common line 40. A signal line for instructing the programmable switch units 23 and 33 to change to a form, for example, a bus type 62 (see FIG. 6C).

FIG. 5 is a diagram showing an example of the configuration of a programmable switch unit associated with each processor of this embodiment.

In FIG. 5, the programmable switch unit 33 of the processor B3 is shown as an example.

As shown in FIG. 5, the programmable switch section 33 comprises a communication control section 32, a selector 330 for selecting a connection relation between the common line 40, and a control section 331 for controlling the selector 330. It

A selector 332 is provided as an interface with the upper layer element network 43.
As a connection between the upper and lower layers, the selector 330 and the selector 332 are connected via a relay FIFO (First-In-First-Out: first-in first-out queue) 333.

Further, the selector 330 and the selector 3
The 32 includes FIFOs 334 and 335 for changing the connection form of the element network 7 according to the type of communication.

FIG. 6 is an explanatory diagram for explaining the connection pattern of the separate network of this embodiment.

As shown in FIG. 6A, the selector 330
Is provided with a relay FIFO 334, and changes the connection between the common line 40 and the connection line 60 to the communication control unit 22 into a plurality of connection patterns.

FIGS. 6B to 6G are views showing connection patterns. FIG. 6B is a torus type 61, and FIG. 6C is a bus type 6.
2, (D) is 1: 1 (connection) type 63, (E) is 1: 1
(Unconnected) type 64a and 64b (F) is an inter-tier connection type 65, and (G) is a bus (at the time of changing the connection form) type 66
Is.

Next, a procedure for performing communication using the separate system network 6 accompanied by the dynamic change of the connection form will be described.

FIG. 7 is a diagram showing a time chart of the procedure for changing the connection form in the single element network of this embodiment.

Below, FIG. 4 and FIG.
Description will be made in correspondence with the time chart shown in FIG.

As shown in FIG. 7, among a plurality of processors, a processor (for example, processor A2)
If the need for higher priority communication arises, this processor A2 will use the element network 7 to which it is connected.
"1" is sent as a request signal to the call line 41 (time chart 70).

The management processor (for example, the processor B3) having received the signal of the call line 41 sends "1" as a request read signal to the reset line 42 to make a connection form change request of the element network 7 (time chart 71). ).

When the processor A2, which is the source of the connection form change request, and the other processors connected to the element network 7 complete the preparation for the connection form change, "1" is sent to the call line 41 as a preparation completion signal. Is transmitted (time chart 72).

Here, the processor B3 uses the reset line 4
By returning the signal of 2 from "1" to "0",
The programmable switch 330 is operated to change the connection form (for example, change to the bus type 51) (time chart 71).

After that, the processor B3 transmits the communication request register 33 of the processor A2, which is the source of the connection form change request.
7 (see FIG. 5) is read, a bit pattern corresponding to the connection form suitable for the communication type is placed on the common line 40 (not shown), and broadcast to all the processors connected to the element network 7.

Then, all the processors connected to the element network 7 read this bit pattern (time chart 73), and their own status register 3
By writing in 36 (time chart 74), the connection form changing process of the element network 7 ends. Then, after the change of the connection form, the requested communication process is executed.

Note that when low-priority communication is being executed when changing the connection form of the element network 7, interruption processing 701 such as saving interruption information to the memory is performed during the request read preparation period.

After the communication processing is completed, the value of the status register 339 of the used element network 7 is reset to unused in the same procedure as when the communication is started.

FIG. 8 is a diagram showing a time chart when the connection form of the upper layer network is changed by a request from the lower layer network in the layered network of this embodiment.

Below, FIG. 4 and FIG.
Description will be made in correspondence with the time chart shown in FIG.

As shown in FIG. 8, first, the processor (for example, the processor A2) connected to the element network 7 which is a lower layer network makes a connection form change request of the element network 7, and the element network 7
The procedure until the management processor (for example, the processor B3) changes the connection form is the same as the procedure shown in FIG. 7, and the description thereof will be omitted (time charts 80 to 8).
3).

In the time chart 81, the processor B3 resets the signal on the reset line 42 from "1" to "0" and then requests the call line 41 to change the connection form of the upper layer network 43. 1 ”is transmitted (time chart 84).

Further, the management processor (for example, the processor C of the upper layer network 43 that receives this notification)
4), but the procedure until the connection form is changed to all the processors connected to the upper layer network 43 is the same as the procedure shown in FIG. 7, and the description thereof will be omitted (time charts 84 to 88).

The connection form of the upper layer network 43 is changed, and the bit pattern corresponding to the connection form is written in the status 336 by all the processors connected to the element network 7 of the lower layer to execute all the connection form changing processes. The process ends (time chart 89). Then, after the change of the connection form, the requested communication process is executed.

After the communication processing is completed, the value of the status register 339 of the used element network 7 is reset to unused in the same procedure as when the communication is started.

Note that, as in the case of FIG. 7, when low priority communication is being executed when changing the connection form of the element network 7 and the upper layer network 43, the interruption information memory is stored during the request read preparation period. A suspending process 801 such as saving to a file is performed.

FIG. 9 is a diagram showing a time chart when the connection form of the lower layer network is changed in response to a request from the upper layer network in the layered network of this embodiment.

The connection form changing process will be described below with reference to FIGS. 4 and 5 and the time chart of FIG.

As shown in FIG. 9, first, a request signal "1" is sent from the processor (for example, the processor B3) connected to the upper layer network 43 to the call line 41 as a connection form change request (time Chart 90).

Then, the processor (for example, the processor C4) which manages the upper layer network 43.
Receives this signal and sends out the request read preparation signal “1” to the reset line 42 (time chart 9
1).

The processor B3 sends the preparation completion signal "1" to the call line 41, and reads the bit pattern corresponding to the changed connection form sent on the common line 40 (time chart 93).

As a signal for transmitting this bit pattern to the lower layer, the request transmission signal "1"
Is transmitted to the common line 40 (time chart 94).

The management processor (for example, the processor B3) of the element network 7 in the lower hierarchy which receives the request transmission signal is compared with the other processors (for example, the processor A2) connected to the element network 7.
The write preparation signal “1” is broadcast and notified to the reset line 42 (time chart 95).

When the processor A2 connected to the element network 7 completes the preparation for writing the bit pattern corresponding to the connection mode to be changed, it sends a write preparation completion signal "1" to the reset line 42 (time chart 9
6), the corresponding bit pattern is written from the common line 40 to its own status 336, and the process ends (time chart 97).

In FIG. 9, as in the case of FIGS. 7 and 8, when changing the connection form of the element network 7 and the upper layer network 43, if low priority communication is in progress, request read preparation is performed. During the period, the interruption processing 901 such as saving the interruption information to the memory is performed.

FIG. 10 is a diagram showing a specific configuration example of a parallel computer system in which a parallel computer having a variable structure-based network according to an embodiment of the present invention is configured in a two-dimensional torus type.

In FIG. 10, 100 and 101 are separate networks, 102 is a host computer, 103 is a high-speed channel connecting the separate network 101 and the host computer 102, 104 is a processor D, 105 is a relay processor, and 106. Is the faulty processor E,
Reference numeral 107 is a management processor of the element network 101 to which the processor E106 is connected, and reference numeral 108 is an adjacent processor adjacent to the processor E106.

In the configuration example shown in FIG. 10, the data network 5 of the main system is a two-dimensional torus network, and the processors B3 and C4 having an interface to the input / output device are arranged in parallel with the y axis, and x It exists at the position of = 0.

All the processor groups existing at other positions are composed of the processor A2 having no interface to the input / output device.

The variable-structure another-system network 6 is composed of two layers in this configuration example.

The element network 100 of the upper hierarchy connects the processors B3 and C4 in parallel with the y-axis in a ring shape at a position of x = 0.

The management processor C4 of the upper layer element network 100 exists at the position of x = y = 0, and this processor C4 plays the role of the management processor of the entire system, and as one of the input / output devices, the console. A display (not shown) is connected.

The element networks 101 in the lower hierarchy are each a processor B located at x = 0 in parallel with the x-axis.
3, C4 and the processor A2 having the same y coordinate are connected in a ring shape. Each lower layer element network 101
The management processors B3 and C4 have a relay function between upper and lower layers.

The effects of the present invention other than those described above will be described below with reference to FIG.

(1) Large Scale Calculation In the parallel computer system shown in FIG. 10, when a large scale calculation is executed, the calculation process is executed by the processor A2 having no interface to the input / output device.

Therefore, the load on the processors B3 and C4 having the interface to the input / output device is extremely light except at the time of input / output processing for preparation for calculation before and after the calculation processing and at the time of outputting the calculation result. Further, it can be said that it is appropriate that the processors B3 and C4 having a large capacity memory manage the separate system networks 100 and 101 as compared with the processor A2 because they need to perform input / output processing.

(2) Substitute operation Utilizing that the load on the processors B3 and C4 is light, the processor B3 arranged at the same y coordinate is used as a substitute processor when a failure occurs in any of the processors A2. It can be operated using C4.

Now, assuming that a failure occurs in the processor E106 shown in FIG. 10, the data network 5 causes the communication control units 22 and 32 and the programmable switch unit 2 to operate.
Another system network 10 via 3, 33 (see FIG. 4)
Since it is directly connected to 0 and 101, the management processor 107, which is a substitute processor, automatically communicates with the faulty processor E106 from the adjacent processor 108.
Transfer to.

(3) Reduction of software processing Generally, in the distributed storage type parallel computer system, the processing involving the input / output of data from the input / output device is viewed from software as compared with the shared storage type computer system. The processing becomes complicated.

This is a network between the processor (for example, the processors B3 and C4) to which the input / output device is connected and the memory 21 (see FIG. 2) of the processor (for example, the processor A2) which performs calculation processing. This is for performing data communication via the via.

Particularly, in the processors B3 and C4,
Even though the data is not processed at all, the processing time related to the data transfer between the software controlling the input / output processing and the software controlling the communication is large, which is a problem.

This problem becomes more serious when high-speed input / output processing is performed. For example, as shown in FIG. 10, the parallel computer is not a stand-alone system.
Separate host computer 102 and high-speed channel 10
The problem becomes more serious in the case of high-speed inter-system communication in the system configuration connected by No. 3, or in the case of high-speed communication for outputting the moving image of the calculation result.

In such a case, in the parallel computer system of the present embodiment, as shown in FIG. 10, for example, when executing the input / output processing from the processor D104 to the host computer 102 without using the memory of the relay processor 105. 2 shows an example of the connection state of the separate network 101.

In the relay processor 105, the separate system network 101 and the high-speed channel 103 pass through the programmable switch section 33, the communication control section 32, and the input / output control section 35 (see FIG. 4), the arithmetic processing section 30 and the memory. Since it is directly connected without going through 31 (see FIG. 4), the processing of software in the relay processor 105 can be significantly reduced.

(4) Debugging work In the debugging work in the parallel computer system, it is necessary to know the communication state of the data from the other processor which is mainly communicated using the data network 5 of the main system. Can be obtained independently of the data network 5 that is the main system.

This independence is particularly important in the debugging work of software for controlling communication in the data network 5.

(5) Tuning Work In tuning work of software operating on a parallel computer, it is desirable to be able to display data relating to data communication efficiency in real time while the software is being executed.

In this case, it is possible to accurately output the monitor information in real time by avoiding that the communication for collecting the monitor information from each processor interferes with the communication accompanying the execution of the software. There are advantages.

(6) Collection of Fault Information When a fault occurs in a certain processor in the parallel computer system, it is necessary to perform a dump output process of the memory information of the processor in order to analyze the fault factor.

The communication processing of a large amount of data related to this failure will affect the operation of other normal processors, but by using the parallel computer system of this embodiment, this effect can be avoided. You can

Further, even if a failure occurs in the data network 5, there is an advantage that the failure information can be surely collected by using the parallel computer system of this embodiment.

[0123]

As described above, according to the present invention,
The following effects can be obtained.

(1) Communication of various information such as high-priority communication, broadcast-type communication, debug information communication, reset request information communication, monitor information communication, etc. without hindering transmission / reception of calculation target data Can be done efficiently.

(2) It is possible to efficiently perform communication of various information such as communication of various input / output data and communication of control information without reducing the efficiency of the entire parallel computer system.

(3) When a fault occurs in the processor in the parallel computer system, the processor having the interface can be substituted, and when the fault occurs in the data network, the fault information can be obtained by using the separate system network. It can be collected reliably.

Further, (4) communication other than transmission / reception of a large amount of data to be processed, considering that the transfer data length is short, the communication frequency is low, or the priority is low, these plural types of communication are Physically realizing it with a single network has an economic effect.

[Brief description of drawings]

FIG. 1 is a system configuration diagram showing a configuration of an embodiment of a parallel computer having another system network of a variable structure to which the present invention is applied.

FIG. 2 is a block configuration diagram showing a configuration of a processor having no interface to an input / output device of the present embodiment.

FIG. 3 is a block configuration diagram showing a configuration of a processor having an interface to an input / output device of this embodiment.

FIG. 4 is an explanatory diagram for explaining another system network of the present embodiment.

FIG. 5 is an explanatory diagram for explaining a programmable switch unit of the present embodiment.

FIG. 6 is an explanatory diagram for explaining a connection pattern of another system network of the present embodiment.

FIG. 7 is a time chart showing a connection change procedure of a single element network according to the present embodiment.

FIG. 8 is a time chart showing a procedure when a connection change request is issued from a processor of a lower layer in the layered network of the present embodiment.

FIG. 9 is a time chart showing a procedure at the time of a connection change request from a processor in an upper layer in the layered network of this embodiment.

FIG. 10 is a diagram showing a specific configuration example of a parallel computer system in which a parallel computer having a variable structure-based network according to an embodiment of the present invention is configured in a two-dimensional torus type.

[Explanation of symbols]

1 ... Parallel computer system having another system network of variable structure, 2 ... Processor A, 3 ... Processor B, 4 ...
Processor C, 5 ... Data network, 6 ... Separate system network, 7 ... Element network, 8, 23, 33 ...
Programmable switch section, 20, 30 ... Arithmetic processing section,
21, 31 ... Memory, 22, 32 ... Communication control unit, 35 ...
Input / output control unit, 40 ... Common line, 41 ... Call line, 42 ...
Reset line, 43 ... Upper layer element network.

Claims (3)

[Claims] 1. An information processing system comprising: a plurality of processors each having a memory; and a network connecting the plurality of processors to each other, and transmitting and receiving a plurality of types of information including control information between the plurality of processors. A parallel computer to perform, the network comprises at least a data network for transmitting and receiving calculation target data, and a separate network for transmitting and receiving at least control information between the plurality of processors, the plurality of processors, A parallel computer having a variable structure-based separate network having a programmable switch that changes a connection form with the separate network according to the type of information transmitted and received between a plurality of processors. 2. At least one of the plurality of processors has an interface for accessing an input / output device, and the basic network is a torus type for connecting the different system network in a ring shape between the plurality of processors. 2. The parallel computer having a variable structure-based sequence network according to claim 1, wherein the processor having a connection and managing the connection form of the plurality of processors and the different-system network. 3. The separate series network, which is connected by using the torus type as a basic type, is connected as a hierarchical torus type including a plurality of layers, and the processor having the interface connects the plurality of processors with the different system network. The parallel computer having a series network according to variable structure according to claim 2, wherein the connection form is managed.