JPH0722819A - Hybrid integrated circuit - Google Patents

Abstract

PURPOSE:To easily adjust a circuit to an optimum value by providing a second micro strip line having a preliminarily determined shape where an impedance adjusting element is formed on the dielectric having a second dielectric constant lower than a first dielectric constant. CONSTITUTION:An adjustment part 8 is provided with a substrate 81 using a dielectric of, for example, Teflon (epsilonr=2 to 3) whose dielectric constant is lower than the dielectric constant (epsilonr=8 to 10) of a substrate 3 and a ladder part 82 which has bars (d), (e), and (f) for adjustment formed as micro strip lines on the substrate 81. The substrate 81 is adhered to Line substrate by an adhesive or the like, and the ladder part 82 is connected to micro strip lines 6 by soldering. Since the dielectric constant of the substrate 81 is 1/3 to 1/5 of that of the substrate of the base, the electric length of the ladder part 82 is 1/3<1/2> to 1/5<1/2> of that of the adjustment part on the substrate though micro strip lines on these substrates have the same physical length. Consequently, the electric length is changed by about 1/2 step, and fine adjustment is possible.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hybrid integrated circuit, and more particularly to a high frequency hybrid integrated circuit used in a transmitter / receiver for mobile communication.

[0002]

2. Description of the Related Art A conventional hybrid integrated circuit of this type is, for example, soldered on a heat sink 4 as shown in FIGS. 3A and 3B, which are plan views and XY sectional views thereof. A microstrip line 6 formed on a substrate 3 such as a ceramic having a dielectric constant (εr) of 8 to 10, chip resistors R1 to R4 mounted on the microstrip line 6, chip capacitors C1 to C8, and through holes 7. Through the heat sink 4
Transistors 1 and 2 soldered to and mounted on substrate 3
And a plurality of leads 5 for connecting an external circuit. The output side microstrip line 6 of the transistor 2 is provided with a ladder-shaped adjusting circuit 9 for matching the output impedance of the transistor 2.

The operation of the conventional hybrid integrated circuit will be described. The adjustment circuit 9 shown in detail in FIG. 4A constitutes a capacitor C7 and an LC resonance circuit. The output impedance of the transistor 2 and the external circuit are as follows. Match the circuit. That is, in FIG. 4 (A), the bars a, b, and c of the adjusting circuit 9 are sequentially cut so that L of the adjusting circuit 9 is cut.
The C component becomes large, and the output impedance (A of the transistor 2 on the Smith chart shown in FIG.
The point moves in the inductive (+ xj) region in the direction of the point B and changes to the capacitive (−xj) region side (C direction). Therefore, the impedance matching can be adjusted without changing, that is, replacing the capacitance value of the chip capacitor C7.

The above impedance adjusting method is a method of performing this impedance adjustment by cutting a part of an impedance adjusting open stub provided in a microstrip line described in Japanese Patent Application Laid-Open No. 61-133702. It is a variation.

[0005]

In the conventional hybrid integrated circuit described above, since the dielectric constant of the substrate is large, the interval between the bars to be cut for adjusting the adjusting circuit is the practical minimum value.
There is a drawback that the amount of change in impedance is large and it is difficult to adjust to the optimum value of the circuit even if it is reduced to less than 00 μm.

[0006]

SUMMARY OF THE INVENTION A hybrid integrated circuit of the present invention is used for input / output impedance matching with a high frequency semiconductor device including a plurality of peripheral circuit elements mounted on one main surface of a dielectric substrate having a first dielectric constant. Including an impedance adjusting element of the first
And a signal transmission path including an input / output circuit of the high-frequency semiconductor device formed of the microstrip line, the impedance adjusting element having the first
The second microstrip line having a predetermined shape is formed on a dielectric having a second dielectric constant lower than the dielectric constant.

[0007]

Embodiments of the present invention will now be described with reference to the drawings. Referring to FIG. 1, which is a plan view of an embodiment of the present invention, the hybrid integrated circuit of this embodiment is configured such that the constituent elements 1 to 7, C1 to C7, and R1 of the conventional hybrid integrated circuit described above.
In addition to ~ R4, an adjusting unit 8 is provided instead of the conventional adjusting unit 9.

Referring to FIG. 2 showing details of the adjusting unit 8 which is a feature of the present invention, the adjusting unit 8 has a dielectric constant lower than that of the substrate 3 (εr = 8 to 10), for example, a Teflon system (εr =). Substrate 81 using the dielectric material of 2-3) and substrate 8
1 and a ladder section 82 having adjustment bars e, f, g formed as microstrip lines as in the conventional adjustment section 9. The substrate 81 is bonded to the substrate 3 with an adhesive or the like, and the ladder portion 82 is connected to the microstrip line 6 by soldering.

In operation, since the substrate 81 has a dielectric constant of about ⅓ to ⅕ as compared with the base substrate 3, even if the microstrip lines on these substrates have the same physical length, the ladder section 82 is provided. Has an electric length of 1 / √3 to 1 / √5 of the electric length of the adjusting unit 9 on the substrate 3, and the average is about 1
/ 2. Therefore, the bars e, f, g of the ladder unit 82 for changing the physical length for impedance adjustment
Even if the interval is the same as the interval between the bars a, b, and c of the adjusting unit 9, if the other conditions are the same, the change in the electrical length is about 1/2 step of the conventional one, and a finer adjustment is possible. Is possible.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above-mentioned embodiments and various modifications can be made. For example, it is needless to say that the open stub as described in Document 1 may be used instead of the ladder section as long as it does not depart from the gist of the present invention.

[0011]

As described above, in the hybrid integrated circuit of the present invention, the impedance adjusting element is provided with an adjusting portion using a microstrip line formed on a dielectric material having a dielectric constant lower than that of the base substrate. With the provision, there is an effect that the amount of impedance change corresponding to the change in the physical length of the microstrip line is small, and the circuit can be easily adjusted to the optimum value.

[Brief description of drawings]

FIG. 1 is a plan view showing an embodiment of a hybrid integrated circuit of the present invention.

FIG. 2 is a plan view showing details of an adjusting unit in FIG.

FIG. 3 is a plan view and a cross-sectional view showing an example of a conventional hybrid integrated circuit.

4A and 4B are a plan view showing details of an adjustment unit in FIG. 3 and a Smith chart showing an example of adjustment.

[Explanation of symbols]

 1, 2 Transistor 3,81 Substrate 4 Heat sink 5 Lead 6 Microstrip line 7 Through hole 8,9 Adjustment part 82 Ladder part C1 to C7 Chip capacitors R1 to R4 Chip resistance

Claims (3)

[Claims] 1. A high-frequency semiconductor device including a plurality of peripheral circuit elements mounted on one main surface of a dielectric substrate having a first dielectric constant,
In a hybrid integrated circuit including a signal transmission path including an input / output circuit of the high-frequency semiconductor device, which includes an impedance adjustment element for input / output impedance matching, and is formed of a first microstrip line, the impedance adjustment element includes: A hybrid integrated circuit comprising a second microstrip line of a predetermined shape formed on a dielectric having a second dielectric constant lower than the dielectric constant. 2. The impedance adjusting element is formed by the second microstrip line, and two first lines having a predetermined width and arranged in parallel in the longitudinal direction are short-circuited to these two first lines. A ladder-shaped stub circuit composed of a plurality of lateral second lines arranged so that impedance adjustment is performed by cutting the plurality of second lines one by one. The hybrid integrated circuit according to claim 1, wherein: 3. The impedance adjusting element comprises an open stub having a predetermined shape, which is formed by the second microstrip line, and the open stub is based on a predetermined adjustment rule.
The hybrid integrated circuit according to claim 1, wherein the impedance adjustment is performed by cutting out step by step.