JPH07226677A - Phase detector, (pi/2) phase converter and digital signal demodulator - Google Patents

Abstract

PURPOSE:To output the voltage according to the phase difference of an I signal and a Q signal to be input signals with high accuracy, without generating an error of a phase rotation component theta in the output voltage of a phase detector. CONSTITUTION:Two phase detection circuits are used. Of the I signal and Q signal outputted by a variable phase two-distribution circuit, the I signal is inputted in the transistor for mixer of a first detection circuit 3 and the buffer transistor of a second detection circuit 4. The Q signal is inputted in the buffer transistor of the first detection circuit 3 and the transistor for mixer of the second detection circuit 4. The output voltage of the first and second detection circuits 3 and 4 is synthesized in a synthetic circuit 5 and the voltage is defined as phase detection output voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a PLL (Phase Locked)
Loop: a phase detector used in a phase synchronization loop circuit,
The present invention relates to a (π / 2) phaser configured by using the phase detector, and a digital signal demodulating device configured by using the (π / 2) phaser.

[0002]

2. Description of the Related Art FIG. 9 is a circuit diagram showing a general phase detector used in a PLL control (π / 2) phase shift circuit.
As can be seen in the figure, the phase detector includes a transistor 5
2 to 57, a constant current source 65, and load resistors 58 and 59, which are Gilbert type detectors. The operation of this circuit will be briefly described.

A signal 49 from the signal generating circuit 1 is I (Inphas) having a phase difference of approximately 90 degrees from each other in a 90 degree phase dividing circuit 2.
e) signal (60, 61) and Q (Quadrature) signal (62,
63). Here, the signals 60 and 61 and the signals 62 and 63 are differential signals. Next, the I signal is input to the mixer transistors 52 to 55 of the phase detector, and the Q signal is input to the buffer transistors 56 and 57 after the direct current level is adjusted by the level shift circuit 64. Now i
I (t) and Q (t) are assumed as the signals and Q signals as follows.

I (t) = A1 * cos (wt + φ1): A1, A2 amplitude, w angular frequency, φ1, φ2 phase, t time Q (t) = A2 * cos (wt + φ2) Equation (1 )

The phase detection voltage Vout obtained from the output terminal 66 or 67 is given as follows, ignoring the initial DC level at the terminals 66 and 67. Vout = I (t) * Q (t) = A1 * cos (wt + φ1) * A2 * cos (wt + φ2) = A * {cos (2wt + φ1 + φ2) + cos (φ1-φ2)}… Formula (2) where A = A1 * A2 / 2

When a low-pass filter is connected to the terminals 66 and 67, the first term is deleted and Vout = A * cos (φ1-φ2) (3) is obtained.

FIG. 10 is a characteristic diagram showing the output (Vout) characteristic of the phase detector shown in FIG. Phase difference φ1-φ on the horizontal axis
2, the output voltage Vout is plotted on the vertical axis. The curve indicated by the dotted line is the output voltage given by the above equation (3), which gives the characteristic when the phase detector shown in FIG. 9 operates ideally.

In this case, the output voltage takes the maximum and minimum values when the phase difference is 0 or ± π, and the phase difference is ± π / 2.
Becomes 0 when. Therefore, the output voltage of the phase detector (terminals 66 and 67 in FIG. 9) is set to 90 degrees as a variable phase circuit.
° Phase control terminal of the phase distribution circuit 2 (terminal 29 in FIG. 9,
By constructing a loop for negative feedback to 30), I
P that locks the phase difference between the Q and Q signals to π / 2 accurately
The LL loop can be configured (in this way the PLL
The entire circuit that constitutes the loop is called a PLL control (π / 2) phaser.

However, in practice, the level shift circuit 64 for matching the DC voltage with the phase detector, the phase delay due to the transistors 56, 57, etc. in the phase detector, and the values of the load resistors 58, 59 cause a phase difference. A phase rotation of θ occurs in the output phase of the detector. For example, the mixer transistor 52 to the input I signal (initial phase φ1)
55 and the load resistors 58 and 59, the phase rotation is θ1, the phase rotation by the level shift circuit 64 for the Q signal (initial phase φ2) is θ2, the phase rotation by the buffer transistors 56 and 57 is θ3, and the mixer transistors 52 to 55.
And the phase rotation by the load resistors 58 and 59 is θ4,
The phase detector outputs I (t) and Q (t) rotate in phase and become I (t) 'and Q (t)' in the phase detector.

I (t) '= A1 * cos (wt + φ1 + θ1) Q (t)' = A2 * cos (wt + φ2 + θ2 + θ3 + θ4) Equation (4)

Therefore, the actual phase detection output voltage is given by the following equation. Vout = I (t) '* Q (t)' = A1 * cos (wt + φ1 + θ1) * A2 * cos (wt + φ2 + θ2 + θ3 + θ4) = A * (cos {2wt + (φ1 + θ1 ) + (φ2 + θ2 + θ3 + θ4)} + cos {(φ1 + θ1)-(φ2 + θ2 + θ3 + θ4)}]

By passing this Vout through a low-pass filter, the first term is deleted, and Vout = A * cos (φ1-φ2 + θ) Equation (5) where θ = θ1- (θ2 + θ3 + θ4) can get.

The output voltage given by the above equation (5) is shown in FIG.
Since the characteristics are represented by a solid line at 0, when the PLL loop is applied, the I signal and the Q signal are synchronized with each other with a phase difference deviating from π / 2 by θ. This phenomenon is due to the frequency of the signal (f = 2π
As w) becomes higher, the frequency band to be handled becomes higher and higher.
/ 2) It was an obstacle to the realization of a phase shifter.

[0014]

SUMMARY OF THE INVENTION According to the present invention, the phase rotation component θ shown in the equation (4) is added to the output voltage of the phase detector.
Does not occur, and the phase difference φ between the I and Q signals that are the input signals
A phase detector that outputs a voltage according to 1-φ2, a (π / 2) phase shifter configured by using the phase detector, and the (π /
2) It is an object to provide a digital signal demodulation device configured by using a phase shifter.

[0015]

The phase detector according to the present invention uses two phase detection circuits. The I signal from the 90 ° phase distribution circuit (variable phase 2 distributor) is input to the mixer transistor of the first detection circuit and the buffer transistor of the second detection circuit. On the other hand, the Q signal from the 90 ° phase distribution circuit (variable phase 2 distributor) is input to the buffer transistor of the first detection circuit and the mixer transistor of the second detection circuit. The output voltages of the first and second detection circuits are combined to obtain a phase detection output voltage. Thus, the phase detector according to the present invention is realized.

If such a phase detector is obtained, a PLL control (π / 2) phase shifter can be constructed by applying a negative feedback control to the 90 ° phase distribution circuit using the phase detection output voltage. Further, a digital signal demodulating device can be constructed by incorporating the I signal and the Q signal, which are the outputs of the PLL controlled (π / 2) phase shifter, into the synchronous detection circuit and using them.

[0017]

The phase detector according to the present invention will be described. Now, it is assumed that both the phase rotation amount of the first detection circuit and the phase rotation amount of the second detection circuit are equal. The I signal and the Q signal that have undergone phase rotation in the first detection circuit are I (t) ′ and Q (t) ′, and the I signal and the Q signal that have undergone phase rotation in the second detection circuit are I (t) ′ and Q (t) ′.
(t) ”, Q (t)”,

I (t) '= A1 * cos (wt + φ1 + θ1) Q (t)' = A2 * cos (wt + φ2 + θ2 + θ3 + θ4) Equation (6) I (t) ”= A1 * cos (wt + φ1 + θ2 + θ3 + θ4) Q (t) ”= A2 * cos (wt + φ2 + θ1) Equation (7).

Therefore, the output voltage Vout1 of the first detection circuit
And the output voltage Vout2 of the second detection circuit is given by the following equation, ignoring the high frequency component.

Vout1 = I (t) '* Q (t)' = A1 * cos (wt + φ1 + θ1) * A2 * cos (wt + φ2 + θ2 + θ3 + θ4) = A * cos {(φ1- φ2) + (θ1-θ2-θ3-θ4)} = A * cos (φ1-φ2 + θ) Equation (8)

Vout2 = I (t) ”* Q (t)” = A1 * cos (wt + φ1 + θ2 + θ3 + θ4) * A2: cos (wt + φ2 + θ1) = A * cos {(φ1- φ2)-(θ1-θ2-θ3-θ4)} = A * cos (φ1-φ2-θ) Equation (9)

When the detection voltage output Vout is the synthesis of the output voltages of the two detection circuits, Vout = Vout1 + vout2 = A * cos (φ1-φ2 + θ) + A * cos (φ1-φ2-θ) = 2A * cos θ * cos (φ1-φ2)… Given by equation (10).

In the above equation (10), since θ is a constant peculiar to the phase detection circuit, Acos θ is constant, and therefore Vout
Becomes an output voltage according to the phase difference φ1-φ2 between the input I and Q signals.

As described above, by combining two phase detection circuits to obtain a detection output, it is possible to realize a phase detector in which the influence of phase rotation due to the level shift circuit or the phase detection circuit is removed. A (π / 2) phase shifter configured by such a phase detector, and such (π /)
2) The digital signal demodulating device constructed by using the phase shifter becomes highly accurate.

[0025]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a phase detector according to the present invention. In FIG. 1, 135 and 136 are signal input terminals, 3 and 4 are phase detection circuits,
Reference numeral 5 indicates a synthesis circuit.

The phase detection circuits 3 and 4 are circuits having the same function and uniform characteristics, and the input terminal 1 of the phase detection circuit 3 is used.
01 and the input terminal 103 of the phase detection circuit 4 are terminals having the same function. Similarly, the input terminal 102 of the phase detection circuit 3 and the input terminal 104 of the phase detection circuit 4 are terminals having the same function. is there. The operation of this embodiment will be described below.

The I signal 105 having a phase of φ1 and the Q signal 106 having a phase of φ2 are input from the signal input terminals 135 and 136, respectively. The I signal 105 and the Q signal 106 are given as I (t) and Q (t) by the following equations, respectively.

I (t) = A1 * cos (wt + φ1): A1, A2 amplitude, w angular frequency, φ1, φ2 phase, t time Q (t) = A2 * cos (wt + φ2) Equation (11) )

Here, the input terminal 101 of the phase detection circuit 3
The signal input to the input terminal 103 of the phase detection circuit 4 is θ1 due to the resistance and capacitance components inside the phase detector.
Phase rotation only, while the input terminal 10 of the phase detection circuit 3
2 and the signal input to the input terminal 104 of the phase detection circuit 4 are assumed to rotate in phase by θ2 due to the resistance and capacitance components.

Now, the I signal input from the input terminal 101 and rotated in phase by the phase detection circuit 3 is I (t) ', input terminal 1
02 is input from the phase detection circuit 3, and the phase signal is rotated by the phase detection circuit 3 is Q (t) '. Input terminal 103 is input, and the phase signal is rotated by the phase detection circuit 4 is Q (t) ". The I signal that has been input and has undergone phase rotation in the phase detection circuit 4 is I
(t) ", I (t) ', Q (t)', I (t)", and Q (t) "are given by the following equations.

I (t) '= A1 * cos (wt + φ1 + θ1) Q (t)' = A2 * cos (wt + φ2 + θ2) I (t) "= A1 * cos (wt + φ1 + θ2 ) Q (t) "= A2 * cos (wt + φ2 + θ1)… Equation (12)

Therefore, the output voltage Vout1 of the phase detection circuit 3
And the output voltage Vout2 of the phase detection circuit 4, Vout1 = I (t) '* Q (t)' = A1 * cos (wt + φ1 + θ1) * A2 * cos (wt + φ2 + θ2) = A * [ cos (2wt + φ1 + φ2 + θ1 + θ2) + cos {(φ1-φ2) + (θ1-θ2)}}] Equation (13)

Vout2 = I (t) "* Q (t)" = A1 * cos (wt + φ1 + θ2) * A2 * cos (wt + φ2 + θ1) = A * [cos (2wt + φ1 + φ2 + θ1 + θ2) + cos {(φ1-φ2)-(θ1-θ2)}}] Equation (14) where A = A1 * A2 / 2.

When Vout1 and Vout2 are high-pass components removed by the low-pass filters 113 and 114, respectively, and synthesized by the synthesizing circuit 5, the phase detection output voltage 109 is given by the following equation.

Vout = Vout1 + Vout2 = A * cos {(φ1-φ2) + (θ1-θ2)}} + A * cos {(φ1-φ2)-(θ1-θ2)} = 2A * cos (θ1- θ2) * cos (φ1-φ2) Equation (15)

Since cos (θ1−θ2) in (15) above is a constant value that is unique to the phase detection circuits 3 and 4, the phase detection output voltage 109 is cos (φ1−φ2) (phase difference (φ1−φ1)). φ2) is 90
It is determined only by the change in the phase difference between the I signal and the Q signal of the phase shift distribution circuit 2.

FIG. 2 is a characteristic diagram showing the relationship between the phase difference (φ1-φ2) and the output voltage for the embodiment shown in FIG.
In FIG. 2, the solid line 6 indicates the output voltage 1 of the phase detection circuit 3.
07, the solid line 7 indicates the output voltage 1 of the phase detection circuit 4.
08 and the dotted line 8 show the characteristics of the output voltage 109 of the synthesizing circuit 5.

The output voltage 108 of the phase detection circuit 4 is ± (π
/ 2) + θ, and the output voltage 107 of the phase detection circuit 3 is ± (π / 2) −θ and the output voltage is 0 V.
The output voltage 109 of the combining circuit 5 has a phase difference (φ1-φ2) = ±
Good characteristics of 0 V at π / 2 are obtained.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention. In FIG. 3, a differential input terminal 137 composed of input terminals 135 and 135 ′ and a differential input terminal 138 composed of input terminals 136 and 136 ′ are shown, and 3 and 4 are phase detection circuits, respectively. Reference numeral 5 indicates a synthesis circuit.
The phase detection circuits 3 and 4 use double balance type phase detection circuits, and are circuits having the same function and uniform characteristics.

The phase detection circuit 3 comprises transistors 11 to 14 of the balance mixer section, load resistors 25 and 26, buffer transistors 15 and 16, a constant current source 23, and a bias terminal 50. Similarly, the phase detection circuit 4 includes: Transistors 17-20, load resistors 27, 2 in the balance mixer section
8, buffer transistors 21 and 22, constant current source 24,
It comprises a bias terminal 51.

The phase detection circuits 3 and 4 can easily obtain circuits having almost the same detection characteristics by forming the circuits close to each other when they are integrated into an IC. The circuit operation of this embodiment will be described in detail below.

The signals input from the differential input terminal 137 are I signals 33 and 34 having an output phase φ1, and the signals input from the differential input terminal 138 are Q signals 35 and 36 having an output phase φ2. . Where 33, 34 and 35,
Reference numerals 36 are differential signals having mutually opposite phases. I signal 3
3 and 34 are input to the balance mixer transistor units 11 to 14 of the phase detection circuit 3, and the phase detection circuit 4 as the I signals 39 and 40 via the DC level adjustment circuit 10.
Is input to the buffer transistor portions 21 and 22 of the.

Similarly, the Q signals 35 and 36 are input to the balance mixer transistor sections 17 to 20 of the phase detection circuit 4, and also the Q signal 3 via the DC level adjusting circuit 9.
7 and 38 are input to the buffer transistor units 15 and 16 of the phase detection circuit 3. In the phase detection circuit 3, the I signals 33 and 34 and the Q signals 37 and 38 are multiplied and output as phase detection voltages 41 and 42 having mutually opposite phases.

Similarly, in the phase detection circuit 4, the Q signal 3
5, 36 and I signals 39, 40 are multiplied and output as phase detection voltages 43, 44 having opposite phases. The phase detection voltages 41, 42, 43, 44 are input to the synthesizing circuit 5, voltage-synthesized, and output voltages 45, 46 are output to the terminal 3
It is output from 1 and 32.

As described above, the DC level adjusting circuits 9, 10 and the buffer transistors 15, 16, 21, 2 are also provided.
2. Due to the influence of the mixer transistors 11 to 14, 17 to 20, the load resistors 25, 26, 27, 28, etc., the phase detection output voltages 41, 42, 43, 44 include the phase error component θ, but the combination circuit By combining in 5, the phase error component θ
Can be canceled and an output voltage of cos (φ1-φ2) corresponding to the phase difference (φ1-φ2) of the input I and Q signals can be obtained from the output terminals 31, 32.

Therefore, by applying the PLL loop for controlling the phase shift amount of the 90-degree phase distribution circuit by the phase detection voltage from the output terminals 31 and 32, I of the output of the 90-degree phase distribution circuit 2 can be obtained.
A phase shift circuit can be obtained in which the phase shift difference (φ1−φ2) between the signal and the Q signal is exactly π / 2.

FIG. 4 is a circuit diagram showing a third embodiment of the present invention. Those having the same functions as those in FIG. 3 are designated by the same reference numerals and the description thereof will be omitted. In the present embodiment shown in FIG. 4, the double-balanced phase detection circuit 3 is composed of a constant current source 23, buffer transistors 15, 16 and mixer transistors 11-14, and the phase detection circuit 4 is a constant current source 24, a buffer transistor. 21, 22 and mixer transistors 17 to 20, and the phase detection circuit 3 and the phase detection circuit 4 have the same characteristics.

Further, the synthesis circuit 5 includes load resistors 25 and 26.
It is composed of The load resistors 2 have the common collectors of the mixer transistors 11 and 13 of the phase detection circuit 3 and the collectors of the mixer transistors 17 and 19 of the phase detection circuit 4.
On the other hand, the collectors of the mixer transistors 12 and 14 of the phase detection circuit 3 and the collectors of the mixer transistors 18 and 20 of the phase detection circuit 4 are connected in common to the load resistor 26. In the load resistors 25 and 26, the detection voltages of the phase detection circuit 3 and the phase detection circuit 4 are combined, and the terminal 3
The phase detection output voltage is output from 1 and 32.

According to this embodiment, the DC level adjusting circuits (level shift circuits) 9, 10, the buffer transistors 15, 16, 21, 22, the mixer transistors 11-1 are used.
The output voltages of the phase detection circuits 3 and 4 include the phase error component θ due to the influences of 4, 17 to 20, the load resistances 25 and 26, and the like. It can be canceled, and an output voltage of cos (φ1-φ2) corresponding to the phase difference (φ1-φ2) of the input I and Q signals is obtained from the output terminals 31, 32. Further, according to this embodiment, since the collectors of the phase detection circuits 3 and 4 are connected to synthesize the output voltage, it is also effective in simplifying the circuit configuration.

FIG. 5 is a circuit diagram showing a fourth embodiment of the present invention. This embodiment is the phase detection circuit 3 of the embodiment of FIG.
Alternatively, it is an embodiment in which 4 has another circuit configuration, and the terminal 1
26 and 127, and the terminals 128 and 12
9 is a circuit that detects the phase difference of the signal input from 9 and outputs it.

The circuit of this embodiment has buffer transistors 120 to 123 for input and mixer transistors 11 to 1 for input.
4, coupling resistance 132 of transistors 11 and 12, coupling resistance 133 of transistors 13 and 14, transistor 12
It is composed of a coupling resistor 134 of 0 to 123, load resistors 25 and 26, a power supply terminal 50, and constant current sources 124 and 125. By providing the coupling resistors 132, 133, and 134, respectively, the amplitude of the input signal can be suppressed to a small level, and thus the malfunction of the phase detection circuit at the time of excessive input can be prevented.

FIG. 6 is a block diagram showing an embodiment of a PLL control (π / 2) phase shifter constructed by using the phase detector according to the present invention. In FIG. 6, 1 is a signal generator, 2
Is a variable phase 2 divider (90 degree phase divider), 3 and 4 are phase detectors, and 5 is a combiner. The phase detection circuits 3 and 4 are circuits having the same function and having the same characteristics. The input terminal 101 of the phase detection circuit 3 and the input terminal 103 of the phase detection circuit 4 are terminals having the same function. The input terminal 102 of the phase detection circuit 3 and the input terminals 103 and 104 of the phase detection circuit 4 also have the same function. The circuit operation of this embodiment will be described below.

The signal 110 from the signal generator 1 is input to the variable phase 2 divider 2 and divided into two signals, an I signal 105 having a phase of φ1 and a Q signal 106 having a phase of φ2. As described in the embodiment of FIG. 1, the phase detection output voltage 109
Is determined only by the change of cos (φ1-φ2) (the phase difference (φ1-φ2) is the phase difference between the I signal and the Q signal of the variable phase 2 distributor 2). Therefore, by feeding back the phase detection output voltage 109 to the variable phase shift 2 divider 2, a highly accurate 90 degree phase shift in which the phase difference between the I signal and the Q signal of the variable phase 2 divider 2 is synchronized with π / 2. You get a bowl.

FIG. 7 shows the PLL control (π /
2) QPSK, MSK, configured by incorporating a phase shifter
It is a block diagram which shows the Example of the digital signal demodulation apparatus which demodulates a digital signal, such as QAM.

The blocks having the same functions as those of the embodiment of the PLL control (π / 2) phase shifter shown in FIG. 6 are designated by the same reference numerals and the description thereof will be omitted. In FIG. 7, 140 is a QPS, for example.
Input terminal for inputting K-modulated intermediate frequency signal, 14
1, 142 are synchronous detection circuits, 143, 144 are low-pass filters, 145 is a carrier recovery circuit,
Reference numerals 146 and 147 are amplifying circuits, and 148 and 149 are baseband output terminals.

The circuit operation of this embodiment shown in FIG. 7 will be described in detail below. QPSK input from the input terminal 140
The signal 150 is divided into two, and the synchronous detection circuits 141 and 1 are provided.
42 is input. In the synchronous detection circuit, the PLL control type 9
The signals are synchronously detected with the output signals 105 and 106 from the 0-degree phase shifter PS, and converted into an I signal 151 and a Q signal 152.

The I signal and the Q signal are input to low-pass filters 143 and 144, respectively, and after removing unnecessary wave signals, they become baseband I signal 153 and Q signal 154, which are output through amplifiers 146 and 147. Terminals 148, 1
It is output from 49 as a demodulation signal. Also, I signal, Q
The signal is also input to the carrier wave reproduction circuit 145, and the carrier wave reproduction signal 155 is fed back to the variable oscillator circuit 1 to form a PLL loop.

In the present embodiment, the synchronous detection circuit 14
Since the PLL-controlled 90-degree phase shifter shown in FIG. 6 is used as a signal source for supplying the quadrature signal to the signals 1 and 142, it is possible to supply a highly accurate 90-degree phase difference signal and to obtain a good digital signal. Signal demodulation can be performed.

FIG. 8 is a circuit diagram showing another embodiment of the present invention. This embodiment has substantially the same configuration as that of the embodiment shown in FIG. 3, and uses FETs instead of the bipolar transistors 11 to 22 of the embodiment of FIG. F
When GaAs FET is used as ET, there is an effect that the high frequency operation of the phase detection circuit becomes possible. Also, MO
When the SFET is used, a phase detection circuit effective in reducing power consumption can be obtained. The embodiment using the FET is shown in FIG.
Not only that, the same effect can be obtained by applying to FIG. 4 and FIG.

[0060]

As described above, according to the phase detector of the present invention, the variable phase 2 distribution circuit (90 degree phase distribution circuit).
By combining the outputs using two phase detection circuits that detect the phase difference between the I signal and the Q signal of the output of, the phase error component θ included in the phase detection circuit can be canceled, and the input from the combined output Phase difference between the I and Q signals (φ1-φ
A highly accurate output voltage of cos (φ1-φ2) according to 2) can be obtained.

Therefore, by applying a PLL loop for negative feedback control of the phase shift amount of the variable phase 2 distribution circuit with the phase detection voltage from the synthesis circuit, the I signal and the Q signal output from the variable phase 2 distribution circuit are shifted. A (π / 2) phase shift circuit in which the phase difference (φ1−φ2) is exactly π / 2 is obtained. It takes more (π / 2)
A highly accurate digital signal demodulator constructed by using a phase shift circuit can also be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a phase detector according to the present invention.

FIG. 2 is a phase difference (φ1-φ2) of the embodiment shown in FIG.
It is a characteristic view showing the relationship between the output voltage and.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a third embodiment of the present invention.

FIG. 5 is a circuit diagram showing a fourth embodiment of the present invention.

FIG. 6 is a PL configured by using the phase detector according to the present invention.
It is a block diagram which shows the Example of L control ((pi) / 2) phase shifter.

7 is a block diagram showing an embodiment of a digital signal demodulating device for demodulating a digital signal such as QPSK, MSK, QAM, which is configured by incorporating the PLL control (π / 2) phase shifter shown in FIG. .

FIG. 8 is a circuit diagram showing still another embodiment of the present invention.

FIG. 9 is a circuit diagram showing a general phase detector used in a PLL control (π / 2) phase shift circuit.

10 is a characteristic diagram showing an output (Vout) characteristic of the phase detector shown in FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Signal generator, 2 ... 90 degree phase distribution circuit (variable phase 2 divider), 3, 4 ... Phase detection circuit, 5 ... Synthesis circuit,
9, 10 ... DC level adjusting circuit, 11-22 ... Transistor, 23, 24 ... Constant current source, 25-28 ... Load resistance,
113, 114 ... Low-pass filter

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical display location H04L 27/14 27/227 9297-5K H04L 27/14 B 9297-5K 27/22 B

Claims (6)

[Claims] 1. A phase detector for detecting a phase difference between a first signal and a second signal, comprising first and second phase detection circuits and a combining circuit, wherein the first phase detection circuit is a first phase detection circuit. The first phase detection circuit has first and second input terminals and a first output terminal, and the second phase detection circuit has third and fourth input terminals and a second output terminal. The third input terminal corresponds to the first input terminal of the first phase detection circuit, and the fourth input terminal of the second phase detection circuit is the second input terminal of the first phase detection circuit. Correspondingly, the second output terminal of the second phase detection circuit corresponds to the first output terminal of the first phase detection circuit, and the first signal is applied to the first and fourth input terminals. Input, the second signal is input to the second and third input terminals, and the first and second phase detection signals are input. A phase detector characterized in that the output of the circuit is combined by the combining circuit to obtain a phase detection output. 2. The phase detector according to claim 1, wherein the first phase detection circuit includes at least first to sixth transistors, first and second load resistors, and a constant current source, The first and second transistors have a common emitter (or source), the third and fourth transistors have a common emitter (or source), and the first and third transistors have collectors. (Or drain) in common, the second and fourth transistors in common in collector (or drain), the first and fourth transistors in common in base (or gate), The second and third transistors have a common base, and the collector (or drain) of the fifth transistor is connected to the emitters (or sources) of the first and second transistors. , The collector (or drain) of the sixth transistor is connected to the emitters (or sources) of the third and fourth transistors, and to the emitters (or sources) of the fifth and sixth transistors. The constant current source is connected, the first load resistor is connected to the collectors (or drains) of the first and third transistors, and the collector (or drain) of the second and fourth transistors is connected to the first load resistor. Two load resistors are connected, the second phase detection circuit has the same configuration as the first phase detection circuit, and the first input terminal includes first and second differential input terminals, The first differential input terminal is connected to the bases (or gates) of the first and fourth transistors, and the second differential input terminal is the bases of the second and third transistors. -Connected to the ground (or gate), in front The second input terminal is composed of third and fourth differential input terminals, the third differential input terminal being connected to the base (or gate) of the fifth transistor, The fourth differential input terminal is the base (or gate) of the sixth transistor.
The first output terminal is composed of first and second actuation output terminals, and the first actuation output terminal is connected to collectors (or drains) of the first and third transistors. Connected,
The phase detector, wherein the second operation output terminal is connected to the collectors (or drains) of the second and fourth transistors. 3. The phase detector according to claim 2, wherein the second phase detection circuit includes at least first to sixth transistors and a constant current source, and the first and second transistors are emitters. (Or source) in common, the third and fourth transistors have a common emitter (or source), the first and third transistors have a common collector (or drain), and The second and fourth transistors have a common collector (or drain), the first and fourth transistors have a common base (or gate), and the second and third transistors have a base. (Or gate) in common, the collector (or drain) of the fifth transistor is connected to the emitters (or sources) of the first and second transistors, and The collector (or drain) of the first transistor is connected to the emitters (or sources) of the third and fourth transistors, and the emitters (or sources) of the fifth and sixth transistors are connected.
Connected to the constant current source, the first load resistor of the first phase detection circuit is connected to the collectors (or drains) of the first and third transistors, and the second and fourth The second load resistance of the first phase detection circuit is connected to the collector (or drain) of the transistor, and the collectors (or drains) of the first and third transistors and the collectors of the second and fourth transistors are connected. (Or drain) is a phase detection output, a phase detector. 4. The phase detector according to claim 2, wherein the first phase detection circuit includes at least first to eighth transistors, first and second load resistors, and first and second load resistors. 2 constant current source, the emitter (or source) of the first transistor is connected to the collector (drain) of the fifth transistor, and the emitter (or source) of the second transistor.
Is the collector (or drain) of the sixth transistor
The emitter (or source) of the third transistor is connected to the collector (or drain) of the seventh transistor, and the emitter (or source) of the fourth transistor is connected to the eighth transistor. Connected to the collectors (or drains) of the transistors, the fifth and sixth transistors have a common base (or gate), the sixth and eighth transistors have a common base (or gate), and 5 and 6
Common emitter (or source) of
The emitters (or sources) of the seventh and eighth transistors are commonly used, and the first and second transistors couple the emitters (or sources) with a first coupling resistor, and the third and Fourth
The second transistor is a second coupling resistor, and
The fifth and seventh transistors are coupled to the emitter (or source) by a third coupling resistor, and the emitters (or source) of the fifth and sixth transistors are coupled to each other.
Phase detection circuit, wherein the first constant current source is connected to the second constant current source and the emitters (or sources) of the seventh and eighth transistors are connected to the second constant current source. vessel. 5. At least a signal generator, a variable phase shifter,
In a PLL control (π / 2) phase shifter including a phase detector that detects a phase difference between a first signal and a second signal, the signal generator outputs a third signal, and the variable phase shifter Inputs the third signal, distributes and outputs the first and second signals, and the phase detector outputs the first and second signals.
And a first output terminal, the first phase detection circuit has first and second input terminals, and the second phase detection circuit has third and fourth input terminals. Second
An output terminal of the second phase detection circuit, a third terminal of the second phase detection circuit corresponds to a first input terminal of the first phase detection circuit, and a fourth terminal of the second phase detection circuit is The second input terminal of the first phase detection circuit corresponds to the second output terminal of the second phase detection circuit corresponds to the first output terminal of the first phase detection circuit; Signal is input to the first and fourth input terminals, the second signal is input to the second and third input terminals, and the outputs of the first and second phase detection circuits are combined circuit. (Π / 2) phase shifter, wherein the phase detection output is fed back to the variable phase shifter for PLL control. 6. A digital signal demodulation device comprising at least a synchronous detection circuit, a signal generator, a variable phase shifter, and a phase detector for detecting a phase difference between a first signal and a second signal, wherein the phase detector is A first phase detection circuit having first and second input terminals and a first output terminal; and a second phase detection circuit having third and third phase detection circuits. 4 input terminals and a second output terminal, the third terminal of the second phase detection circuit corresponds to the first input terminal of the first phase detection circuit, and the second phase detection circuit. The fourth terminal of the first phase detection circuit corresponds to the second input terminal of the first phase detection circuit, and the second output terminal of the second phase detection circuit is the first output terminal of the first phase detection circuit. Corresponding to, inputting the first signal to the first and fourth input terminals, The second signal is input to the second and third input terminals, the outputs of the first and second phase detection circuits are combined by a combining circuit to form a phase detection output, and the phase detection output is used for the variable phase shift. A digital signal demodulating device, characterized in that the first and second signals are fed to the synchronous detection circuit by being fed back to a signal processing device for PLL control.