JPH07226019A - Disk striping device - Google Patents

Abstract

PURPOSE:To inexpensively realize the device by simplifying its structure in a disk striping device used when recording dispersedly the continuous data for which only one recording medium is not enough in the processing speed, to plural recording media and connecting and reproducing them. CONSTITUTION:This device is provided with N pieces of recording media 51, N pieces of control part 41 to control them, plural FIFO memories 11 corresponding to the number of channels, a data bus 31 connecting between respective control parts 41 and respective FIFO memories 11 and an FIFO control part 21 provided with an N-ary counter 22 and controlling respective FIFO memories 11. Then, by successively using the data bus 31 according to the value of the N-ary counter 22, the constitution is simplified, and the cost is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for recording continuous data, which cannot be processed by a single recording medium in time, on a plurality of recording media, recording the combined data, and reproducing the data, in particular, an image editing device or a moving image. The present invention relates to a disk striping apparatus suitable for a case where it is necessary to record and reproduce a plurality of videos in real time and process them in real time, such as an image communication apparatus that transmits an image.

[0002]

2. Description of the Related Art Generally, when it is desired to record data at a transfer rate higher than that of an individual recording medium, a method of increasing the processing speed is adopted by dividing the data into a plurality of media and processing the divided data. For example, when reading three data groups from three recording media, as shown in FIG.
1-213, 221-223, 231-233, and three switches 241-243 and recording medium 25, respectively.
With 1 to 253, a disk striping device can be realized.

The operation of the above apparatus will be described. First,
The recording operation will be described. The data of each system is equally divided into three channels and is divided into FIFO memories 211 to 213 and 221 to 2 respectively.
23, 231-233. Next, the switches 241 to 243 are aligned with the channel CH1, and the channel C
The data string of H1 is transmitted from the FIFO memories 211 to 213 to the recording media 251 to 253, respectively. Next, the switches 241 to 243 are adjusted to the channel CH2, and the data strings of the channel CH2 are transmitted from the FIFO memories 221 to 223 to the recording media 251 to 253, respectively. Finally, the switches 241 to 243 are adjusted to the channel CH3, and the data strings of the channel CH3 are similarly transmitted from the FIFO memories 231 to 233 to the recording media 351 to 353, respectively. By repeating the above cycle, recording of three systems is completed.

Next, the reproducing operation will be described. Playback is controlled in the opposite direction to recording. First, the switches 241 to 243 are adjusted to the channel CH1 and data is transferred from the recording media 351 to 353 to the FIFO memories 211 to 213 of the channel CH1. Next, the channel CH2 and finally the channel CH3 are similarly transferred. After the completion of these three steps, each channel CH controls each of the three FIFO memories to synthesize and read the data. Stripe processing can be realized by repeating the above operation.

[0005]

However, in the above-mentioned conventional device, there are nine FIFO memories, and data is exchanged from three recording media at the same time.
Nine O controllers are also required, which increases the price of the control unit. Further, even if the data transmission path is 8 bits, the number of lines in the 9 lines is 72, which is complicated. Furthermore, three switches are required to switch the data path, and a large increase in cost is unavoidable for realizing the stripe processing.

An object of the present invention is to solve such a conventional problem, and an object thereof is to provide a disk striping apparatus which has a simpler structure and can realize stripe processing at low cost.

[0007]

In order to achieve the above object, the present invention provides one data bus instead of nine data paths, and transfers data between each recording medium and each FIFO memory. If there are N, the FIFO control unit having a built-in N-counter performs time division of the bus evenly. That is, as shown in FIG. 1, a plurality of N recording media 51, N control units 41 that control each recording medium 51, a plurality of FIFO memories that record and reproduce data, and each control unit 41. And a FI for controlling each FIFO memory 11 by having a data bus 31 for coupling between each FIFO memory 11 and the N-ary counter 22.
The FO control unit 21 is provided.

[0008]

[Operation] The operation will be described. First, the recording operation will be described. The data of each channel CH is stored in each FIFO memory 1
Written to 1. First, the data string of the channel CH (1) is transferred to each recording medium 51 via the data bus 31 and each control unit 41. The transfer order of the recording medium 51 depends on the value of the N-ary counter 22 in the FIFO control unit 21 that controls the data bus 31. That is, when the value of the counter 22 is 1, the recording medium (1) 51 is displayed. When the value of the counter 22 is 2, the recording medium (2) 51 is recorded.
When it is 3, the data is transferred to the recording medium (3) 51. Next, the data string of the channel CH (2) is transferred to each recording medium 51. Also at this time, the recording medium to be transferred is controlled by the value of the N-ary counter 22. Next, channel CH
The data string of (3) is transferred to each recording medium 51 by the same method. By repeating the above cycle, recording of N systems is completed.

Next, the reproducing operation will be described. Playback is controlled in the opposite direction to recording. Each recording medium 51 has a channel C
The data of H (1) is read. First, each recording medium 51,
Data is transferred from 52 and 53 to the FIFO memory (1) 11 of the channel CH (1). If the value of the N-ary counter 22 is 1, the recording medium (1) 51 is transferred, if it is 2, the recording medium (2) 51 is transferred, and if it is 3, the recording medium (3) 51 is transferred to the FIFO memory (1) 11 of the channel CH (1). To do.
The channel CH (2) and the channel CH (3) are also transferred by the same method. After the above steps are completed, each channel CH synthesizes and reads the data from the respective FIFO memories. Stripe processing can be realized by repeating the above operation.

[0010]

FIG. 2 shows the structure of an embodiment of the present invention. In this embodiment, three moving images are image-compressed by JPEG, and three hard disk drives (hereinafter HDD)
Record and combine in two.

In FIG. 1, 111, 112 and 113 are H
DD, 121, 122 and 123 are S for controlling each HDD.
CSI controllers 131, 132, 133 are provided in accordance with the number of channels for recording / reproducing data.
IFO memories 141, 142 and 143 are FIFO controllers having N-ary (N = 3 in the present embodiment) counters, and 151, 152 and 153 J for compressing and expanding moving images.
PEG processing unit, 161 is each SCSI controller 121
To 123 and the respective FIFO memories 131 to 133 are coupled to each other, and 162 is each SCSI controller 121.
˜123 and the FIFO controllers 141 to 143 are coupled to each other, and 171 is a host CPU.

The R / W of each HDD 111-113 is SC
Transfers byte by byte using the SI protocol. Further, the SCSI controllers 121 to 123 for controlling the HDDs 111 to 113 are responsible for SCSI control, and data can be input at high speed through the 2-byte wide DMA bus 161.

In this embodiment, the DMA bus 161 is set to 3
SCSI controllers 121-123 and 3 FIs
The stripe transfer is executed by the ternary counters connected to the FO memories 131 to 133 and incorporated in the respective FIFO controllers 141 to 143.

Next, the operation of the above embodiment will be described. First, the recording operation will be described. The video of each channel CH is compressed by the JPEG processing units 151 to 153 and written in each of the FIFO memories 131 to 133 as a code string. On the other hand, the host CPU 171 first selects three SCSI
The controllers 121 to 123 are instructed to transfer the data of the channel CH (1) to the HDDs 111 to 113. Then, the request flag of data from each of the SCSI controllers 121 to 123 becomes H, and the data is sent to the FIFO controllers 141 to 143 by the control bus 162.

The FIFO controller 141 of the channel CH (1) divides the data in the FIFO memory 131 into three equal parts, and sequentially transfers the data to the three SCSI controllers 121 to 123 according to the value of the internal ternary counter. When the predetermined data transfer is completed, the data request flag becomes L. When the host CPU 171 confirms the end by looking at this flag, this time the data of the channel CH (2) is changed to H level.
Command to transfer to DD111-113. The FIFO controller 142 of the channel CH (2) has an internal 3
According to the value of the binary counter, each SCSI controller 121
Transfer data to 123. When the channel CH (2) ends, the host CPU 171 determines that the channel CH (3)
Command is sent to each HDD 111-113. By continuing the above operation, without interruption,
Data of three systems are distributed and recorded in the three HDDs 111 to 113.

Next, the reproducing operation will be described. The playback operation is
The procedure is the same except that the recording operation is reversed in direction.
That is, first, the host CPU 171 instructs the SCSI controllers 121 to 123 to read the data of the channel CH (1) from the HDDs 111 to 113 and transfer the data to the FIFO memory 131. The SCSI controllers 121 to 123 set the data read request flag to H. FIFO controller 14 of channel CH (1)
1 sequentially transfers data from the SCSI controllers 121 to 123 to the FIFO memory 131 according to the value of the internal ternary counter. At this time, the inside of the FIFO memory 131 is divided into three equal parts, and the data from each HDD 111 to 113 is written in a predetermined area.
(2) and channel CH (3). On the other hand, in accordance with the expansion operation of the JPEG processing units 151 to 153 from the FIFO memories 131 to 133, the FIFO memories 131 to 133 are sequentially transferred to the JPEG processing units 151 to 153.
Transferred to.

[0017]

According to the present invention, as is apparent from the above-described embodiment, the number of FIFO controllers can be minimized, there is no changeover switch, connection is simple, and cost reduction and space saving can be realized.

Further, in the case of a system in which the number of stripes is optionally increased, in the conventional configuration, all of them must be replaced, but according to the present invention, simply the additional C
Only H can be connected to the bus, and expansion is easy.

[Brief description of drawings]

FIG. 1 is a block diagram showing the concept of a disk striping device of the present invention.

FIG. 2 is a block diagram of a disk striping device showing an embodiment of the present invention.

FIG. 3 is a block diagram of a disk striping device showing a conventional example.

[Explanation of symbols]

 11 to 13 FIFO memory 21 FIFO control unit 22 N-ary counter 31 data bus 41 to 34 control unit 51 to 53 recording medium 111 to 113 HDD 121 to 123 SCSI controller 131 to 133 FIFO memory 141 to 143 FIFO memory controller 151 to 153 JPEG Processing unit 161 DMA bus 162 Control bus 171 Host CPU

Claims (1)

[Claims] 1. A plurality of N recording media, N control units for controlling each recording medium, a plurality of FIFO memories for recording and reproducing data, each control unit and each FI.
A disk striping device comprising a data bus for coupling with a FO memory, and a FIFO control unit having an N-ary counter and controlling each of the FIFO memories.