JPH0722526A - Semiconductor device - Google Patents

Abstract

PURPOSE:To speed up the operation of a single chip microcomputer and the like including a flash memory therein by correcting impurity concentration distribution below a channel of a MOSFET, the ditribution being yielded owing to a heat treatment, and hereby restricting the lowering of an operation speed of the MOSFET. CONSTITUTION:First impurity, i.e., B<+> ion is doped into a channel region of a MOSFETQI constituting an ordinary logical circuit such as a central processing unit CPU so as to obtain peak concentration in the vicinity of the surface of a semicondcutor substrate in step ST1, and thereafter prior to an annealing processing of improving the withstand voltage of a MOSFETQ2 constituting a peripheral circuit and the like of a flash memory FMEM second impurity, i.e., As<+> ion is doped to the predetermined depth in the substrate such that the absolute value of the second impurity has smaller peak concentration than that of the first impurity in step ST2. Hereby, the concentration distribution of the first impurity flattened by a heat treatment is cancelled with that of the second impurity for correction thereof.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a technique which is particularly effective when used in a single-chip microcomputer having a built-in flash memory.

[0002]

2. Description of the Related Art There is a flash memory which has an electrically programmable non-volatile memory cell as a basic structure and which can be collectively erased in a predetermined block unit. There is also a single-chip microcomputer that incorporates this flash memory.

The flash memory is described in, for example, Japanese Patent Laid-Open No. 2-289997.

[0004]

The inventors of the present application have encountered the following problems in an attempt to accelerate the speed of a single-chip microcomputer incorporating the above flash memory. That is, as is well known, the flash memory uses an erasing voltage having a relatively large absolute value of about +12 V in batch erasing. Therefore, for example, a MOSFET (metal oxide semiconductor field effect transistor, which is a generic term for an insulated gate field effect transistor in this specification) constituting a peripheral circuit of a flash memory has a erasing voltage of Q2. It is indispensable to have sufficient pressure resistance so as not to cause element breakdown even when applied. Therefore, in a conventional single-chip microcomputer that incorporates flash memory,
As illustrated in FIG. 7, step ST3, that is, MOS
At the stage where the implantation of P ⁺ for forming the source / drain of the FET Q2, that is, phosphorus ions is completed, an annealing process is performed at a high temperature of about 1000 ° C. to increase the withstand voltage of the MOSFET Q2.

However, at this time, in the MOSFET Q1 forming a normal logic circuit such as the central processing unit CPU of the microcomputer, the implantation of B ^+, that is, boron ions into the channel region in step ST1 is completed. The impurity concentration distribution in the depth direction under the channel of the MOSFET Q1 is assumed to have its peak concentration near the surface of the semiconductor substrate immediately after ion implantation, as illustrated in FIG.
After the annealing treatment of No. 3 is performed, it is flattened and exhibits a relatively high concentration even at a relatively deep position.

As is well known, the drain-source current Ids flowing through the channel of the MOSFET Q1 forming a normal logic circuit has a gate width W and a surface electron density Q induced at a position y from the source. , Where the effective mobility of electrons on the channel surface is μeff and the electric field at the point y is εy, Ids = W · Q · μeff · εy. Further, the surface electron density Q in the above equation is MO
The gate capacitance of SFETQ1 is Co, the gate voltage is Vg,
The flat band voltage is Vfb, the Fermi potential is φf, the potential at the y point is V (y), and the relative permittivity of silicon is ε.
s, the dielectric constant of vacuum is εo, the charge amount of electrons is q, and the impurity concentration is Na: Q = −Co × {Vg−Vfb−2φf−V (y)} + [2εs · εo · q · Na {V (y) + 2φf}] ^1/2 . In addition, [2εs ・ εo ・ q ・ Na {V (y) +2
φf}] ^1/2 is [2εs · εo · q · Na {V (y) +
2φf}]. The first term is the inversion layer and the second term is the acceptor charge density in the depletion layer.

As described above, the impurity concentration Na under the channel of the MOSFET Q1 has a peak concentration in the vicinity of the substrate surface immediately after the boron ion implantation and has a small impurity concentration in the depletion layer, but enhances the withstand voltage of the MOSFET Q2. After the annealing treatment is performed, it is flattened and the impurity concentration in the depletion layer is increased. Therefore, the second term of the above equation for obtaining the surface electron density Q becomes large and the surface electron density Q becomes small, so that the value of the drain source current Ids of the MOSFET Q1 becomes small. This decrease in the drain-source current Ids eventually causes the operation speed of the MOSFET Q1 forming the normal logic circuit to be slowed down, which restricts the speeding up of the single-chip microcomputer.

An object of the present invention is to provide MOSF by heat treatment.
It is to realize a semiconductor device such as a single-chip microcomputer capable of correcting a change in the impurity concentration distribution under the ET channel. Another object of the present invention is to suppress the decrease in the operating speed of the MOSFET due to heat treatment and promote the speedup of a single-chip microcomputer having a built-in flash memory.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0010]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, in a single-chip microcomputer or the like having a built-in flash memory, the first MO that constitutes a normal logic circuit such as a central processing unit.
After ion-implanting the first impurity into the channel region of the SFET so as to have a peak concentration near the surface of the substrate, for example, a second MOSFE forming a peripheral circuit of a flash memory.
Prior to the heat treatment for increasing the withstand voltage of T, a second impurity of the opposite conductivity type is ion-implanted to a predetermined depth inside the substrate so that the second impurity has a peak concentration whose absolute value is smaller than that of the first impurity.

[0011]

According to the above means, the concentration distribution of the first impurity flattened by the heat treatment is canceled by the concentration distribution of the second impurity, and the peak concentration is almost in the state before the heat treatment, that is, near the substrate surface and the substrate has a peak concentration. It can be corrected to a low concentration at a relatively deep position inside. As a result,
The average value of the impurity concentration in the depletion layer of the first MOSFET forming a normal logic circuit such as the central processing unit is reduced, the drain source current thereof is increased, and the operating speed of the first MOSFET is reduced by heat treatment. Since it is possible to suppress the above, it is possible to promote the speeding up of a single-chip microcomputer having a built-in flash memory.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a board layout diagram of an embodiment of a single chip microcomputer to which the present invention is applied. Based on the figure, first, an outline of the configuration and board arrangement of the single-chip microcomputer of this embodiment will be described. In the following description, the positional relationship shown in FIG.

In FIG. 1, the single-chip microcomputer of this embodiment has a central processing unit CPU arranged in the upper center of the P-type semiconductor substrate PSUB as its basic constituent element, although not particularly limited thereto. A flash memory FMEM for storing a control program and fixed data necessary for the operation of the central processing unit CPU is arranged under the central processing unit CPU, and a clock generation circuit CPG, a timer circuit TIM, and A control circuit CTL is arranged. A random access memory RAM and an analog / digital conversion circuit A / D are arranged on the right side of the flash memory FMEM, and 12 input / output ports P1 are provided around these circuits along the four sides of the semiconductor substrate PSUB. ~ PC is arranged.

Here, the central processing unit CPU performs a step operation according to a control program stored in advance in the flash memory FMEM, executes a predetermined logical operation process, and controls / controls each unit of the microcomputer. As described above, the flash memory FMEM stores the control program and fixed data necessary for the operation of the central processing unit CPU, and the random access memory RAM stores the calculation result of the central processing unit CPU and the input / output ports P1 to P1. Temporarily stores data and the like input / output via the PC. Further, the clock generation circuit CPG forms a clock signal necessary for the step operation of the central processing unit CPU, and the timer circuit TIM realizes a predetermined time counting and calendar function according to the clock signal supplied from the clock generation circuit CPG. . In addition, the control circuit C
The TL manages access to various input / output devices such as a flash memory FMEM and a random access memory RAM, and also manages interrupt requests to the central processing unit CPU, and the analog / digital conversion circuit A.
/ D converts an analog signal input from an external sensor into a digital signal of a predetermined bit.

In this embodiment, the central processing unit C
A normal logic circuit including PU uses a power supply voltage VCC having a relatively small absolute value such as + 3V as its operating power supply, and a flash memory FMEM uses an internal voltage VP having a relatively large absolute value such as + 12V. Erase voltage. Therefore, in particular, the MOSFET Q2 constituting the peripheral circuit of the flash memory FMEM, etc.
It is indispensable to have sufficient pressure resistance so as not to cause element breakdown even when P is applied, and heat treatment at a relatively high temperature is required to realize such high voltage resistance.

FIG. 2 is a partial process flow chart of one embodiment for explaining the formation process of the MOSFET included in the single-chip microcomputer shown in FIG. Further, FIG. 3 shows the impurity concentration distribution immediately after the boron ion implantation and after the high temperature annealing of the MOSFET Q1 included in the normal logic circuit such as the central processing unit CPU of the single-chip microcomputer shown in FIG. Further, FIG. 4 shows the impurity concentration distribution of the MOSFET Q1 immediately after arsenic ion implantation and after high temperature annealing, and FIG. 5 shows the case where the impurity concentration distribution of boron after the high temperature annealing is offset by the impurity concentration distribution of arsenic. The impurity concentration distribution of is shown. Based on these drawings, the outline of the MOSFET forming process of the single-chip microcomputer of this embodiment, the change in the concentration distribution of the MOSFET Q1 due to the heat treatment, and the characteristics thereof will be described.

Note that, in FIG. 2, a MOSFET Q1 (first MOSFET) forming a normal logic circuit such as a central processing unit CPU along with the process of forming the MOSFET.
And the MO that constitutes the peripheral circuit of the flash memory FMEM
A partial cross-sectional structure of the SFET Q2 (second MOSFET) is shown. In addition, the impurity concentrations of boron and arsenic under the channel actually influence each other and change, but in FIGS. 3 and 4, each is shown in a state where ions are individually implanted.

In FIG. 2, the MOSFET forming process in the single-chip microcomputer of this embodiment is started by forming a field oxide film in step ST1 and forming a silicon oxide film SiO ₂ prior to ion implantation. P-type well region PWELL formed with a predetermined depth in a P-type semiconductor substrate PSUB
At this time, B ^+, that is, boron ions are implanted through the silicon oxide film SiO ₂ . As a result, MOSFE
P-type well region PWELL which becomes the channel region of TQ1
As shown by the solid line in FIG. 3, a P-type (first conductivity type) impurity (first impurity) is implanted so as to have a peak concentration near the surface of the semiconductor substrate. This allows the MOS
The characteristics of the FET Q1 are controlled so as to have a predetermined threshold voltage, and the punch-through breakdown voltage thereof is increased. The concentration distribution of the P-type impurity by the boron ion implantation is MO as shown by the dotted line in FIG.
The SFET Q2 is flattened by the annealing treatment, that is, the heat treatment for enhancing the withstand voltage, and the impurity concentration in the depletion layer is increased.

In this embodiment, next, As ^+, that is, arsenic ion implantation is performed in step ST2. MOS
P-type well region PWE which becomes the channel region of the FET Q1
As indicated by a solid line in FIG. 4, LL has an opposite conductivity type, that is, N type (second conductivity type) so as to have a peak concentration inside the substrate.
Impurity (second impurity) is injected. In addition, this N
The type impurity has a peak concentration at a predetermined depth inside the substrate by setting the implantation energy to a predetermined value, and its absolute value is also made smaller than the absolute value of the peak concentration of the P-type impurity. . As shown by the dotted line in FIG. 4, the concentration distribution of the N-type impurity is slightly flattened by the annealing treatment for enhancing the withstand voltage of the MOSFET Q2, but it does not change significantly.

On the semiconductor substrate after the ion implantation,
In step ST3, polysilicon PolySi and tungsten silicon WSI ₂ which will be the gate electrodes of the MOSFETs Q1 and Q2 are formed. Further, in step ST4, after implanting P ^+, that is, phosphorus ions to form a pair of N-type high-concentration semiconductor regions N ⁺ to be the source and drain of the MOSFET Q2,
Annealing is performed at a high temperature of about 1000 ° C.
As a result, the MO that constitutes the peripheral circuit of the flash memory
It is possible to improve the withstand voltage of the SFET Q2 and prevent the element breakdown of the MOSFET Q2 due to the application of the erase voltage VP. Finally, in step ST5, MOSFETQ
P ^+, that is, phosphorus ions are implanted to form a pair of N-type low-concentration semiconductor regions N ^−, and a sidewall of the gate electrode is formed, and then a pair of N-types serving as a source and a drain of the MOSFET Q1. High concentration semiconductor region N
Implantation of As, that is, arsenic ions, for forming ⁺ is performed.

By the way, the concentration distribution of the P-type impurity under the channel of the MOSFET Q1 is flattened by the heat treatment in step ST4, as shown by the dotted line in FIG. 3, and the impurity concentration in the depletion layer increases. . However, in the single-chip microcomputer of this embodiment, as described above, arsenic ions are implanted in step ST2, and the concentration distribution thereof has a peak concentration inside the substrate even after the annealing process. Therefore, the flattened P-type impurity concentration distribution is offset by the N-type impurity concentration distribution having a peak concentration inside the substrate, as shown in FIG. It has a peak concentration and is corrected to a low concentration at a relatively deep position inside the substrate.

As is well known, the drain-source current Ids flowing through the channel of the MOSFET Q1 forming a normal logic circuit has its gate width W, and the surface induced at a position y from the source S in FIG. The electron density is Q, and the effective electron mobility on the channel surface is μe.
When the electric field at the ff and y points is εy, it can be obtained as Ids = W · Q · μeff · εy. Further, the surface electron density Q in the above equation is MO
The gate capacitance of SFETQ1 is Co, the gate voltage is Vg,
The flat band voltage is Vfb, the Fermi potential is φf, the potential at the y point is V (y), and the relative permittivity of silicon is ε.
s, the dielectric constant of vacuum is εo, the charge amount of electrons is q, and the impurity concentration is Na: Q = −Co × {Vg−Vfb−2φf−V (y)} + [2εs · εo · q · Na {V (y) + 2φf}] ^1/2 . Therefore, the flattening of the P-type impurity concentration distribution by the heat treatment causes the impurity concentration Na in the depletion layer to increase, the surface electron density Q to decrease, and the drain source current Ids of the MOSFET Q1 to decrease.

However, in this embodiment, the implantation of arsenic ions in step ST2 causes the P
The concentration distribution of the type impurities is corrected to have a peak concentration in the state before the heat treatment, that is, near the substrate surface and to be low at a relatively deep position inside the substrate, and the impurity concentration in the depletion layer is reduced. Therefore, the surface electron density Q recovers and increases, and the drain-source current Ids of the MOSFET Q1 increases correspondingly. As a result, it is possible to suppress the decrease in the operating speed of the MOSFET Q1, that is, the normal logic circuit due to the heat treatment, and thereby to accelerate the speedup of the single-chip microcomputer incorporating the flash memory.

By applying the present invention to a semiconductor device such as a single-chip microcomputer having a built-in flash memory as shown in the above embodiment, the following operational effects can be obtained. That is, (1) In a single-chip microcomputer or the like having a built-in flash memory, the first impurity is ion-implanted into the channel region of the first MOSFET forming a normal logic circuit so as to have a peak concentration near the substrate surface. After that, the second MO that constitutes the peripheral circuit of the flash memory
Prior to the heat treatment for increasing the withstand voltage of the SFET, a second conductivity type second impurity is ion-implanted at a predetermined depth inside the substrate so as to have a peak concentration whose absolute value is smaller than that of the first impurity. The concentration distribution of the first impurity flattened by the heat treatment is canceled by the concentration distribution of the second impurity, and the peak concentration is almost in the state before the heat treatment, that is, the peak concentration is near the substrate surface, and it is low at a relatively deep position inside the substrate. The effect is that the density can be corrected as much as possible.

(2) According to the above item (1), it is possible to reduce the impurity concentration in the depletion layer of the first MOSFET forming a normal logic circuit and increase the drain-source current thereof. . (3) According to the above items (1) and (2), it is possible to suppress the decrease in the operating speed of the first MOSFET due to the heat treatment and to promote the speedup of a single-chip microcomputer having a flash memory. To be

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, the block configuration of the single-chip microcomputer is not restricted by this embodiment, and the substrate layout can adopt various embodiments. In FIG. 2, boron and arsenic and phosphorus used for ion implantation can be replaced with other equivalent materials, and M
The process of forming the OSFET is not limited to this embodiment. 3 to 5, various specific embodiments of the impurity concentration distribution under the channel of the MOSFET Q1 can be adopted.

In the above description, the case where the invention made by the present inventor is mainly applied to a single-chip microcomputer which is a field of application which is the background of the invention has been described, but the present invention is not limited thereto and, for example, absolute The present invention can also be applied to various other memory integrated circuit devices that require a large internal voltage, various digital integrated circuit devices and gate array integrated circuit devices that incorporate such memory integrated circuits. The present invention can be widely applied to a semiconductor device including at least a MOSFET forming a normal logic circuit and a MOSFET requiring heat treatment.

[0028]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a single-chip microcomputer or the like having a built-in flash memory, after ion-implanting the first impurity into the channel region of the first MOSFET forming a normal logic circuit so as to have a peak concentration near the surface of the semiconductor substrate. Prior to the heat treatment for increasing the withstand voltage of the second MOSFET that constitutes the peripheral circuit of the flash memory, etc., the absolute value should be reversed to a predetermined depth inside the substrate so as to have a peak concentration smaller than that of the first impurity. By ion-implanting the second conductivity type impurity,
The concentration distribution of the first impurity flattened by the heat treatment is canceled by the concentration distribution of the second impurity, and the peak concentration is almost in the state before the heat treatment, that is, the peak concentration is near the substrate surface and the low concentration is relatively deep inside the substrate. It can be modified as much as possible. As a result, the impurity concentration in the depletion layer of the first MOSFET forming a normal logic circuit can be reduced and its drain-source current can be increased to suppress the decrease in the operating speed of the first MOSFET due to heat treatment. It is possible to promote the speedup of a single-chip microcomputer having a built-in flash memory.

[Brief description of drawings]

FIG. 1 is a board layout diagram showing an embodiment of a single-chip microcomputer to which the present invention is applied.

2 is a partial process flow chart showing an embodiment for explaining a process of forming a MOSFET included in the single-chip microcomputer shown in FIG. 1. FIG.

3 is an impurity concentration distribution diagram immediately after boron ion implantation and after high-temperature annealing of a MOSFET included in a normal logic circuit of the single-chip microcomputer in FIG.

FIG. 4 is an impurity concentration distribution diagram of MOSFET included in a normal logic circuit of the single-chip microcomputer of FIG. 1 immediately after arsenic ion implantation and after high temperature annealing.

5 is an impurity concentration distribution diagram when the impurity concentration of boron after the high temperature annealing of the MOSFET included in the normal logic circuit of the single-chip microcomputer of FIG. 1 is canceled by the impurity concentration of arsenic.

6 is a sectional structural view showing an embodiment of a MOSFET included in a normal logic circuit of the single-chip microcomputer shown in FIG.

FIG. 7 is a partial process flow chart showing an example for explaining a process of forming a MOSFET included in a conventional single-chip microcomputer.

8 is an impurity concentration distribution immediately after boron ion implantation and after high temperature annealing of a MOSFET included in a normal logic circuit of the single-chip microcomputer shown in FIG.

[Explanation of symbols]

PSUB ... P-type semiconductor substrate, CPU ... Central processing unit, FMEM ... Flash memory, CPG ...
..Clock generation circuit, TIM ... Timer circuit, C
TL ... Control circuit, RAM ... Random access memory, A / D ... Analog / digital conversion circuit, P
1-PC ... Input / output ports. Q1 ... N-channel MOSFET forming a normal logic circuit, Q2 ... N-channel MO forming a peripheral circuit of a flash memory
SFET, PWELL ... P-type well region, SiO ₂
... silicon oxide film, PolySi ... polysilicon, WSI ₂ ... tungsten silicide, N ⁺ · ·
· N-type high-concentration semiconductor region, N ^- · · · N-type low concentration semiconductor region. B ... Boron, As ... Arsenic, P ... Phosphorus.
S ... source, D ... drain, G ... gate,
IS ... Gate oxide film, CH ... Channel, DL.
..Depletion layer

Claims (4)

[Claims] 1. A step of ion-implanting a first impurity of a first conductivity type into a channel region of a first MOSFET, and a step of correcting the concentration distribution of the first impurity in the depth direction after heat treatment. A semiconductor device, which is formed through a step of implanting ions of a second conductivity type second impurity. 2. The first impurity has a peak concentration near the surface of the semiconductor substrate, and the second impurity has a peak concentration at a predetermined depth inside the semiconductor substrate. 2. The semiconductor device according to claim 1, wherein the absolute value of the peak concentration of the second impurity is made smaller than the absolute value of the peak concentration of the first impurity. 3. The first MOSFET is included in an ordinary logic circuit, and the semiconductor device is included in another predetermined internal circuit and is kept at a relatively high temperature in order to increase its withstand voltage. Second MOSFET requiring heat treatment at
3. The semiconductor device according to claim 1, wherein the semiconductor device includes T. 4. The semiconductor device according to claim 3, wherein the semiconductor device is a single-chip microcomputer containing a flash memory, and the internal circuit is included in the flash memory.