JPH07222191A - Chroma key combination circuit - Google Patents

Abstract

PURPOSE:To naturally point the desired video part of a first moving picture to be a designated object by the use of a second moving picture with any visual trouble. CONSTITUTION:The second moving picture is subjected to chroma key combination with the first moving picture. At the time, blue back in the second moving picture to be a foreground is displayed transparently, hands and arms are displayed opaquely and the shadow is displayed translucently. Thus, the color range of the blue back is judged in a first comparator 21 and the color range of the shadow is judged in a second comparator 22 respectively. Corresponding to the output codes of the first and second comparators 21 and 22, the pixel data Va of the first moving picture are selected in the part of the blue back, the pixel data Vb of the second moving picture are selected in the part of the hands and the arms and the result of weighting and adding the Va and the Vb is selected in the part of the shadow by a data selector 4 as output pixel data Vout respectively. When the output codes relating to the hands and the arms are converted so as to be coincident to the case of the shadow in a code converter 40, the hands and the arms are also displayed translucently.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for chroma-key combining two video moving images in real time.

[0002]

2. Description of the Related Art A multimedia computer that uses a video moving picture as a means of communication (mutual communication) is installed at two remote locations, one by one, and the video moving pictures taken by both video cameras are transmitted to each other. If you send it to and combine it with chromakey, you can have intimate visual communication. Also, in the presentation system, the desired part of the reproduced video moving image is reproduced by chroma-key combining the video moving image reproduced from the VTR or the optical disc device with the image of one's own hand captured by the video camera. You can give a presentation while pointing with the image of your hand.

FIG. 22 shows an example of the configuration of a conventional chroma-key synthesizing circuit mounted on a system device having such a function. The circuit of FIG. 22 has a function of combining and outputting Vout on the right side based on the images Va (background) and Vb (foreground) arranged on the left side, as in the image diagram of the screen image of FIG. In FIG. 22, 901, 902, 903, 90
Reference numeral 6 denotes a D flip-flop (DF / F / F / F / F / F / F) that holds and outputs input data at the rising edge of the clock signal (clock)
F). Reference numeral 1 is a condition determining means for inputting two input data A and B and outputting a match signal if the input data A matches the condition indicated by the input data B. In the example of FIG. To be realized. The comparator 21 inputs the two input data A and B, determines whether the value of the input data A is within the range indicated by the input data B, and if yes, outputs a match signal “1” to the output Y. Output. A data selector 4 outputs an input signal B when the selection input S is "0", an input signal A when the selection input S is "1", and an output Y.
Are output respectively. In FIG. 22, B (0) indicates that B is selected when S = 0, and A (1) indicates that A is selected when S = 1. Dcon is condition data to be input to the comparator 21. In this example, RGB (Red: red, red,
Green: Blue, Blue: Blue) RG corresponding to each 8 bits
B upper limit (8 bits x 3) and lower limit (8 bits x 3)
In order to specify the range of the moving image data value by giving 3), the condition data Dcon of 48 bits in total is adopted.

In the D flip-flop 901, image data as shown by Va in FIG. 23 (a video image of a building photographed from the ground and reproduced by a VTR) is a pixel.
Input in units (24 bits) in synchronization with the clock signal. The Va screen is composed of horizontal 640 pixels and vertical 480 pixels, and each pixel has RGB 8-bit data, that is, 24-bit color data. The moving image signal Va is horizontally scanned from the pixel in the upper left corner of Va in FIG. 23, and when it reaches the upper right corner,
Go to the left corner of the second line, scan the second line horizontally, and repeat this process until reaching the lower right corner and returning to the upper left corner again. Similarly, in the D flip-flop 902, the image data indicated by Vb in FIG. 23 (the image of one's hand photographed by the video camera in front of the blue background (blue background)) is synchronized with the clock signal in pixel units. And enter. Of course, all the input pixel data are in the same scan position and are synchronized.

The condition data Dcon is set in the "blue back" color range (key color) of Vb in FIG. 23, and the D flip-flops 901 and 902 hold the pixel data of Va and Vb in synchronization with the clock signal. When output, the condition determination means 1 outputs "1" only when it corresponds to the "blue back" portion of the Vb image data. As a result, from the D flip-flop 906 that latches the output of the data selector 4, as shown by Vout in FIG. 23, "hands and arms" and their "shadows" that are always generated when photographing them (both are "blue backgrounds"). , Which is out of the color range of) and is superimposed on the image of "Bill" (chroma key composition).

[0006]

Looking at Vout in FIG. 23, the "hand and arm" and the "shadow" are overlaid on the image of "Bill", and the image below is invisible at all. This has a drawback in that there is often a fatal situation in which a considerably large amount of image information is lost and sometimes misleading.

An object of the present invention is to point (instruct) a desired portion of the first video moving image in real time with an image (second video moving image) of a "hand" or the like taken by one's own video camera. In order to be able to do so, in particular, to provide a chroma key synthesis circuit that prevents the first video moving image that is being pointed out from being obscured by the pointing "hand" or its "shadow". is there.

[0008]

In order to achieve the above object, the first chroma-key synthesizing circuit according to the present invention generates a foreground video moving image by using a background video moving image as a first moving image or pointing means. In the case of the second moving image, at least one mixing circuit for performing weighted addition (semi-transparent synthesis) of the pixel data of the first and second moving images, and the pixel data of the second moving image are conditional data (color range). ), A plurality of condition determining means having a function of outputting a match signal when the condition is satisfied, and a first moving image (background) according to a combination of the match signal outputs of the plurality of condition determining means, And a data selector for selectively outputting one of the second moving image (foreground) and the output (semitransparent composite) of at least one mixing circuit. .

A second chroma key composition circuit according to the present invention includes a mixing circuit for weighted addition (semi-transparent composition) of pixel data of the first and second moving images in accordance with transparency data, and a second mixing circuit, respectively. A combination of a plurality of condition determining means having a function of outputting a match signal when the pixel data of the moving image conforms to the condition indicated by the condition data (color range), and a match signal output of each of the plurality of condition determining means. The data selector for supplying at least one variable transparency data, fixed complete transparency data, and fixed opacity data to the mixing circuit.

The third chroma key composition circuit according to the present invention converts the "colored shadow" generated in the second moving image (foreground) into the "colorless shadow" in the second moving image. It further comprises a black-and-white circuit for inputting pixel data (having color), removing a color component, and outputting only a luminance (gray) component, and the mixing circuit outputs a matching signal of each of the plurality of condition determining means. Depending on the combination, weighted addition is performed so that the output data of the black-and-white circuit and the pixel data of the first moving image (background) are semi-transparently synthesized, and a more natural "shadow" falls on the first moving image. It was done like this.

The fourth chromakey combination circuit according to the present invention adopts a two-stage pipeline structure, and
In order to reduce the power consumption, all inputs of the mixing circuit are fixed when semitransparent synthesis is not required.

[0012]

By adopting the configuration provided with the plurality of condition determining means, a partial area of the second moving image (foreground) (for example, only "shadow" or "hand and arm" and "shadow") Both sides)
By superimposing the image on the first video (background) in a semi-transparent manner, the second background without covering the background with the foreground
You can point to the first video with this video. Also,
If the "hand and arm" and the "shadow" are semi-transparent composite superimposed with different transparency, more effective pointing and presentation are possible. Moreover, if you convert the "colored shadow" that always occurs when you use blue background etc. into a completely uncolored "shadow" and combine it semi-transparently with the first moving image (background), a very natural composite moving image will be obtained. can get.

[0013]

【Example】

(Embodiment 1) FIG. 1 is a block diagram showing a chroma key synthesis circuit according to a first embodiment of the present invention. In FIG. 1, V
6, a, Vb, and Vout are TV-size image data composed of 640 (horizontal) × 480 (vertical) pixels, as shown in the image displayed.
For b and Vout, each pixel has 8 bits for RGB,
It has a total of 24 bits of color data. Video data Va, V
When b is input to the circuit of FIG. 1, a non-interlaced scan starting from the upper left corner of the screen image diagram of FIG. 6 (scans the uppermost line from the upper left corner to the right and reaches the upper right corner, then the second line from the top). To the left corner, scan the second line to the right, ..., to the lower right corner, return to the upper left corner, and repeat this.) Data in 1 pixel units is converted into the clock signal (clock). It is input in sync. Of course, the phases of non-interlaced scan are also perfectly synchronized.

Reference numeral 3 is a mixing circuit for weighted addition of two input data A and B, and M = t at its output M.
The data of the size of A + (1-t) B is obtained.
t is transparency and takes a value of 0 ≦ t ≦ 1. When t = 0 (completely opaque), M = B (foreground), and when t = 1 (completely transparent), M = A (background). When 0 <t <1, semi-transparent composition is performed. In the case of FIG. 1, the data is RGB for each 8
Since R is composed of bits, R is for R, G is for G, and B is for B. Transparency t
Is supplied as 8-bit transparency data T. t = 0 is T
= “00000000”, and t = 1 corresponds to T = “11111111”.

A configuration example of the mixing circuit 3 is shown in FIG.
8 for 301, 302, 304, 305, 307, 308
It is a multiplication circuit of bit / 2 inputs, 303, 306, 3
Reference numeral 09 is an 8-bit output addition circuit. Reference numeral 310 denotes a complement conversion circuit, which converts t into (1-t), that is, converts 8-bit T into ("11111111" -T) and outputs the converted value. Specifically, the sign of all the bits of T is inverted. 301-303
Red (red), 304-306 green (Green), 307
At ~ 309, the weight of blue is added. Red (R
Expressing the output M with respect to ed), M = (T × Va +
(“11111111” −T) × Vb) / “11111111”.

Referring again to FIG. 1, reference numeral 1 is a first condition determining means for inputting two input data A and B and outputting a match signal m1 if the input data A meets the condition indicated by the input data B. This is realized by the first comparator 21 in this embodiment. The first comparator 21 has two input data A and B.
Is input to determine whether the value of the input data A is within the range indicated by the input data B, and if it is, a match signal “1” is output to the output Y. 2 is a second condition determining means, m2 is a match signal, and specifically, the second comparator 2
Realize in 2. These are the same as the first condition judging means 1, the coincidence signal m1, and the first comparator 21, respectively. The first comparator 21 receives the pixel data Vb of the second moving image and the first condition data Dcon1, and the second comparator 22 receives the pixel data Vb of the second moving image and the second condition data Dcon2. Supplied.

FIG. 2 shows a configuration example of the first and second comparators 21 and 22. Reference numerals 200 to 205 denote known magnitude comparators, which compare the values of input data P and Q, and if P is equal to or greater than Q, P> Q = "1" and P <Q.
= "0", and if P is smaller than Q, P> Q = "0" and P <Q = "1". 206-209 are well-known AND
It is a gate. The pixel data Vb of the second moving image is input to the input A of the first comparator 21 in 24 bits, that is, each of RGB is 8 bits, and the first condition data Dcon1 is input to the input B of 48 bits, that is, each of RGB is 8 bits. Corresponding upper limit value Rma
x, Gmax, Bmax (8 bits each) and lower limit values Rmin, G
When min and Bmin (each 8 bits) are input, the pixel data value of the moving image of the input A is Rmin ≤ Red ≤ Rmax and Gmin ≤
The output Y becomes "1" only when the conditions of Green≤Gmax and Bmin≤Blue ≤Bmax are satisfied, and otherwise "0".

Referring again to FIG. 1, reference numeral 4 denotes a 3-input data selector, which outputs Y according to the selection control inputs S1 and S0.
Is to determine. That is, the input signal A is output when S1 = 0 and S0 = 1, the input signal B is output when S1 = 0 and S0 = 0, and the input signal C is output otherwise.
Is selected as. In FIG. 1, for example, S1 = 0 and S0
A (01) indicates that A is selected when = 1. The pixel data Va (background) of the first moving image is input to the A input of the data selector 4, the pixel data Vb (foreground) of the second moving image is input to the B input, and the output of the mixing circuit 3 is input to the C input. Supplied.

Reference numeral 40 denotes a programmable (variably settable) code converter, which has first and second condition determining means 1 and 2.
The code composed of the match signals m1 and m2 output from the converter is converted and output. An example of the configuration is shown in FIG. 401 is an 8-bit D flip-flop, and
Reference numerals 02 and 403 denote data selectors, both of which are publicly known. A conversion rule (conversion table) by writing a conversion code (data for code conversion) from the 8-bit data buses D7 to D0 to the D flip-flop 401.
Can be set freely. Three setting examples of the conversion table for converting A1 and A0 into Q1 and Q0 are shown in FIG.
It shows in (c). For example, in the setting of FIG. 5A, A1,
A0 passes through Q1 and Q0 as they are (no conversion). At this time, "11001010" is written in the D flip-flop 401.

Referring again to FIG. 1, reference numerals 901 to 906 denote D flip-flops which hold and output input data at the rising edge of the clock signal. These D flip-flops 901 to 906 have 24-bit first moving image data Va, 24-bit second moving image data Vb, 48-bit first condition data Dcon1, 48-bit second condition data Dcon2, It holds and outputs 8-bit transparency data Tp and 24-bit output data Vout.

Next, the operation of the embodiment shown in FIG. 1 will be described with reference to FIG. In the D flip-flop 901, background image data (an image reproduced while moving a high-rise building while moving from the ground and reproduced by a VTR) as a background as shown by Va in FIG. 6 is synchronized with a clock signal in a pixel unit. Enter. The Va screen is composed of horizontal 640 pixels and vertical 480 pixels, and each pixel has RGB 8-bit data, that is, 24-bit color data. D flip-flop 9
Image data (image of one's own hand photographed by the video camera in front of the blue background) as the foreground as indicated by Vb in FIG. 6 is input to 02 in units of pixels in synchronization with the clock signal. Of course, all the input pixel data are in the same scan position and are synchronized.

The first condition data Dcon1 is supplied with the upper limit value and the lower limit value of the color data in the range that covers the color representing the "blue back" of Vb. That is, for example, the distribution range of the color data of “blue background” is red: Red = Rmin to Rma
x = "00000000" to "00000010", green: Green = Gmin
~ Gmax = "00000000" to "00000010", blue: Blue =
If Bmin-Bmax = "11111100"-"11111111", Dcon1 = Rmin-Rmax-Gmin-Gmax-Bmin
・ Bmax = "00000000 00000010 00000000 00000010 11
111100 11111111 ". The second condition data Dcon2 is supplied with the upper limit value and the lower limit value of the color data in the range that covers the color representing the" shadow "of Vb. That is, the color range of the “shadow” is red: Red = Rmin to Rmax = “00000000” to “0000”.
0001 ”, green: Green = Gmin to Gmax =“ 00000000 ”to
"00000001", blue: Blue = Bmin to Bmax = "100000
If 00 ”to“ 11110000 ”, Dcon2 = Rmin · Rmax
-Gmin-Gmax-Bmin-Bmax = "00000000 000000
01 00000000 00000001 1000000011110000 ”.

Now, pixel data of 1 pixel of Va and Vb are respectively supplied to the D flip-flops 901 and 902.
The first and second condition data Dcon1, Dcon2 and the transparency data Tp are D flip-flops 903, 904, 9 respectively.
When it is taken in by 05, the mixing circuit 3 outputs Va and Vb.
Are translucently combined and output in a distribution corresponding to the transparency data Tp. As indicated by m1 and m2 in FIG. 6, the first condition determination means 1 matches only when the pixel in the “blue back” portion of Vb is captured because Dcon1 is set as described above. The signal "1" is output. Also, the second
Since the Dcon2 is set as described above, the condition determining means 2 outputs the coincidence signal "1" only when the pixel in the "shadow" portion of Vb is captured. The match signals m2 and m1 of the second and first condition determining means 2 and 1 are 0 and 1 in the “blueback” region of Vb, and “hand and arm”.
Is 0, 0, and the "shadow" is 1, 0 (in this example, there is almost no area of 1, 1). Code converter 4
When 0 is set to “pass through without conversion” as shown in FIG. 5A, moving image data such as Vout of FIG. 6 is obtained at the output of the D flip-flop 906 with the next clock signal. It will be. That is, Vout of the conventional example of FIG.
Comparing with, you can see the situation of the building in the background through the "shadow". Originally, the shadow allows the background to be seen through, so it looks very natural and is very effective for presentations.

Next, when the code converter 40 is set as shown in FIG. 5 (b), even if the match signals m2 and m1 from the second and the first condition judging means 2 and 1 are both "0", the data is obtained. Since the selector 4 selectively outputs the output of the mixing circuit 3,
Like Vout in Fig. 7, not only "shadow" but also "hand and arm" can be seen through. As a result, all the background appears and important information is not lost, so that not only the presentation effect but also the pointing effect becomes extremely good.

(Embodiment 2) FIG. 8 is a block diagram showing a chroma key synthesis circuit according to a second embodiment of the present invention. In the present embodiment, the large data selector 4 for selectively outputting the 24-bit pixel data in FIG. 1 is removed, and the 8-bit small data selector 5 for selectively outputting the transparency data is used. The same function as that of the embodiment is realized by small hardware.

In FIG. 8, the data selector 5 is a three-input selector that determines the output Y according to the selection control inputs S1 and S0. That is, the input signal A is selected as the output Y when S1 = 0 and S0 = 0, the input signal B is selected when S1 = 0 and S0 = 1, and the input signal C is selected otherwise. The minimum value of transparency data "00000000" (opaque data) is input to the A input of the data selector 5, the maximum value of transparency data "11111111" (completely transparent data) is input to the B input, and the clock signal is synchronized to the C input. The transparency data Tp from the outside is supplied. The output Y of the data selector 5 is given to the mixing circuit 3.

Next, the operation of the embodiment shown in FIG. 8 will be described. The output up to the code converter 40 is exactly the same as in FIG. Since the data selector 5 supplies the output Y as described above to the mixing circuit 3 as a transparency signal, if the code converter 40 is set as shown in FIG. 5A, the moving image data Vout as shown in FIG. The code converter 40 is shown in FIG.
If the setting is made as shown in (b), the moving image data Vout as shown in FIG. 7 is obtained.

(Embodiment 3) FIG. 9 is a block diagram showing a chroma key composition circuit according to a third embodiment of the present invention. In this embodiment, the configuration of the first embodiment is modified so that two transparency data are input. The difference from FIG. 1 is that the number of mixing circuits is increased by one and the data selector is changed from three inputs to four inputs accordingly.

In FIG. 9, 6 and 7 are first and second mixing circuits, each having the same function as the mixing circuit 3 of FIG. Reference numerals 907 and 908 denote D flip-flops for supplying the first and second transparency data Tp1 and Tp2 to the first and second mixing circuits 6 and 7 in synchronization with the clock signal. Reference numeral 8 denotes a 4-input data selector, which outputs Y depending on the selection control inputs S1 and S0.
Is to determine. That is, the input signal A is S1 = 0 and S0 = 1, the input signal B is S1 = 1 and S0 = 1, and the input signal C is S1 = 0 and S0 = 0.
However, when S1 = 1 and S0 = 0, the input signal D is selected as the output Y, respectively. The pixel data Va (background) of the first moving image is input to the A input of the data selector 8, the pixel data Vb (foreground) of the second moving image is input to the B input, and the pixel data Va of the first mixing circuit 6 is input to the C input. The output and the output of the second mixing circuit 7 are respectively supplied to the D input.

Next, the operation of the embodiment shown in FIG. 9 will be described. Similar to the first embodiment (FIG. 1), it is assumed that the video as shown in FIG. 7 is input as the pixel data Va and Vb of the first and second moving images. The first condition data Dcon1 includes Vb
The upper limit value and the lower limit value of the color data in the range that covers the color representing the "blue background" of are supplied. Second condition data Dco
The upper limit value and the lower limit value of the color data in the range that covers the color representing the “shadow” of Vb are supplied to n2. When the code converter 40 is set to “pass through without conversion” as shown in FIG. 5A, the “hand and arm” portion corresponds to the first transparency data Tp1 by the first mixing circuit 6. The result of the semi-transparent synthesis is reflected in the output Vout by the result of the semi-transparent synthesis in accordance with the second transparency data Tp2 by the second mixing circuit 7 in the "shadow" portion, and is represented by Vout in FIG. Video is obtained. Moreover, the "hand and arm" portion can be seen through with transparency corresponding to the first transparency data Tp1 (for example, 30%: not so transparent), and the "shadow" portion can be seen through the second transparency data Tp2 (for example, 80%). %: Almost transparent) with a transparency corresponding to. That is, "hand and arm" and "shadow"
By changing the transparency of the, it becomes possible to make it look more natural, which is very effective for presentations.

Note that S1 = 1 and S0 = 1 are the "blue back" and "shadow" areas, and this portion should not occur. However, if the color range of the chroma key condition data Dcon1 and Dcon2 is expanded too much,
Overlapping areas appear along the boundaries of the "shadow", and in the above example, the unexpected Vb (foreground) becomes prominently visible. At this time, if the conversion table of the code converter 40 is set as shown in FIG. 5C, Va (background) is output to Vout even when S1 = 1 and S0 = 1. Convenient without being hidden.

(Embodiment 4) FIG. 10 is a block diagram showing a chroma key combination circuit according to a fourth embodiment of the present invention. In this embodiment, the two mixing circuits 6, 7 and 24 in FIG.
Third embodiment by removing the large data selector 8 for selectively outputting bit pixel data and using one mixing circuit 3 and a small 8-bit data selector 9 for selectively outputting transparency data It implements the same function as the example with small hardware.

In FIG. 10, the data selector 9 is a 4-input selector that determines the output Y according to the selection control inputs S1 and S0. That is, the input signal A when S1 = 1 and S0 = 1, the input signal B when S1 = 0 and S0 = 1, the input signal C when S1 = 0 and S0 = 0,
When S1 = 1 and S0 = 0, the input signal D is output Y
Is selected as. The minimum value of the transparency data "00000000" (opaque data) is input to the A input of the data selector 9.
However, the maximum transparency data "11111111" (complete transparency data) is input to the B input, the first transparency data Tp1 from the outside synchronized with the clock signal is input to the C input, and the D input is synchronized with the clock signal. Second transparency data Tp2 from the outside
Are supplied respectively. The output Y of the data selector 9 is given to the mixing circuit 3.

Next, the operation of the embodiment shown in FIG. 10 will be described. The output up to the code converter 40 is exactly the same as in FIG. Since the data selector 9 supplies the output Y as described above to the mixing circuit 3 as a transparency signal, when the code converter 40 is set to "pass without conversion" as shown in FIG. The moving image data Vout as shown in FIG. 7 in which the transparency of “hand and arm” and “shadow” are different is obtained.

In the first to fourth embodiments, the input data A is used as the function of the first and second comparators 21 and 22.
Is a match signal "1" when matches the condition of condition data B
However, the present invention is not limited to this, and conversely "0"("1" when they do not match) may be output as the match signal. The selection rules of the data selectors 4, 5, 8 and 9 are not limited to those in each embodiment and can be freely designed. Once the selection rule suitable for the application is set, the code converter 40 is not always necessary.

Further, in each embodiment, there are two condition determining means for monitoring the pixel data of the foreground and outputting a match signal (key signal) when the condition is met, and corresponding to this, there are three data selector options. There are four or four. If there are three or more colors to be removed as keys, the condition determining means may be installed according to the number. For example, if there are three key colors of light blue, dark blue, and light green, three condition determining means are installed, and those colors are used for the first, second, and third condition data Dcon.
1, Dcon2, Dcon3, and their outputs may be supplied to the selection control inputs S2, S1, S0 of the data selector. At this time, each pixel can be changed in 2 × 2 × 2 = 8 ways, and the number of options can be increased. When you want to chrominically combine "hands and arms" with opacity and "shadows" with semi-transparency, the color of part of the "hands and arms" falls within the "blue back" setting range due to lighting. , If part of the “hand and arm” becomes transparent unexpectedly, narrow the setting color range of “blue back” and use multiple conditions to judge the color range of “hand and arm”. The transparent portion of the "hand and arm" may be restored by providing the determination means.

(Embodiment 5) FIG. 11 is a block diagram showing a chroma key composition circuit according to a fifth embodiment of the present invention. In the present embodiment, the code converter 40 is removed from FIG. 9 described in the third embodiment, and the color component of the pixel data Vb of the second moving image is removed to output only the luminance component and output the monochrome image. The conversion circuit 30 and the output data of the black-and-white conversion circuit 30 and the original pixel data Vb are appropriately switched to perform the first and second conversions.
The data selectors 31 and 32 for supplying to the B inputs of the mixing circuits 6 and 7 and the code converter 41 of 4-bit output are newly provided. As a result, the "shadow" that falls on the "background" becomes completely black and white (gray), and unnatural colors (blue, etc.) are eliminated, enabling more natural translucent composition.

In FIG. 11, a black-and-white circuit 30 is a circuit for inputting the pixel data Vb of the second moving image, removing its color components, and outputting only the luminance (gray) component,
FIG. 12 shows a configuration example thereof. In FIG. 12, 331 to
Reference numeral 333 is a coefficient circuit for multiplying input data by coefficients of 0.30, 0.59, and 0.11. Reference numeral 334 denotes a 3-input adder circuit that adds the output data of the coefficient circuits 331 to 333 and outputs an 8-bit result. The black and white circuit 30 uses RGB
Corresponding to the input pixel data Vb of each 8-bit structure, the 8-bit output data of the adder circuit 334 is overlapped three-fold and is apparently output as each 8-bit RGB structure. For example, as Vb, Vb = “11111111 (R) 111111
When the data of “11 (G) 00000000 (B)” (yellow) is input, the output of the adding circuit 334 becomes “11100011”, and the 24-bit output of the black-and-white circuit 30 becomes “11100011”.
(R) 11100011 (G) 11100011 (B) ”. The coefficients of the coefficient circuits 331 to 333 are Y /
Conversion formula to C (luminance / color difference) signal: Ey = 0.30 Er + 0.
The value is based on 59Eg + 0.11Eb, but the value is not limited to this value, and the coefficient may be set to a desired value.

Referring again to FIG. 11, the data selector 3
21 and 32 are the same as the data selector 4 of FIG. 21, and output the input signal B when the selection input S is "0" and the input signal A when the selection input S is "1", respectively. Is. A configuration example of the code converter 41 is shown in FIG. This is an extension of the code converter 40 of FIG. 4, 411 and 412 are 8-bit D flip-flops, and 413 to 416 are data selectors, all of which are known. 8-bit data bus D7 ~
Conversion code (data for code conversion) from D0 to D
The conversion rule (conversion table) can be freely set by writing in the flip-flops 411 and 412. A1, A0
FIG. 14 shows a setting example of the conversion table for converting Q3 to Q0. At this time, the D flip-flop 411,
“01001010” and “10111111” are written in 412, respectively.

Next, the operation of the embodiment shown in FIG. 11 will be described. Similar to the third embodiment (FIG. 9), the image shown in FIG. 7 is input as the pixel data Va and Vb of the first and second moving images, and if the image of Q2 of the code converter 41 of FIG.
Assuming that both Q3 outputs are fixed to "1",
The data selectors 31 and 32 input the pixel data V of the second moving image to the B inputs of the first and second mixing circuits 6 and 7, respectively.
In order to continue supplying b, the embodiment of FIG. 11 operates in exactly the same manner as the operation when the code converter 40 is set in FIG. 5 (c) in FIG. 9, and is the same as Vout in FIG. Is obtained. At this time, since the “shadow” of Vb in FIG. 7 is the shadow of the “hand and arm” that has fallen on the blue background, it is inevitably a “dark blue” “shadow”. Since this "dark blue""shadow" is semi-transparently combined with Va, the "shadow" that falls on the "building" of Vout becomes an unnatural "shadow" of "dark blue".

Therefore, in the embodiment of FIG. 11, the Q2 and Q3 outputs of the code converter 41 appropriately change according to the conversion table of FIG. In this example, the Q2 output outputs "1" in any case, and the second moving image pixel data Vb is directly connected to the B input of the first mixing circuit 6. Therefore, the "hands and arms" are semi-transparently synthesized with the transparency Tp1 while preserving the original color. The Q3 output normally outputs "1", but becomes "0" only when the pixel data Vb becomes a "shadow" pixel, that is, when the input A1 = 1 and A0 = 0. . As a result, the data selector 32 is switched from the A input to the B input, and the output data of the monochrome circuit 30 is supplied to the B input of the second mixing circuit 7.
The second mixing circuit 7 semi-transparently combines the "shadow" and the "building" (Va), which are black and white and have only the brightness (gray), with the transparency Tp2. That is, the “shadow” that falls on the “building” of Vout becomes a completely black and white (gray) with no unnatural color component, and an extremely natural “shadow” can be obtained in the composite moving image Vout.

If only the composite moving image shown in FIG. 7 is obtained, the 4-bit output code converter 41 is replaced with the 2-bit output code converter 40 (FIG. 9), and the data selectors 31 and 32 are removed. The pixel data Vb of the second moving image may be directly supplied to the B input of the first mixing circuit 6, and the output of the monochrome circuit 30 may be directly connected to the B input of the second mixing circuit 7.

(Sixth Embodiment) FIG. 15 is a block diagram showing a chroma-key synthesizing circuit according to a sixth embodiment of the present invention. In the present embodiment, the code converter 40 is removed from FIG. 10 described in the fourth embodiment, and the color component of the pixel data Vb of the second moving image is removed to output only the luminance component, which is a monochrome image. And a data selector 31 for appropriately switching the output data of the black-and-white circuit 30 and the original pixel data Vb to supply it to the B input of the mixing circuit 3.
And a 3-bit output code converter 42 are newly provided. As a result, the "shadow" that falls on the "background" becomes completely black and white (gray), and unnatural colors (blue, etc.) are eliminated, enabling more natural translucent composition.

In FIG. 15, the black-and-white circuit 30 and the data selector 31 are exactly the same as those of FIG. 11 (embodiment 5) having the same names and numbers. FIG. 16 shows a configuration example of the code converter 42. This is an extension of the code converter 40 of FIG. 4, and 421 and 422 are 8-bit and 4-bit D flip-flops, respectively, and 423-4.
Reference numeral 25 is a data selector, all of which are publicly known. A conversion code (data for code conversion) is transferred from the 8-bit data buses D7 to D0 to the D flip-flop 4
By writing in 21 and 422, the conversion rule (conversion table) can be freely set. FIG. 17 shows a setting example of a conversion table for converting A1 and A0 into Q2 to Q0. At this time, "01001010" and "1011" are written in the D flip-flops 421 and 422, respectively.

Next, the operation of the embodiment shown in FIG. 15 will be described. Similar to the fourth embodiment (FIG. 10), the image shown in FIG. 7 is input as the pixel data Va and Vb of the first and second moving images, and if the image data Q2 of the code converter 42 of FIG.
Assuming that the output is fixed to "1", the data selector 31 continues to supply the pixel data Vb of the second moving image to the B input of the mixing circuit 3, and thus the embodiment of FIG. The operation is the same as the operation when the code converter 40 is set to FIG. 5C, and a composite moving image exactly the same as Vout in FIG. 7 is obtained. At this time, since the “shadow” of Vb in FIG. 7 is the shadow of the “hand and arm” that has fallen on the blue background, it is inevitably a “dark blue” “shadow”. Since this "dark blue""shadow" is semi-transparently combined with Va, the "shadow" that falls on the "building" of Vout becomes an unnatural "shadow" of "dark blue".

Therefore, in the embodiment of FIG. 15, the Q2 output of the code converter 42 appropriately changes according to the conversion table of FIG. The Q2 output normally outputs "1", but becomes "0" only when the pixel data Vb becomes a "shadow" pixel, that is, when the inputs A1 = 1 and A0 = 0. As a result, the data selector 31 is switched from the A input to the B input, and the output data of the monochrome circuit 30 is supplied to the B input of the mixing circuit 3. Mixing circuit 3
Is a semi-transparent composite of the "shadow" and the "building" (Va), which have been converted into black and white and have only brightness (gray), with the transparency Tp2. That is,
The "shadow" that falls on the "building" of Vout becomes a completely black and white (gray) with no unnatural color component, and a very natural "shadow" can be obtained in the composite moving image Vout.

(Embodiment 7) FIG. 18 is a block diagram showing a chroma key composition circuit according to a seventh embodiment of the present invention. The first and second condition determining means 1 and 2, the mixing circuit 3 and the D flip-flops 901 to 906 in FIG. 18 have the same functions as in the first embodiment (FIG. 1). The present embodiment adopts a two-stage pipeline configuration by further providing five D flip-flops 909 to 913, and positively fixes all the inputs of the mixing circuit 3 when semitransparent synthesis is not required. By
This is a device that reduces power consumption.

In FIG. 18, reference numeral 11 denotes a first data selector, which determines the output Y from the two inputs A and B according to the selection control inputs S1 and S0. That is, "S
The input signal A is selected as the output Y when "1 = 0 and S0 = 0" or "S1 = 0 and S0 = 1", and otherwise the input signal B is selected. An arbitrary fixed transparency data (for example, "00" is input to the A input of the first data selector 11).
000000 ″), the transparency data Tp from the outside synchronized with the clock signal is supplied to the B input. The output Y of the data selector 5 is supplied to the mixing circuit 3 via the D flip-flop 912.

A second data selector 10 determines the output Y from the three inputs A, B and C according to the selection control inputs S1 and S0. That is, S1 = 0 and S0
= 1, the input signal A is selected as the output Y, the input signal B is selected when S1 = 0 and S0 = 0, and the input signal C is selected otherwise. This second data selector 1
The pixel data Va (background) of the first moving image is input to the A input of 0 through the two D flip-flops 901 and 909, and
The pixel data Vb (foreground) of the second moving image is supplied to the input via the two D flip-flops 902 and 910, and the output of the mixing circuit 3 is directly supplied to the C input.

Numeral 12 is the second and first condition judging means 2, 1
2 is a logic circuit for decoding the match signals m2 and m1. The logic circuit 12 outputs the fixed signal γ of "0" when semitransparent synthesis of Va and Vb is not required, that is, when Va or Vb should be directly output to Vout. Figure 1
In the example of FIG. 8, the fixed signal γ is set to “0” only when the match signals m2 and m1 of the second and first condition determining means 2 and 1 are 0, 0 or 0 and 1, respectively.

Normally, 13 and 14 pass the input 24-bit pixel data as it is and output it, and only when the fixed signal γ of "0" is asserted from the logic circuit 12 as a control input, a predetermined value is given. It is a gate circuit having a function of outputting a 24-bit fixed value. An example of the configuration is shown in FIG.
Shown in. Reference numeral 130 denotes a known AND gate, in which 24 pieces having the same function are arranged. When the fixed signal γ is “1”, the input signal passes through and is output as it is. When the fixed signal γ is “0”, that is, when the logic circuit 12 asserts the fixed signal γ, all bits are “0”. A 24-bit signal of "" is output.

Next, the operation of the embodiment shown in FIG. 18 will be described. The output data Vout is the same as that in the case where the code converter 40 is set to “pass without conversion” as shown in FIG. 5A in the first embodiment (FIG. 1). That is, the output Vout as shown in FIG. 6 is obtained.

First, for the sake of clarity, the D flip-flops 909 to 913 will be ignored. Focusing on the inputs A, B, and T of the mixing circuit 3, from the above description,
When semi-transparent composition of Va and Vb is not required, that is, in the case of a pixel in which Va or Vb can be output as it is (area other than the “shadow” of Vout in FIG. 6), the inputs A, B, and T have predetermined values. A fixed value is supplied. That is, if pixels that do not require semi-transparent composition are continuous, the logic of the mixing circuit 3 freezes during this period, and it becomes difficult to consume power. The effect is particularly great when the present chromakey synthesis circuit is composed of CMOS transistors, and the power consumption of the mixing circuit 3 becomes almost zero. Further, since the output of the mixing circuit 3 is frozen, a considerable effect that a large amount of logic associated with the input C of the second data selector 10 is frozen is also great. In the first embodiment, considering that the mixing circuit 3 having a large amount of hardware continues to operate (every clock) even when a pixel for semi-transparent synthesis is not necessary, the effect of reducing power consumption according to the present embodiment Is big.

Next, the pipeline operation will be described. The configuration of FIG. 18 is a two-stage pipeline.
D flip-flop 901 at the first clock pulse
~ 905 takes in the data and makes a condition decision, and at the second clock pulse, the D flip-flops 909-913 send the decision result to the mixing circuit 3 and the second data selector 10 for calculation, and at the third clock pulse. D
The flip-flop 906 synchronously outputs Vout to the outside. In the condition judging stage, it is decided whether or not to move the mixing circuit 3, a fixed signal γ for freezing the operation is prepared, and the next clock pulse is waited for.
The fixed signal γ arrives at the mixing circuit 3 at the arrival of the clock pulse, but if it is “frozen” at the immediately preceding clock pulse, the logic of the mixing circuit 3 does not change and power is not consumed.

A time chart of the circuit of FIG. 18 is shown in FIG. The n-th to (n + 4) th pixel data of Vb is a pixel that does not require translucent composition. It can be seen that Vout is output 2 clocks after the Va and Vb inputs. The A, B and T inputs of the mixing circuit 3 are "0" for 5 clocks.
And the power consumption of the mixing circuit 3 has been consumed for 4 clocks. When N pixels that do not require semitransparent composition are lined up consecutively, the power consumption of the mixing circuit 3 is eliminated during (N-1) clocks. In general, it is extremely rare that pixels requiring semi-transparent composition occupy the entire screen, and therefore, the effect of reducing the power consumption is large and extremely valuable.

The selection rules of the data selectors 10 and 11 and the decoding rules of the logic circuit 12 are not limited to those in this embodiment, and can be set freely according to the application. When the transparency data Tp does not change frequently, the data selector 11 may be removed and the transparency data Tp may be directly connected to the D flip-flop 912.
Between the D flip-flop 910 and the gate circuit 14,
It is also possible to insert a black-and-white circuit and a data selector in accordance with the fifth embodiment (FIG. 11).

(Embodiment 8) FIG. 21 is a block diagram showing a chroma key composition circuit according to an eighth embodiment of the present invention. In this embodiment, the configuration of the seventh embodiment is modified so that two transparency data are input. The difference from FIG. 18 is that the first data selector has changed from 2 inputs to 3 inputs.

In FIG. 21, reference numeral 16 is a first data selector, which determines the output Y from the three inputs A, B and C according to the selection control inputs S1 and S0. That is,
"S1 = 0 and S0 = 1" or "S1 = 1 and S0 =
1 ”, the input signal A is selected as the output Y, the input signal B is selected as the output Y when S1 = 0 and S0 = 0, and the input signal C is selected when the S1 = 1 and S0 = 0. An arbitrary fixed transparency data (for example, "00000000") is input to the A input of the first data selector 16, the first transparency data Tp1 from the outside synchronized with the clock signal is input to the B input, and the clock is input to the C input. The second transparency data Tp2 from the outside synchronized with the signal is supplied. The output Y of the first data selector 16 is given to the mixing circuit 3 via the D flip-flop 912.

A second data selector 17 determines the output Y from the three inputs A, B and C according to the selection control inputs S1 and S0. That is, S1 = 0 and S0
= 1, the input signal A is selected as the output Y, the input signal B is selected when S1 = 1 and S0 = 1, and the input signal C is selected as the output Y otherwise. This second data selector 1
The pixel data Va (background) of the first moving image is input to A of 7
However, the pixel data Vb (foreground) of the second moving image is input to B.
However, the output of the mixing circuit 3 is supplied to each C input.

Reference numeral 15 designates second and first condition judging means 2, 1
2 is a logic circuit for decoding the match signals m2 and m1. The logic circuit 15 outputs a fixed signal γ of "0" when semitransparent synthesis of Va and Vb is not required, that is, when Va or Vb should be directly output to Vout. Figure 2
In the first example, the fixed signal γ is set to “0” only when the match signals m2 and m1 of the second and first condition determining means 2 and 1 are 0, 1 or 1, 1.

Next, the operation of the embodiment shown in FIG. 21 will be described. Similar to the third embodiment (FIG. 9), the pixel data Va and Vb of the first and second moving images, the first and second condition data Dcon1 and Dcon2, and the first and second transparency data Tp1. , T
supply with p2. In the "hand and arm" part, the result of the semi-transparent composition according to the first transparency data Tp1 by the mixing circuit 3 is shown, and in the "shadow" part, the semi-transparency according to the second transparency data Tp2 by the same mixing circuit 3 is shown. Since the result of the combination is reflected in the output Vout, the moving image data Vout as shown in FIG. 7 in which the transparency of the "hand and arm" and the "shadow" are different is obtained.

Further, similarly to the seventh embodiment (FIG. 18),
A two-stage pipeline operation is executed. Moreover, when semi-transparent synthesis is not required, the input A of the mixing circuit 3,
Since B and T are all fixed, the power consumption of the mixing circuit 3 becomes almost zero.

The selection rules of the data selectors 16 and 17 and the decoding rules of the logic circuit 15 are not limited to those in this embodiment, and can be set freely according to the application. It is also possible to insert a black and white circuit and a data selector between the D flip-flop 910 and the gate circuit 14 as in the fifth embodiment (FIG. 11).

[0064]

As described above, according to the present invention, a plurality of condition judging means for judging the color range of each pixel data are provided, and when the background moving image is pointed by the foreground moving image, Some areas of the foreground video (for example,
Since only the "shadow" or both the "hand and arm" and the "shadow" are translucently combined with the background moving image, it is possible to realize pointing without covering the background with the foreground. The "hands and arms" and the "shadow" of the foreground can be semi-transparently combined with the background moving image with different transparency. Furthermore, by selectively turning a part of the foreground video into black and white (gray), the original black and white (gray) "shadow" that does not mix unrelated colors can be dropped into the background video. It enables more natural pointing and effective presentation. Therefore, the present invention exerts an extremely excellent value in applications such as a multimedia computer and a presentation system using a video moving image as a communication means.

[Brief description of drawings]

FIG. 1 is a block diagram of a chroma key synthesis circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration example of two comparators in FIG.

3 is a circuit diagram showing a configuration example of a mixing circuit in FIG.

FIG. 4 is a circuit diagram showing a configuration example of a code converter in FIG.

5A to 5C are diagrams showing three setting examples of a conversion table of the code converter of FIG.

6 is a schematic diagram of the chroma key synthesis circuit of FIG.
It is a figure which shows operation | movement at the time of adopting the conversion table of.

7 is a diagram of the chroma-key synthesizing circuit of FIG.
It is a figure which shows operation | movement at the time of adopting the conversion table of.

FIG. 8 is a block diagram of a chroma key composition circuit according to a second embodiment of the present invention.

FIG. 9 is a block diagram of a chroma key composition circuit according to a third embodiment of the present invention.

FIG. 10 is a block diagram of a chroma key composition circuit according to a fourth embodiment of the present invention.

FIG. 11 is a block diagram of a chroma key composition circuit according to a fifth embodiment of the present invention.

FIG. 12 is a circuit diagram showing a configuration example of a monochrome circuit in FIG.

13 is a circuit diagram showing a configuration example of a code converter in FIG.

14 is a diagram showing a setting example of a conversion table of the code converter of FIG.

FIG. 15 is a block diagram of a chroma key composition circuit according to a sixth embodiment of the present invention.

16 is a circuit diagram showing a configuration example of a code converter in FIG.

17 is a diagram showing a setting example of a conversion table of the code converter of FIG.

FIG. 18 is a block diagram of a chroma key composition circuit according to a seventh embodiment of the present invention.

19 is a circuit diagram showing a configuration example of two gate circuits in FIG.

FIG. 20 is a time chart showing the operation of the chroma key combination circuit of FIG. 18.

FIG. 21 is a block diagram of a chroma key composition circuit according to an eighth embodiment of the present invention.

FIG. 22 is a block diagram showing a configuration of a conventional chroma key synthesis circuit.

FIG. 23 is a diagram showing an operation of the chroma key combination circuit of FIG. 22.

[Explanation of symbols]

1, 2 Condition determination means 3, 6, 7 Mixing circuit 4, 5, 8-11, 16, 17, 31, 32 Data selector 12, 15 Logic circuit 13, 14 Gate circuit 21, 22 Comparator 30 Monochrome circuit 40 , 41, 42 Code converter 130, 206-209 AND gate 200-205 Magnitude comparator 301, 302, 304, 305, 307, 308 Multiplier circuit 303, 306, 309, 334 Adder circuit 310 Complement conversion circuit 331-333 Coefficient circuit 401, 411, 412, 421, 422, 901-9
13 D flip-flops 402, 403, 413 to 416, 423 to 425 data selector

Claims (13)

[Claims] 1. A chroma key combination circuit for generating a combined moving image of the first moving image and the second moving image in real time with the first moving image as a background, the pixel data of the first moving image and the pixel data of the first moving image. First means for inputting pixel data of a second moving image in synchronization with a clock signal, and first means for indicating whether the input pixel data of the second moving image satisfies a first condition And a second means for generating a second binary signal indicating whether or not the input pixel data of the second moving image satisfies a second condition. 3 means, and the input first moving image pixel data so as to achieve a completely transparent composition, an opaque composition and a semi-transparent composition in accordance with the code composed of the first and second binary signals. And the input second moving image pixel data, and the input Fourth means for selectively outputting one of pixel data obtained by performing weighted addition on the pixel data of the first and second moving images; and pixel data output from the fourth means And a fifth means for outputting as pixel data of the composite moving image in synchronization with the clock signal. 2. The chroma-key synthesizing circuit according to claim 1, wherein the data indicating the first and second conditions in the second and third means respectively specify a color range of pixel data. A chroma key composition circuit further comprising means for externally inputting the condition data of 1. 3. The chroma-key synthesizing circuit according to claim 1, wherein the means for externally inputting transparency data designating weight distribution of weighted addition of pixel data of the first and second moving images in the fourth means. A chromakey synthesis circuit characterized by further comprising. 4. The chroma-key synthesizing circuit according to claim 1, wherein the chroma-key synthesizing circuit comprises the first and second binary signals interposed between the second and third means and the fourth means. A chroma key synthesizing circuit, further comprising means for converting the code according to a rule of variable setting. 5. The chroma-key synthesizing circuit according to claim 1, wherein the fourth means performs weighted addition on the input pixel data of the first and second moving images by weight distribution according to given transparency data. Then, mixing means for outputting the pixel data obtained by the weighted addition, and complete transparent synthesis, opaque synthesis and semitransparent synthesis are achieved according to the code composed of the first and second binary signals. As described above, one of the pixel data of the input first moving image, the pixel data of the input second moving image, and the pixel data output from the mixing unit is selectively selected as described above. Chroma key combination circuit, comprising: selecting means for supplying to the fifth means. 6. The chroma key combination circuit according to claim 5, wherein the mixing unit removes a color component from the pixel data of the input second moving image, and monochrome pixel data obtained by removing the color component. And a black-and-white circuit for outputting, and which of the pixel data of the input second moving image and the black-and-white pixel data, depending on the code composed of the first and second binary signals. Or a data selector for selectively outputting the pixel data of the input first moving image and the pixel data output from the data selector, and weighted addition is performed with weight distribution according to given transparency data. A mixing circuit for supplying the pixel data obtained by the weighted addition to the selecting means. 7. The chroma-key synthesizing circuit according to claim 5, wherein the mixing unit weights the input pixel data of the first and second moving images with a weight distribution corresponding to the given first transparency data. A first mixing circuit for adding and supplying pixel data obtained by the weighted addition to the selecting means; a color component is removed from the input second moving image pixel data; A black-and-white circuit for outputting black-and-white pixel data obtained by the removal, and a weight distribution according to the second transparency data given the pixel data of the input first moving image and the black-and-white pixel data. And a second mixing circuit for performing weighted addition and supplying the pixel data obtained by the weighted addition to the selecting means. 8. The chroma-key synthesizing circuit according to claim 5, wherein the selecting means selects one of the pixel data of the input first moving image and the pixel data of the input second moving image. The chroma-key synthesizing circuit further comprises means for stopping the weighted addition operation of the mixing means in the case of performing. 9. The chroma-key synthesizing circuit according to claim 1, wherein the fourth means corresponds to a code composed of the first and second binary signals, and corresponds to a completely transparent synthesizing method. Fixed transparency data, second fixed transparency data corresponding to opaque composition,
Selection means for selectively outputting one of the transparency data corresponding to semi-transparent composition, and the transparency data output from the selection means for the pixel data of the input first and second moving images. And a mixing means for supplying the pixel data obtained by the weighted addition to the fifth means, the chroma-key synthesizing circuit. 10. The chroma-key synthesizing circuit according to claim 9, wherein the mixing unit removes a color component from the pixel data of the input second moving image, and monochrome pixel data obtained by removing the color component. And a black-and-white circuit for outputting, and which of the pixel data of the input second moving image and the black-and-white pixel data, depending on the code composed of the first and second binary signals. Or a data selector for selectively outputting the pixel data of the input first moving image and the pixel data output from the data selector in accordance with the transparency data output from the selecting means. And a mixing circuit for supplying the pixel data obtained by the weighted addition to the fifth means. 11. A chroma-key synthesizing circuit having a pipeline structure for generating in real time a composite moving image of the first moving image and the second moving image against the background of the first moving image, A first D flip-flop for holding and outputting pixel data in synchronization with a clock signal; and a first D flip-flop for holding and outputting pixel data of the second moving image in synchronization with the clock signal. Two D flip-flops, and holds the pixel data of the first moving image output from the first D flip-flop in synchronization with the clock signal,
And a third D flip-flop for outputting the pixel data of the second moving image output from the second D flip-flop in synchronization with the clock signal,
And a fourth D flip-flop for outputting, and a first indicating whether or not the pixel data of the second moving image output from the second D flip-flop satisfies the condition indicated by the first condition data. First for generating a binary signal of
And a second binary signal indicating whether or not the pixel data of the second moving image output from the second D flip-flop satisfies the condition indicated by the second condition data. Second
Of the comparator and the code composed of the first and second binary signals, the fixed signal asserted in the case of a pixel not requiring translucent synthesis In some cases, a logic circuit for outputting the respective fixed signals that are not asserted, a fifth D flip-flop for holding and outputting the given transparency data in synchronization with the clock signal, and A sixth D flip-flop for holding and outputting a fixed signal output from a logic circuit in synchronization with the clock signal, and a code composed of the first and second binary signals. A seventh D flip-flop for holding and outputting in synchronization with the clock signal, and the sixth D flip-flop for outputting the fixed signal that is not asserted when the sixth D flip-flop is output. The pixel data of the first moving image output from the D flip-flop is output as it is, and when the fixed signal asserted from the sixth D flip-flop is output, the pixel data of the first moving image is output. A first gate circuit for outputting alternative fixed pixel data; and a fourth gate circuit output from the fourth D flip-flop when a non-asserted fixed signal is output from the sixth D flip-flop. For outputting the pixel data of the second moving image as it is, and for outputting the fixed pixel data instead of the pixel data of the second moving image when the fixing signal asserted from the sixth D flip-flop is output. The second gate circuit, the pixel data output from the first gate circuit and the pixel data output from the second gate circuit are combined into the fifth D-free circuit. A weighting addition in accordance with the weight distribution according to the transparency data output from the flip-flop, and outputting pixel data obtained by the weighted addition, and a mixing circuit according to the code output from the seventh D flip-flop The pixel data of the first moving image output from the third D flip-flop and the second pixel output from the fourth D flip-flop so as to achieve completely transparent synthesis, opaque synthesis, and semi-transparent synthesis. A data selector for selectively outputting one of the pixel data of the moving picture and the pixel data output from the mixing circuit; and synchronizing the pixel data output from the data selector with the clock signal. An eighth D flip-flop for holding and outputting as pixel data of the composite moving image, wherein the data selector is Note If the code output from the seventh D flip-flop is the code that outputs the fixed signal asserted from the logic circuit, the pixel of the first moving image output from the third D flip-flop It is fixed that the code output from the seventh D flip-flop is not asserted from the logic circuit for any one of the data and the pixel data of the second moving image output from the fourth D flip-flop. A chroma-key synthesizing circuit having a function of selecting each pixel data output from the mixing circuit when the code is a code to be output. 12. The chroma-key synthesizing circuit according to claim 11, wherein the code composed of the first and second binary signals is a code to which a non-asserted fixed signal is output from the logic circuit. At least one variable transparency data supplied in synchronization with the clock signal is output as a fixed signal in which a code composed of the first and second binary signals is asserted from the logic circuit. In the case of a code, the chroma key composition circuit further comprising a data selector for supplying fixed transparency data instead of the variable transparency data to the fifth D flip-flop. 13. The chroma key combination circuit according to claim 11, wherein a color component is removed from the pixel data of the second moving image output from the fourth D flip-flop, and a black and white obtained by removing the color component. A black-and-white circuit for outputting pixel data; and pixel data of the second moving image output from the fourth D flip-flop and the black-and-white conversion in accordance with the code output from the seventh D flip-flop. A chroma key combination circuit, further comprising a data selector for selectively supplying any one of the black and white pixel data output from the circuit to the second gate circuit.