JPH07221718A - Radio communication equipment - Google Patents

Abstract

PURPOSE:To improve the sound quality by implementing a prescribed arithmetic operation when transmission error data are corrected by using a cyclic code and comparing the processed data with an error pattern so as to correct the transmission error data even when a random error takes place. CONSTITUTION:A CRC system error detection circuit 3 generates a frame error signal 4 and CRC residue data 5. Residue data obtained when an error takes place in received data and its error position are stored in a residue data table 6 in pairs. A comparator 12 compares the CRC residue data with all of residue data of 196 patterns stored in the residue table 6, and outputs a signal 14 whose level is logical 1 when any matching pattern is in existence and the signal 14 whose level is logical 0 when no matching pattern is in existence. A correction circuit 11 corrects a signal of a location based on error location data 8 from the table 6 when the level of the signal 14 is logical 1 and passes the signal as it is when the level of the signal 14 is logical 0. A code processing circuit 24, an ADPCM decoding circuit 28 and a band compressor 30 or the like are the same as those of a conventional communication equipment.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wireless communication device applicable in the communication field such as a digital cordless telephone.

[0002]

2. Description of the Related Art In the currently standardized digital cordless telephone system (RCR STD-28), 32 kbps ADPCM (Adaptive Diode) of the ITU-T Recommendation G.721 standard is used as a voice codec.
fferential pulse code modulation) is used.
In digital cordless telephones, ADPCM data, which is a voice signal, has 40 samples as one frame and check bits for error detection (remainder bits generated by a 16-bit generator polynomial according to ITU-T recommendation) for each frame. In addition, it is connected as a TDMA (Time Division Multiple Access) system. The ITU-T Recommendation G.721 standard has been developed on the assumption that it is used for a wired path that originally has a low error rate, and does not take into consideration errors in wireless communication paths where various kinds of errors may occur. Therefore, when using the ITU-T Recommendation G.721 standard for digital cordless telephones, it is difficult to guarantee communication quality unless some kind of error countermeasure is taken.

In conventional transmission error countermeasures, each frame is
Performs error detection by the CRC (Cyclic Redundancy Check) method, determines whether a transmission error has occurred in the frame, and if there is a transmission error, muting operation and replacement of frame data shown below. It is common to focus on.

Here, Japanese Patent Laid-Open No. 4-263528 (Applicant: NT
T, title of invention: voice muting system). In this method, muting processing is applied to each of the input voice and the output signal.

The following processes <1> to <6> are performed on the input signal. That is, <1> The erroneous voice frame is replaced with a specific pattern prepared in advance.

<2> Replace an erroneous voice frame with a previously input error-free voice frame.

<3> An error-free speech frame is replaced with a previously input error-free speech frame converted by a specific code conversion.

<4> An erroneous speech frame is replaced with a previously input erroneous speech frame that has been subjected to a specific code conversion.

<5> When an erroneous voice frame is continuously input, when the number of frames is less than a certain value, it is replaced with the previously input error-free voice frame, and when the number is more than a certain value, Replace with a specific pattern prepared in advance.

<6> When erroneous voice frames are continuously input, when the number of frames is less than a certain value, the previously input error-free voice frame is replaced, and when the number of frames is more than a certain value, The error-free voice frame is replaced with the one with a specific code conversion.

The following processings <7> and <8> are performed on the output signal. That is, <7> the output signal voice band is reduced.

<8> The volume of the output signal is reduced.

That is, when a voice data frame named A, B, C, D is input and a transmission error occurs in B, C, D,
These data frames are processed as follows (where X is a data frame that does not correlate with B, C, D prepared in advance, and is a constant value used in <5> and <6> above. Is set to 2. Also, a, b, c, d are A, B, C, D respectively subjected to a certain code conversion).

<1>, A, X, X, X <2>, A, A, A, A <3>, A, a, a, a <4>, A, b, c, d <5>, A, A, A, X <6>, A, A, A, a

[0015]

The above-described method is effective because, when errors occur continuously during transmission, the peak noise generated at that time is suppressed.

However, when a random error occurs, the use of the above-mentioned method causes a distortion in a portion of the output voice that is originally free from errors, which leads to a deterioration in voice quality.

Further, in consideration of the case where a random error occurs in the conventional processing, when adjusting the degree of muting or replacement of frame data, the noise suppressing action in the case where errors occur continuously is reduced. Resulting in.

The object of the present invention is to solve the above problems,
An object of the present invention is to provide a wireless communication device capable of correcting transmission error data by using a cyclic code and improving voice quality.

[0019]

SUMMARY OF THE INVENTION The present invention is based on arithmetic means for performing a predetermined arithmetic operation on data including ADPCM data and cyclic code by the cyclic code, and on the basis of the arithmetic result by the arithmetic means.
A judgment means for judging whether or not the ADPCM data has an error, and a comparison means for comparing the calculation result by the calculation means with a predetermined error pattern when a positive judgment is made by the judgment means, and a comparison result by the comparison means. If both match, the correction means for correcting the data at the error position is provided.

[0020]

According to the present invention, the data including the ADPCM data and the cyclic code is subjected to the predetermined calculation by the calculation means by using the cyclic code, and based on the calculation result, the determination means determines whether or not the ADPCM data has an error. If the result of the determination is affirmative, the comparison means compares the calculation result of the calculation means with a predetermined error pattern. If the comparison results in a match, the correction means corrects the error position data.

[0021]

Embodiments of the present invention will now be described in detail with reference to the drawings.

<First Embodiment> FIG. 1 shows a first embodiment of the present invention. In this example, in one frame of input ADPCM data,
This is an example of making a correction when only one bit is erroneous, but it is also applicable to an error of two or more bits. In FIG. 1, 1 is a received code, and one frame (196 bits) is sent every 5 ms. The reception code 1 is shown in FIG.
As shown in, it is composed of a CI bit (4 bits), a SACCH bit (16 bits), ADPCM data (160 bits), and a CRC check bit (16 bits). ADPC
M data (160 bits) is voice with 4 bits at 8 kHz.
Obtained by sampling 40. Reference numeral 2 denotes a reception code buffer for buffering the reception code 1. Reference numeral 7 is the received ADPCM data. Reference numeral 11 is a circuit composed of the modifier 20 and the selector 16.

Reference numeral 3 denotes a CRC type error detection circuit, which is an ITU-T
It is the generator polynomial defined by the above, that is, the CRC check bit (16 bits), and 180 bits except the CRC check bit (16 bits) of the reception code 1 are divided. Reference numeral 4 is a signal indicating a frame error. When the remainder by the generator polynomial is "0" and when the received frame has no error, it is "0". When the remainder is not "0" and the received frame has an error, Becomes '1'. Reference numeral 5 is 16-bit remainder data obtained by dividing the reception code 1 by the generator polynomial. If there are no errors, all 16 bits are zero.

Reference numeral 6 is a residual data table prepared in advance, and there are 196 error patterns. Here, 1
The residual data obtained when an error occurs in the received data for processing the bits is stored in the table together with the error position. That is, a pair of error position information and residual data generated when an error occurs at that position is stored in the table as follows.

0xba95 ... 1st bit of ADPCM data section 0xd55a ... 2nd bit of ADPCM data section 0x6aad ... 3rd bit of ADPCM data section Calculation of table data creation has no error in the data at each position of the received code. This is possible by replacing and finding the remainder divided by the generator polynomial.

The true data in this table is obtained by calculation in advance, but it can be realized by calculating each time without holding the table as the processing speed improves.

Numeral 8 is position information stored in the remainder data table 6. Numeral 10 is remainder data obtained when an error occurs in each error position stored in the remainder data table 6.

Reference numeral 12 is a comparator, which compares all the surplus data 5 from the CRC error detection circuit with the surplus data of 196 patterns stored in the surplus data table 6, and the matched values are stored in the surplus data table 6. When it exists'
It outputs a 1'signal and a '0' signal when it does not exist. Reference numeral 14 is a signal of "0" or "1" output from the comparator 12. 9 is a gate, and the signal 14 is'
When it is 1 ', the frame error signal is invalidated and the circuit 11 is brought into a state without frame error. When the signal 14 is “0”, the frame error signal 4 is sent to the circuit 11 as it is.

Reference numeral 16 is a selector which, when the signal 14 is "1", processes the ADPCM data 22 from the modifier 20 into the processing circuit 2
When the signal 14 is "0", the received ADPCM 7 is sent to the processing circuit 24 as it is. 17 is selector 1
It is the ADPCM data selected by 6. Reference numeral 20 is a corrector, which is "0" when the data is "0" with respect to the data at the error position in the case of digital data such as ADPCM.
It is corrected to 1 ', and when the data is'1', it is corrected to '0'. Reference numeral 22 is ADPCM data corrected by the correction unit 20.

Reference numeral 24 is a processing circuit for performing the processing <1> to <6> of the conventional example. 28 is ITU-T Recommendation G.
It is an ADPCM decoder defined by 721 and decodes the processing result of the processing circuit 24. Decodes 4-bit ADPCM data serially at 8kHz. Reference numeral 30 is a processing circuit, which is a conventional circuit for the output of the ADPCM decoder 28.
It processes <7> and <8>.

FIG. 3 is a flowchart showing an example of the error correction processing procedure.

In step S2, CRC method error detection is performed, the remainder is obtained, and in step S4, the remainder calculated from the received code is compared with the remainder table of the remainder table. If a matching code is found in the remainder table as a result of the comparison, the process proceeds to step S6, and the correction is performed based on the error position information in step S6. That is,
If the error position data is "0", modify it to "1", and if the error position data is "1", modify it to "0".

<Second Embodiment> FIG. 4 shows a second embodiment of the present invention.

Compared with the first embodiment, this embodiment is as follows.
The 1-bit error detection and correction circuits are different. That is, in the first embodiment, the remainder table 6 and the comparator 12
And the circuit 11.

On the other hand, in this embodiment, the exclusive OR gate 41, the down counter 42, and the logic circuit 43.
The logic circuit 43 outputs 9-bit data to the input of 16-bit remainder data, and 8 bits of the output true data are ADPCM in 196 bits.
With respect to the remainder data input corresponding to the 1-bit error in the data part, the error positions 0 to 159 corresponding to the error position are output. Further, a value of 160 or more (error position) is output in cases other than the residual data corresponding to the 1-bit error and in the case of the residual data corresponding to the 1-bit error corresponding to the part other than the ADPCM data part. 1 bit of output data is 1
This is a 1-bit error detection bit that outputs "1" when the residual data corresponding to the 1-bit error is input to the 96-bit data. The 8-bit ADPCM data error position data is loaded into the down counter 42 in synchronization with a frame of every 40 samples (160 bits = 4 bits × 40 samples). The down counter 42 is down-counted by the ADPCM transfer clock, and outputs "1" in the 1-bit section from RCO at the set error position. For example, 0
If is set, '1' is output in the first 1-bit section of ADPCM. By taking the exclusive OR of the RCO and the ADPCM data by the exclusive OR gate 41, the ADPCM data can be corrected. The down counter 42 is loaded with a value for each frame,
If no correction is necessary, a value of 160 or more is set, and no correction is performed, so that the function of the selector shown in FIG. 1 can be substituted.

In the first and second embodiments, the ADPCM data is not corrected when there is a continuous error, but the muting and frame data replacement that is most effective for the continuous error is performed by the conventional processing. It can be treated.

[0037]

As described above, according to the present invention,
With the above configuration, it is possible to correct the transmission error data by using the cyclic code and improve the voice quality.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing a configuration example of received data.

FIG. 3 is a flowchart showing an example of an error correction processing procedure.

FIG. 4 is a block diagram showing a second embodiment of the present invention.

[Explanation of symbols]

 2 buffer 3 CRC method error detection circuit 6 remainder data table 9 gate 11 circuit 12 comparator 16 selector 20 corrector 24, 30 processing circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yasukazu Mizushima Asahi Kasei Kogyo Co., Ltd. 221, Tanasawa, Atsugi City, Kanagawa Prefecture

Claims (1)

[Claims] 1. A calculation means for performing a predetermined calculation on data including ADPCM data and a cyclic code by the cyclic code, and a judgment means for judging whether or not the ADPCM data has an error based on a calculation result by the calculation means. If the determination means makes an affirmative determination, the comparison means compares the calculation result of the calculation means with a predetermined error pattern, and the comparison result of the comparison means indicates that they match.
A wireless communication apparatus comprising: a correction unit that corrects data of an error position.