JPH07221668A - Digital radio equipment terminal - Google Patents

Abstract

PURPOSE:To obtain a stable operation and realize power saving by selecting an impedance element which is almost equal to the input impedance of the PLL frequency synthesizer at burst timing at non-burst timing. CONSTITUTION:By the switch of the load changeover switch 240 connected with a PLL frequency synthesizer 224, a resistor 250 as a buffer amplifier 223 or an impedance element is selectively connected with the PLL frequency synthesizer 224. In this case, the changeover switch 240 performs a switch operation by the control command of a control part, connects the PLL frequency synthesizer 224 with a buffer amplifier 223 at the burst timing of a first slot to be used in transmission/reception of a period for transmission and a period for reception, for instance, and connects the synthesizer with the resistor 250 at the non-burst timing other than this.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time-division multiplex type digital wireless terminal device which realizes power saving (power saving).

[0002]

2. Description of the Related Art Recently, a time-division multiplex type digital wireless terminal device has been widely used as a portable terminal device capable of calling a caller from outside to talk. By the way, in such a portable wireless terminal device, in order to minimize the temperature rise due to the extension of the battery life and the heat generation of the device itself due to the restrictions of the battery capacity, etc. I try to save power.

FIG. 5 shows a partial schematic structure of an antenna section and a high frequency section of a digital wireless terminal device.
Is an antenna section, and a high frequency section 200 is connected to the antenna section 100.

The high frequency unit 200 performs a frequency conversion process, and connects the receiving unit 220 and the transmitting unit 230 via a band pass filter (BPF) 210 and an antenna switch unit 211. The receiving unit 220 uses the antenna 10
The 1.9 GHz band received signal input from 0 is taken into the first stage mixer 222 via the RF amplifier 221 and converted into a 250 MHz signal based on the frequency of the PLL frequency synthesizer 224 connected via the buffer amplifier 223. The frequency is converted and given to the IF amplifier 225.
The signal is taken into the second stage mixer 227 via the bandpass filter (BPF) 226, frequency-converted into a signal of 10.7 MHz based on the oscillation frequency of the local oscillator 228, and the IF amplifier 229 and the bandpass filter (BPF) are provided.
The data is output to the next modem via the 2291.

On the other hand, in the transmission section 230, the modulated wave of π / 4 shift QPSK input from the modem is taken into the mixer 232 via the bandpass filter (BPF) 231, and is passed through the buffer amplifier 223 as described above. Based on the frequency of the connected PLL frequency synthesizer 224, the frequency is converted into the same frequency as the received signal (1.9 GHz band), and this is converted from the antenna switch unit 211 and the BPF 210 to the antenna 100 via the power amplifier 233.
I am trying to output to.

Thus, in the digital wireless terminal device, transmission / reception is performed at a predetermined burst timing as described above. Now, as shown in FIG. 3, the burst timing is prepared for each four slots. If one frame is composed of a and the reception period b and the first slot is used for transmission / reception, the transmission / reception operation is not performed for the other three slots (6 slots in total). Therefore, only during this period, the RF amplifier 221 and the IF amplifier 22 of the receiving unit 220
5, 229 and the power amplifier 233 of the receiver 230
Power saving is realized by so-called sleep control that stops the operation of peripheral circuits such as.

[0007]

However, such a burst operation of the receiving section 220 and the receiving section 230 in synchronization with the burst timing means that the input impedance to the PLL frequency synthesizer 224 is in the transmitting / receiving operation state. In other cases, it will change, and this will affect the PLL frequency synthesizer 224 as a load change. This state will be described with reference to the Smith chart shown in FIG.
The input impedance of the PLL frequency synthesizer 224 and the buffer amplifier 223 are matched at A at the burst timing when the receiving unit 230 is in the transmission / reception state, but at the non-burst timing, the input impedance of the amplifier 223 shifts to the vicinity of B open. , The reflection coefficient increases. Therefore, if the PLL frequency synthesizer 224 is operated in this state, a large load fluctuation is given to the PLL frequency synthesizer 224, stable operation cannot be performed, and its characteristics are significantly deteriorated.

Therefore, the PLL frequency synthesizer 224
In order to guarantee the stable operation of the device, it is conceivable to stop the sleep control of the peripheral circuits including the amplifier and operate all the slots in the transmission period a and the reception period b, but this saves power. There was a problem that I could not get it at all.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a digital wireless terminal device capable of achieving stable operation of a PLL frequency synthesizer and realizing power saving.

[0010]

According to the present invention, there is provided a digital wireless terminal device having a high frequency section for performing a frequency conversion process on a signal transmitted and received at a predetermined burst timing by using a PLL frequency synthesizer.
A switching means connected to a frequency synthesizer and switched at the predetermined burst timing, and an impedance substantially equal to the input impedance of the PLL frequency synthesizer at the predetermined burst timing are set, and the switching means transmits and receives the signal. And an impedance element connected to the PLL frequency synthesizer at a non-burst timing other than the predetermined burst timing.

[0011]

As a result, according to the present invention, the impedance of the non-burst timing is set to a value substantially equal to the input impedance of the PLL frequency synthesizer at the burst timing by the switching operation of the switching means which is switched at a predetermined burst timing. Since the element is selected, the input impedance of the PLL frequency synthesizer can be set to a state almost equal to the input impedance at the burst timing at which signal transmission / reception is always executed, and the load fluctuation to the PLL frequency synthesizer can be set. It can be reduced significantly.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a schematic configuration of a digital wireless terminal device to which the present invention is applied. In this case, 100 is an antenna, and the high frequency unit 200 is connected to the antenna 100. The high frequency unit 200 performs frequency conversion processing and includes an antenna switch unit 211, a receiving unit 220, a transmitting unit 230, and a PLL frequency synthesizer 224.

The modem 1 is connected to the high frequency section 200.
3, TDMA14, speech codec 15 and P
A CM 16 is connected, and a speaker 18 on the receiving side and a microphone 19 on the transmitting side are connected to the PCM 16 via an amplifier 17.
Are connected.

Here, the modem 13 uses a π / 4 shift QP
SK modulation and demodulation processing is performed, and at the receiving side, the receiving unit 2
IF signal from 20 is demodulated and separated into IQ data,
The data is transferred to the TDMA 14 as a data string, and on the transmitting side, IQ data is created from the data transferred from the TDMA 14, and π / 4 shift QPSK modulation is performed and the IQ data is sent to the transmitting unit 230.

The TDMA 14 performs signal processing corresponding to time division multiplex connection, that is, frame synchronization and slot format processing. On the receiving side, scrambling of data in a predetermined slot sent from the modem 13 is released. Then, the configuration data is taken out from the format of this slot, and the control data is stored in the control unit 2 which will be described later.
0, the voice data is transferred to the speech codec 15, and on the transmitting side, the control data is added to the voice data transferred from the speech codec 15 to create slot data, which is scrambled at a predetermined timing. The slot data is inserted into the frame at (assigned transmission time slot) and transferred to the modem 13.

The speech codec 15 performs compression / expansion processing of digital data.
ADPCM audio signal (4bi) sent from MA14
t × 8 KHz = 32 Kbps for PCM audio signal (8 b
(it × 8 KHz = 64 Kbps), it is expanded by decoding and output to PCM16.
The PCM voice signal sent from the D.6 is compressed by being encoded into the ADPCM voice signal and sent to the TDMA 14.

The PCM 16 performs analog / digital processing. On the receiving side, the PCM audio signal sent from the speech codec 15 is converted into an analog signal by D / A conversion, and then output to the amplifier 17 for output to the speaker. 18 and a microphone 19 on the transmitting side.
A / D conversion of the analog audio signal input from the PC
The M audio signal is output to the speech codec 15. The PCM 16 also controls the volume, ringer R, tone signal and the like.

The high frequency section 12 and the modem 1
3, TDMA14, speech codec 15 and P
A control unit 20 is connected to the CM 16 and the control unit 20
ROM 21, RAM 22, recording / reproducing circuit 23, memory 2
4, the display unit 25 and the key input unit 26 are connected.

Here, the ROM 21 stores the control program in the control section 20. The RAM 22 temporarily stores the data handled by the control of the control unit 20. Further, the recording / reproducing circuit 23 records and reproduces a message when it is used as an answering machine. The memory 24 stores a typical response message when it is used as an answering machine. Display 25
Displays input data and results for various controls. The key input unit 26 is adapted to give a key input for setting various functions to the control unit 20.

FIG. 2 shows a schematic structure of the high frequency section 12. In FIG. 2, the same parts as those in FIG. 5 described above are denoted by the same reference numerals. In this case, a load switching switch 240 is connected to the PLL frequency synthesizer 224, and the buffer amplifier 223 is switched by switching the switching switch 240. Alternatively, the resistor 250 as an impedance element
Are selectively connected to the PLL frequency synthesizer 224.

In this case, the changeover switch 240 performs a changeover operation according to the control command of the control unit 20 described above. For example, the first switch used for transmission / reception in the transmission period a and the reception period b shown in FIG. The PLL frequency synthesizer 224 is connected to the buffer amplifier 223 at the burst timing of the slot, and is connected to the resistor 250 at other non-burst timings. In this case, the resistor 250 is set to an impedance (A ′ in FIG. 4) that is substantially equal to the input impedance A of the amplifier 223 at the burst timing when transmission / reception is executed.

Others are the same as those in FIG. 5, and therefore the description thereof is omitted here. Next, the operation of the embodiment configured as described above will be described. Now, in the call mode of the digital wireless terminal device shown in FIG.
When a call signal is input via the receiver unit 220 of the high frequency unit 200, a voice is output from the receiver speaker 18 via the modem 13, the TDMA 14, the speech codec 15 and the PCM 16, while the microphone 19 on the transmitter side is output. When a call signal is input from PCM16, speech codec 15, TDMA14, modem 1
3, the antenna 10 via the transmitter 230 of the high frequency unit 12
Output from 0 to the other subscriber.

In this case, the burst timing of transmission / reception in such a communication mode is 4 as shown in FIG.
As described above, the first slot of the transmission period a and the reception period b prepared for each slot is used, and the other 3 slots (total 6 slots) are non-bursts in which transmission / reception is not performed. In response to a control command from the control unit 20, the changeover switch 240 shown in FIG. 2 performs a changeover operation and is synchronized with the burst timing of the first slot used for transmission / reception in the transmission period a and the reception period b shown in FIG. Then, the PLL frequency synthesizer 224 is connected to the buffer amplifier 223 side, and the PLL frequency synthesizer 224 is connected to the resistor 250 at other non-burst timings.

As a result, the input impedance of the PLL frequency synthesizer 224 and the buffer amplifier 223 is A shown in FIG. 4 at the burst timing when transmission / reception is executed in the first slot of the transmission period a and the reception period b. In addition, at the non-burst timing other than this, since the resistor 250 is connected, the load impedance to the PLL frequency synthesizer 224 is
The input impedance A becomes substantially equal to the input impedance A at the burst timing, the load fluctuation on the PLL frequency synthesizer 224 is significantly reduced, stable operation is obtained, and its characteristics are improved. By this operation, the sleep control of the peripheral circuit of the PLL frequency synthesizer 224 becomes possible, and the power saving can be realized.

The present invention is not limited to the above-mentioned embodiments, and can be carried out by appropriately modifying it within the scope of the invention.
For example, although the resistor is used as the impedance element in the above-described embodiments, an impedance element other than the resistor may be used.

[0026]

As described above, according to the present invention, due to the switching operation of the switching means which is switched at a predetermined burst timing, at the non-burst timing, a value substantially equal to the input impedance of the PLL frequency synthesizer at the burst timing is obtained. Since the impedance element set to 1 is selected, the input impedance of the PLL frequency synthesizer can be set to a state substantially equal to the input impedance at the burst timing when signal transmission / reception is always executed. As a result, load fluctuations on the PLL frequency synthesizer can be significantly reduced, stable operation can be obtained, and its characteristics can be improved.
The sleep control of the peripheral circuit of the LL frequency synthesizer 224 becomes possible, and the power saving can be realized.

[Brief description of drawings]

FIG. 1 is a diagram showing a schematic configuration of a time division multiplexing digital wireless terminal device used in an embodiment of the present invention.

FIG. 2 is a diagram showing a schematic configuration of a high frequency unit used in one embodiment.

FIG. 3 is a diagram for explaining burst timing according to an embodiment.

FIG. 4 is a diagram for explaining variations in input impedance of a PLL frequency synthesizer.

FIG. 5 is a diagram showing a schematic configuration of a high frequency unit used in a conventional time division multiplexing digital wireless terminal device.

[Explanation of symbols]

 100 ... Antenna, 200 ... High frequency part, 211 ... Antenna switch part, 220 ... Reception part, 221 ... RF amplifier, 222 ... First stage mixer, 223 ... Buffer amplifier, 225 ... IF amplifier, 226, 2291 ... Bandpass filter (BPF), 227 ... Second stage mixer, 228 ... Local oscillator, 229 ... IF amplifier, 230 ... Transmitting section, 231 ... Bandpass filter (BPF), 232 ... Mixer, 233 ... Power amplifier, 224 ... PLL frequency synthesizer , 240 ... Changeover switch, 250 ... Resistor, 13 ... Modem, 14 ... TDMA, 15 ... Speech codec, 16 ... PCM, 17 ... Amplifier, 18 ... Receiver speaker, 19 ... Microphone, 20 ... Control section, 21 ... ROM , 22 ... RAM, 23 ... Recording / playback circuit, 24 ... Memory 25 ... display unit, 26 ... key input unit.

Claims (2)

[Claims] 1. A digital wireless terminal device having a high frequency unit for performing frequency conversion processing using a PLL frequency synthesizer on a signal transmitted / received at a predetermined burst timing, wherein the digital wireless terminal device is connected to the PLL frequency synthesizer at the predetermined burst timing. Switching means for switching operation, and non-burst timing other than the predetermined burst timing at which the impedance is set to be substantially equal to the input impedance of the PLL frequency synthesizer at the predetermined burst timing and the switching means transmits and receives the signal. And a impedance element connected to the PLL frequency synthesizer. 2. The digital wireless terminal device according to claim 1, wherein the impedance element comprises a resistor.