JPH07221567A - Semiconductor integrated circuit and capacitance value setting circuit - Google Patents

Abstract

PURPOSE:To attain multipurpose setting of capacitance values for setting a circuit characteristic by providing a signal designating a desired capacitance value externally. CONSTITUTION:A selection circuit 21 provides an output of H or L level selection signals S1 to Sm based on capacitance value selection designation signals SC1 to SCn obtained from capacitance value designation terminals P1-Pn. Each analog switch ASi is turned on/off based on a selection signal Si at its control input section C. That is, the switch is turned on when the signal Si is at an H level to connect a terminal N1 and a capacitor Ci corresponding thereto and the switch is turned off when the signal Si is at an L level to disconnect the terminal N1 and the capacitor Ci corresponding thereto. Thus, only the capacitor Ci in series with the switch Si in the on-state among switches AS1 to ASm is valid and the combined capacitance of the valid capacitors Ci is a capacitance value of the capacitors for circuit characteristic setting between the terminals N1 and N2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit in which circuit characteristics change based on a capacitance value of a circuit characteristic setting capacitor such as an operational amplifier, and a capacitance value setting circuit which can be incorporated in a semiconductor integrated circuit such as an operational amplifier. .

[0002]

2. Description of the Related Art FIG. 8 is a circuit diagram showing the internal structure of a conventional operational amplifier. As shown in the figure, the operational amplifier has a differential amplifier circuit 5 and a power amplifier circuit 6 inside, and has an input terminal 1, an input terminal 2 and a bias input terminal 3 as external signal input terminals for outputting an external signal. The output terminal 4 is provided as a terminal.

The differential amplifier circuit 5 includes PMOS transistors 11, 12 and 15 and NMOS transistors 13 and 14.
Composed of. Input terminals 1 and 2 are connected to the gates (input portions) of the PMOS transistor 11 and the PMOS transistor 12, respectively, which form a differential pair, and the PMO
The sources of the S transistors 11 and 12 are connected to the power supply Vcc via the PMOS transistor 15. Also PM
The gate of the OS transistor 15 is connected to the bias input terminal 3.

On the other hand, the PMOS transistor 11 is grounded via the common gate / drain NMOS transistor 13, and the PMOS transistor 12 is grounded via the NMOS transistor 14. The gates of the NMOS transistors 13 and 14 are commonly connected to form a current mirror circuit. And PMOS
A node N5 between the drains of the transistor 12 and the NMOS transistor 14 serves as an output section of the differential amplifier circuit 5.

In the differential amplifier circuit 5 having such a configuration, the PMOS transistors 15 and 16 are turned on and activated by inputting a predetermined bias voltage from the bias input terminal 3. When activated, a potential change appears at the node N5, which is the output section, based on the potential difference obtained from the input terminal 1 and the input terminal 2.

The node N5 of the differential amplifier circuit 5 is connected to one electrode of the capacitor C0 via the NMOS transistor 18. The gate of the NMOS transistor 18 is the power supply V
It is connected to cc and is always on.

Further, a PMOS transistor 16 and an NMOS transistor 17 connected in series are inserted between the power source Vcc and the ground, and the PMOS transistor 16 and the NMOS transistor 17 constitute a power amplifier circuit 6.

The drain of the PMOS transistor 16, N
The other electrode of the capacitor C0 is connected to the node N6 between the drains of the MOS transistors 17, and is also connected to the output terminal 4.

The operational amplifier having such a configuration outputs from the output terminal 4 an output signal obtained by amplifying the potential difference between the signals obtained from the input terminal 1 and the input terminal 2.

At this time, the capacitor C0 is used for phase compensation of the operational amplifier, and the circuit value of the operational amplifier such as phase margin, speed (slew rate) and unity gain frequency is determined by the capacitance value of the capacitor C0. Also,
The on-resistance value of the NMOS transistor 18 also contributes to the phase margin.

[0011]

The conventional semiconductor integrated circuit such as an operational amplifier having a built-in phase compensation capacitor is constructed as described above, and the capacitance value of the built-in capacitor C0 is fixed. , Slew rate,
There is a problem that the circuit characteristics of the operational amplifier such as the unity gain frequency are fixed.

Further, it is difficult in the manufacturing process to accurately set the capacitance value of the built-in capacitor, and the phase margin may be insufficient, or the slew rate and frequency characteristics may not meet the target performance. There is a problem that the circuit characteristics as designed cannot be obtained.

The present invention has been made to solve the above problems, and an object of the present invention is to obtain a semiconductor integrated circuit which can realize various circuit characteristics and more preferably can achieve desired circuit characteristics with high accuracy. .

[0014]

According to a first aspect of the present invention, there is provided a semiconductor integrated circuit comprising: an input terminal; an output terminal; and at least one of which is connected to the input terminal.
A differential amplifier circuit having an input section and an output section for outputting a signal obtained by amplifying the potential difference obtained from the first and second input sections from the output section, and based on the signal obtained from the output section. A circuit for outputting an output signal from the output terminal, which is interposed between at least one capacitance value indicating terminal for receiving a capacitance value indicating signal, and the output terminal and the output section of the differential amplifier circuit, A circuit characteristic setting capacitor that determines the circuit characteristic of the semiconductor integrated circuit based on the capacitance value, and a capacitance value of the circuit characteristic setting capacitor that is connected to the at least one capacitance value instruction terminal and that is based on the capacitance value instruction signal. And a capacitance value setting means for setting.

Preferably, as in the semiconductor integrated circuit according to the second aspect, the circuit characteristic setting capacitors are composed of first to m-th (m ≧ 2) circuit characteristic setting partial capacitors which are respectively connected in parallel. The capacitance value setting means selectively activates the first to mth circuit characteristic setting partial capacitances based on the capacitance value instruction signal, and combines the effective circuit characteristic setting partial capacitances. The value may be set as the capacitance value of the circuit characteristic setting capacitance.

More preferably, as in the semiconductor integrated circuit according to the third aspect, the capacitance value indicating signal is the first to nth.
(N ≧ 1) capacitance value selection instruction signal, wherein the at least one capacitance value instruction terminal receives first to nth capacitance value selection instruction signals, respectively. The number of the first to nth capacitance value selection instruction signals and the first to mth circuit characteristic setting partial capacitances is m> n, and the capacitance value setting means ,
Based on the first to nth capacitance value selection instruction signals,
Selection signal output means for outputting an mth selection signal, each of the first to mth circuit characteristic setting partial capacitors and the first capacitance
~ Is provided corresponding to the m-th selection signal, each of the first
A first to an mth switching means for activating / inactivating the corresponding circuit characteristic setting partial capacitances among the first to mth circuit characteristic setting partial capacitances based on the mth selection signal. Good.

More preferably, as in the semiconductor integrated circuit according to claim 4, the semiconductor integrated circuit further has a circuit characteristic setting resistor therein, and the circuit characteristic changes based on the resistance value of the circuit characteristic setting resistor. The first to mth switching means are respectively connected in series in correspondence with the first to mth circuit characteristic setting partial capacitors, respectively, and the first to mth selections are made. Each of the first to m-th transistors that receives a signal to each control electrode,
Each of the first to mth transistors is turned on / off to control the validity / invalidity of the corresponding circuit characteristic setting partial capacitance among the first to mth circuit characteristic setting partial capacitances. The ON-state transistor among the m-th transistors may function as the circuit characteristic setting resistor, and the ON resistance value thereof may be the resistance value of the circuit characteristic setting resistor.

According to a fifth aspect of the present invention, a semiconductor integrated circuit has first and second terminals, at least one capacitance value indicating terminal for receiving a capacitance value indicating signal, and one electrode at the first terminal. The capacitance value of the setting capacitance is set on the basis of the capacitance value indication signal, which is connected to the setting capacitance having the other electrode connected to the second terminal and the at least one capacitance value indication terminal. And a capacitance value setting means.

[0019]

The capacitance value setting means in the semiconductor integrated circuit according to the first aspect of the present invention sets the capacitance value of the circuit characteristic setting capacitance based on the capacitance value instruction signal, so that a desired capacitance value is indicated from the outside. It is possible to set various capacitance values of the circuit characteristic setting capacitance of the semiconductor integrated circuit by giving the capacitance value instruction signal.

Further, the capacitance value setting means in the semiconductor integrated circuit according to claim 2 of the present invention selectively activates the first to mth circuit characteristic setting partial capacitances based on the capacitance value instruction signal, Since the combined capacitance value of the circuit characteristic setting partial capacitors in the valid state is set as the capacitance value of the circuit characteristic setting capacitor, each of the capacitance values of the first to mth circuit characteristic setting partial capacitors is designed. Even if the value deviates from the stage, the capacitance value closest to the design value can be obtained by appropriately selecting the circuit characteristic setting partial capacitance to be validated.

According to a third aspect of the present invention, in the semiconductor integrated circuit, a selection signal for outputting the first to mth (m> n) selection signals based on the first to nth capacitance value selection instruction signals. Output means, each provided corresponding to the first to mth circuit characteristic setting partial capacitors and the first to mth selection signals,
First to mth switching means for respectively activating / inactivating corresponding circuit characteristic setting partial capacitances among the first to mth circuit characteristic setting partial capacitances based on the first to mth selection signals, respectively. Therefore, by setting the number n of capacitance value indicating terminals smaller than the number m of circuit characteristic setting capacitors, it is possible to set valid / invalid of m circuit characteristic setting capacitors.

Further, the first to m-th transistors, which are the first to m-th switching means in the semiconductor integrated circuit according to the fourth aspect of the present invention, are turned on / off respectively, so that the first to m-th transistors are turned on / off. Of the partial capacitors for setting circuit characteristics described above is controlled to be valid / invalid, and the on-state transistor of the first to mth transistors functions as a resistor for setting circuit characteristics. The value becomes the resistance value of the circuit characteristic setting resistor.
Therefore, the first to m-th transistors are
The effective / ineffective control of the partial capacitance for circuit characteristic setting and the circuit characteristic setting function are combined.

According to a fifth aspect of the present invention, the capacitance value setting means of the capacitance value setting circuit, based on the capacitance value instruction signal,
In order to set the capacitance value of the setting capacitance, it is possible to variously set the capacitance value of the setting capacitance by externally supplying a capacitance value instruction signal for instructing a desired capacitance value.

[0024]

【Example】

<First Embodiment> FIG. 1 is a circuit diagram showing an internal structure of a class A operational amplifier according to a first embodiment of the present invention. As shown in the figure, an operational amplifier, which is an analog IC integrated into one chip, has a differential amplifier circuit 5, a power amplifier circuit 6, and a capacitance value setting circuit 20 inside, and an input terminal 1 as an external signal input terminal. , An input terminal 2, a bias input terminal 3, capacitance value indicating terminals P1 to Pn (n ≧ 1), and an output terminal 4 as an external signal output terminal.

The differential amplifier circuit 5 includes PMOS transistors 11, 12 and 15 and NMOS transistors 13 and 14.
Composed of. Input terminals 1 and 2 are connected to the gates (input portions) of the PMOS transistor 11 and the PMOS transistor 12, respectively, which form a differential pair, and the PMO
The sources of the S transistors 11 and 12 are connected to the power supply Vcc via the PMOS transistor 15. Also PM
The gate of the OS transistor 15 is connected to the bias input terminal 3.

On the other hand, the PMOS transistor 11 is grounded via the common gate / drain NMOS transistor 13, and the PMOS transistor 12 is grounded via the NMOS transistor 14. The gates of the NMOS transistors 13 and 14 are commonly connected to form a current mirror circuit. And PMOS
A node N5 between the drains of the transistor 12 and the NMOS transistor 14 serves as an output section of the differential amplifier circuit 5.

In the differential amplifier circuit 5 having such a configuration, the PMOS transistors 15 and 16 are turned on and activated by inputting a predetermined bias voltage from the bias input terminal 3. When activated, a potential change appears at the node N5, which is the output section, based on the potential difference obtained from the input terminal 1 and the input terminal 2.

A PMOS transistor 16 and an NMOS transistor 17 connected in series are inserted between the power source Vcc and ground, and the PMOS transistor 16 and the NMOS transistor 17 constitute a power amplifier circuit 6.

The node N5 of the differential amplifier circuit 5 is connected via the NMOS transistor 18 to the terminal N1 of the capacitance value setting circuit 20.
Connected to. The gate of the NMOS transistor 18 is connected to the power supply Vcc and is always set to the ON state.

On the other hand, a node N6 between the drain of the PMOS transistor 16 and the drain of the NMOS transistor 17 of the power amplifier circuit 6 is a terminal N2 of the capacitance value setting circuit 20.
And the output terminal 4.

When the first embodiment is compared with the conventional operational amplifier shown in FIG. 8, the capacitance value setting circuit 20 is originally
By connecting the terminal N1 and the terminal N2 to the circuit portion to which the one electrode and the other electrode of the circuit characteristic setting capacitor C0 are respectively connected, the capacitor C0
It is installed in place of. That is, the capacitance value setting circuit 20 is inserted between the output section of the differential amplifier circuit 5 and the output terminal 4.

The capacitance value setting circuit 20 is connected to the capacitance value indicating terminals P1 to Pn which receive the capacitance value selecting instruction signals SC1 to SCn, respectively, and the capacitance value selecting instruction signals SC1 to Sn.
Based on the instruction content of Cn, the capacitance value of the circuit characteristic setting capacitor inserted between the terminals N1 and N2 is variously set.

<Capacity Value Setting Circuit> FIG. 2 is a circuit diagram showing an internal configuration of the capacity value setting circuit 20. As shown in the figure, the capacitance value setting circuit 20 includes a selection circuit 21 and a capacitance built-in circuit 22.

The selection circuit 21 includes capacitance value indicating terminals P1 to P1.
capacitance value selection instruction signals SC1 to S respectively obtained from n
Based on Cn, selection signals S1 to Sm (m ≧ 2 and m> n) of “H” or “L” level are output.

On the other hand, the capacity built-in circuit 22 is composed of m analog switches AS1 to ASm and m capacitors C1 to Cm for setting circuit characteristics. Each analog switch ASi (1 ≦ i ≦ m) receives a selection signal Si corresponding to each control input section C, an input section I is commonly connected to a terminal N1, and an output section O is one electrode of a corresponding capacitor Ci. Connected to. The other electrodes of the capacitors C1 to Cm are commonly connected to the terminal N2.

Each analog switch ASi is turned on / off based on a selection signal Si received by its control input section C.
That is, when the corresponding selection signal Si is "H", it is turned on, the terminal N1 and the corresponding capacitor Ci are electrically connected, and when the corresponding selection signal Si is "L", it is turned off and the terminal N1 is connected. The corresponding capacitor Ci is electrically cut off.

Therefore, the analog switches AS1 to A
Of Sm, only the capacitor Ci connected in series to the analog switch ASi in the ON state is valid, and the combined capacitance value of the capacitors C in the valid state becomes the capacitance value of the circuit characteristic setting capacitor between the terminals N1 and N2.

The on resistance values of the analog switches AS1 to ASm are set to a level that can be ignored with respect to the on resistance value of the NMOS transistor 18.

FIG. 3 is a circuit diagram showing the internal structure of the selection circuit 21. As shown in the figure, the selection circuit 21 includes five inverters G1 to G5 and four AND gates G6 to G5.
9 and 9. The selection circuit 21 shown in FIG.
Shows the configuration when n = 2 and m = 4.

The input of the inverter G1 is connected to the capacitance value indicating terminal P1, and the output of the inverter G1 is connected to the inverter G2.
Of the inverter G is connected to the capacitance value indicating terminal P2.
3 is connected, the output of the inverter G3 is connected to the input of the inverter G4, and the inverter G5 is connected to the ground level.
Input is connected.

The output of the inverter G1 is connected to the inputs of the AND gates G8 and G9, the output of the inverter G2 is connected to the inputs of the AND gates G6 and G7, and the output of the inverter G3 is connected to the inputs of the AND gates G6 and G9. The output of the inverter G4 is connected and the AND gate G7 is connected.
And G8 inputs.

The selection circuit 21 having such a configuration sets only one selection signal among the selection signals S1 to S4 to "H" based on "H" and "L" of the capacitance value selection instruction signals SC1 and SC2. And all other selection signals are "L"
The decoding function set to is realized.

Therefore, of the capacitors C1 to C4, the analog switch AS which receives the selection signal of "H".
Only one capacitor Ci connected in series with i can be set to the valid state. Although the selection circuit 21 that outputs the selection signals S1 to Sm for instructing selection of one capacitor C is shown in the example of FIG. 3, the selection signals S1 to Sm for changing the logical configuration and selecting a plurality of capacitors C are shown. Of course, a configuration for outputting is also possible.

As described above, the selection circuit 21 can output m selection signals S1 to Sm that are larger than the number n of capacitance value indicating terminals.

Hereinafter, with reference to FIG. 2, the capacitance value setting circuit 2
The operation of 0 will be described. The selection circuit 21 outputs m (> n) "H" or "L" selection signals S1 to Sm based on the capacitance value selection instruction signals SC1 to SCn, and selectively selects the analog switches AS1 to ASm. Turn on and off.

As a result, the analog switches AS1 to AS
Among m, the combined capacitance value of the capacitor Ci connected in series to the analog switch ASi in the on state is the terminals N1 and N.
It is set as a capacitance value for setting the circuit characteristic between the two.

Returning to FIG. 1, when an input signal desired to be amplified is input from the input terminal 1 that is a negative input and a reference signal is input from the input terminal 2 that is a positive input to the operational amplifier having the above-described configuration, two input signals are obtained. The potential of the node N5 on the drain side of the NMOS transistor 14 varies according to the potential difference between the signals. On the other hand, a bias voltage is applied from the bias input terminal 3 to determine the current flowing from the PMOS transistor 15 to the differential stage (PMOS transistors 11 and 12). The bias voltage is also applied to the gate of the PMOS transistor 16, so that the output current flowing through the power amplifier circuit 6 is also determined.

The signal obtained from the node N5 which is the output section of the differential amplifier circuit 5 is further amplified by the power amplifier circuit 6 and output from the output terminal 4 as an output signal.

At this time, the capacitance value for setting the circuit characteristic set by the capacitance value setting circuit 20 and the NMOS transistor 18 are set.
The circuit resistance of the operational amplifier such as the phase margin, speed (slew rate), and unity gain frequency is determined by the ON resistance value of. Hereinafter, this point will be described in detail.

For example, assuming that the capacitance value of the circuit characteristic setting capacitor set by the capacitance value setting circuit 20 is C and the output current flowing through the output terminal 4 is I0, the slew rate SR of the operational amplifier is as follows. decide.

SR = I0 / C (I) Therefore, when I0 = 40 μA and C = 5 pF, the slew rate SR is 8 V / μS, and I0 = 40.
When μA and C = 4 pF, the slew rate SR is 1
It becomes 0 V / μS.

The unity gain frequency is ft, PM
When the transconductances of the OS transistors 11 and 12 are both gm, the following relational expression holds.

2πft = gm / C (II) Therefore, when gm = 157 μA / V and C = 5 pF, the unity gain frequency f becomes 5 MHz, and gm =
When C = 4 pF at 157 μA / V, the unity gain frequency f is 6.25 MHz.

When the on-resistance of the NMOS transistor 18 is R and the transconductance of the NMOS transistor 17 is gm1, the following relational expression holds for the phase margin φ. In addition, a is a constant.

Φ = a · | 1 / ((R−1 / gm1) · C) | ... (III) Therefore, by changing the capacitance value C of the circuit characteristic setting capacitor and the on-resistance R of the NMOS transistor 18, The phase compensation of the operational amplifier can be performed by changing the phase margin φ.

As described above, the operational amplifier of the first embodiment is
Since the capacitance value of the internal circuit characteristic setting capacitor that determines the circuit characteristic of the operational amplifier can be variously set based on the capacitance value selection instruction signals SC1 to SCn obtained from the outside, a desired capacitance value can be set according to the application. Circuit characteristics can be obtained.

Further, even if the individual capacitance values of the capacitors C1 to Cm in the capacitance built-in circuit 22 of FIG. 2 deviate from the design values to some extent, by selecting the effective capacitors C1 to Cm as appropriate, Since the closest capacitance value (combined capacitance value) can be obtained, the capacitance value of the circuit characteristic setting capacitor can be accurately set, and the operational amplifier can obtain accurate circuit characteristics.

Further, the selection circuit 2 is provided in the capacitance value setting circuit 20.
By providing 1, the valid / invalid setting of the m capacitors C1 to Cm, which is larger than the number n of capacitance value indicating terminals, can be performed, so that the number of capacitance value indicating terminals that are external terminals can be minimized. .

The capacitance value setting circuit 20, as described above,
Based on the capacitance value selection instruction signals SC1 to SCn obtained from the outside, the capacitance value of the capacitor formed between the terminals N1 and N2 can be variously changed. Therefore,
If the capacitance value setting circuit 20 is built in a semiconductor integrated circuit that requires various capacitance values in order to obtain various circuit characteristics like the operational amplifier having the configuration shown in FIG. By giving a signal, various circuit characteristics can be set.

<Application to Comparator> In the first embodiment shown in FIG. 1, the example of the operational amplifier including the capacitance value setting circuit 20 is shown. However, the capacitance value is set in a semiconductor integrated circuit other than the operational amplifier. Naturally, it is conceivable to incorporate a circuit.

4 and 5 are circuit diagrams showing the first and second comparators having the capacitance value setting circuit 20 built therein. FIG. 4 shows a class A operational amplifier type comparator.
Shows a class AB operational amplifier type comparator.

As shown in FIG. 4, the first comparator is
Like the operational amplifier shown in FIG. 1, the differential amplifier circuit 5 is internally provided.
A power amplifier circuit 6 and a capacitance value setting circuit 20, and an input terminal 1, an input terminal 2, a bias input terminal 3, and capacitance value indicating terminals P1 to Pn (n ≧ 1) as external signal input terminals, The output terminal 4 is provided as an external signal output terminal.

The internal configurations of the differential amplifier circuit 5 and the power amplifier circuit 6 are the same as those of the first embodiment shown in FIG. The terminal N1 of the capacitance value setting circuit 20 is connected to the node N5 which is the output section of the differential amplifier circuit 5, and the terminal N1
2 is connected to the node N6 (output terminal 4) of the power amplifier circuit 6.

Similar to the first embodiment, the capacitance value setting circuit 20 is connected to the capacitance value instruction terminals P1 to Pn which receive the capacitance value selection instruction signals SC1 to SCn, respectively, and the instruction contents of the capacitance value selection instruction signals SC1 to SCn. Based on the terminal N1,
The capacitance value of the circuit characteristic setting capacitor inserted between the terminals N2 is set.

The first comparator having such a configuration is
By inputting a predetermined bias voltage from the bias input terminal 3, the PMOS transistors 15 and 16 are turned on and the differential amplifier circuit 5 is activated. Differential amplifier circuit 5
When activated, compares the potentials of the signals obtained from the input terminal 1 and the input terminal 2 and outputs the comparison result from the node N5 which is the output section. Then, the power amplifier circuit 6 amplifies the signal obtained from the node N5 and outputs the output signal from the output terminal 4.

At this time, depending on the capacitance value of the circuit characteristic setting capacitor set by the capacitance value setting circuit 20, comparators such as phase margin, speed (slew rate), unity gain frequency, etc. are provided as in the operational amplifier of the first embodiment. Circuit characteristics are determined.

The slew rate SR and the unity gain frequency ft are determined by the equations (I) and (II) described in the first embodiment. Also, the NMOS transistor 1
If the transconductance of 7 is gm1, the following relational expression holds for the phase margin φ. However, b is a constant.

.Phi. = B.multidot..vertline.gm1 / C.vertline. (IV) Therefore, by changing the capacitance value C of the circuit characteristic setting capacitor and changing the phase margin .phi., The phase compensation of the first comparator can be performed.

Further, even when the individual set capacitance values of the capacitors C1 to Cm in the capacitance built-in circuit 22 (see FIG. 2) in the capacitance value setting circuit 20 deviate from the design values to some extent, the capacitors C1 to Cm to be activated are selected. By appropriately selecting, the capacitance value (combined capacitance value) closest to the design value can be obtained, so that the capacitance value of the circuit characteristic setting capacitor can be set accurately, and the first comparator Good circuit characteristics can be obtained.

As described above, the capacitance value setting circuit 20 is built in the first comparator, and the capacitance value selection instruction signal SC1
By setting the capacitance value of the circuit characteristic setting capacitor in the capacitance value setting circuit 20 by ~ SCn, it is possible to determine the circuit characteristic of the first comparator variously and with high accuracy, as in the first embodiment. .

Further, like the second comparator shown in FIG. 5, the differential amplifier circuit 5, the level shift circuit 7,
It has a power amplifier circuit 6 and a capacitance value setting circuit 20, and has an input terminal 1, an input terminal 2, a bias input terminal 3, and capacitance value indicating terminals P1 to Pn (n ≧ 1) as external signal input terminals. The output terminal 4 may be provided as an output terminal.

The internal configurations of the differential amplifier circuit 5 and the power amplifier circuit 6 are the same as those of the first comparator example shown in FIG. 4, and the terminal N1 of the capacitance value setting circuit 20 is connected to the differential amplifier circuit 5. Connected to the node N5 which is the output section of the
Is connected to the node N6 (output terminal 4) of the power amplifier circuit 6.

The level shift circuit 7 is composed of a PMOS transistor 31 and a PMOS transistor 32,
The source of the PMOS transistor 31 is connected to the power supply Vcc, the gate is connected to the bias input terminal 3, the drain is connected to the source of the PMOS transistor 32, and the terminal N1 of the capacitance value setting circuit 20. P
The gate of the MOS transistor 32 is connected to the node N5 of the differential amplifier circuit 5, and the drain is grounded.

Like the first comparator, the capacitance value setting circuit 20 is connected to the capacitance value instruction terminals P1 to Pn that receive the capacitance value selection instruction signals SC1 to SCn, respectively, and the instruction contents of the capacitance value selection instruction signals SC1 to SCn. Based on, the capacitance value of the circuit characteristic setting capacitor inserted between the terminals N1 and N2 is set.

The second comparator having such a configuration is
By inputting a predetermined bias voltage from the bias input terminal 3, the PMOS transistors 15 and 16 are turned on and the differential amplifier circuit 5 is activated. Differential amplifier circuit 5
When activated, compares the potentials of the signals obtained from the input terminal 1 and the input terminal 2 and outputs the comparison result from the node N5 which is the output section. Then, the level shift circuit 7 level-shifts the signal obtained from the node N5, and the power amplification circuit 6 amplifies the level-shifted signal and outputs it as an output signal from the output terminal 4.

At this time, depending on the capacitance value of the circuit characteristic setting capacitor set by the capacitance value setting circuit 20, the circuit characteristics of the comparator such as phase compensation, speed (slew rate) and unity gain frequency are similar to those of the first comparator. Is determined, and the same effect as the first comparator is obtained.

As described above, the capacitance value setting circuit 20 is built in the second comparator, and the capacitance value selection instruction signal SC1
By setting the capacitance value of the circuit characteristic setting capacitor in the capacitance value setting circuit 20 by ~ SCn, it is possible to determine the circuit characteristic of the second comparator variously and with high accuracy.

<Second Embodiment> FIG. 6 shows a second embodiment of the present invention.
3 is a circuit diagram showing the internal structure of an operational amplifier that is an example of FIG. As shown in the figure, an analog IC integrated into one chip
The operational amplifier, which has a differential amplifier circuit 5, a power amplifier circuit 6, and a capacitance value setting circuit 23, has an input terminal 1, an input terminal 2, a bias input terminal 3, and a capacitance value instruction terminal as external signal input terminals. P1 to Pn (n ≧ 1) are provided, and an output terminal 4 is provided as an external signal output terminal.

The capacitance value setting circuit 23 is connected to a node N5 which is an output section of the differential amplifier circuit 5 via a terminal N3,
It is connected to the output terminal 4 via the terminal N4. Further, the capacitance value setting circuit 23 uses the capacitance value selection instruction signals SC1 to SC.
n is respectively connected to the capacitance value indicating terminals P1 to Pn, and the capacitance value of the circuit characteristic setting capacitor inserted between the terminals N3 and N4 is set based on the instruction contents of the capacitance value selecting instruction signals SC1 to SCn. .

The differential amplifier circuit 5 and the power amplifier circuit 6
The internal configuration of is the same as that of the operational amplifier of the first embodiment shown in FIG. The capacitance value setting circuit 23 different from that of the first embodiment will be described below.

<Capacity Value Setting Circuit> FIG. 7 is a circuit diagram showing the internal structure of the capacity value setting circuit 23. As shown in the figure, the capacitance value setting circuit 23 includes a selection circuit 21 and a capacitance built-in circuit 25.

The selection circuit 21 has an internal structure similar to that of the first embodiment illustrated in FIG. 3, and has capacitance value indicating terminals P1 to P1.
capacitance value selection instruction signals SC1 to S respectively obtained from n
Based on Cn, the selection signals S1 to Sm (m ≧ 2 and m> n), one of which is set to “H” and the other to “L”, are output.

On the other hand, the capacity built-in circuit 25 is composed of m NMOs.
It is composed of S transistors Q1 to Qm and m capacitors C1 to Cm for setting circuit characteristics. Each transistor Qi (1 ≦ i ≦ m) receives a corresponding selection signal Si at its gate, has its drain commonly connected to the terminal N3, and has its source connected to one electrode of the corresponding capacitor Ci. The other electrodes of the capacitors C1 to Cm are commonly connected to the terminal N4.
Connected to.

Each transistor Qi is turned on / off based on a selection signal Si received by its gate. That is, when the corresponding selection signal Si is "H", it is turned on, the terminal N3 and the corresponding capacitor Ci are electrically connected, and when the corresponding selection signal Si is "L", it is turned off and the terminal N3 is connected. The corresponding capacitor Ci is electrically cut off.

Therefore, among the transistors Q1 to Qm, only the capacitor Ci connected in series with the transistor Qi in the ON state is valid, and the combined capacitance value of the capacitors C in the valid state is the circuit characteristic setting capacitor between the terminals N3 and N4. It becomes the capacity value of. Then, the ON resistance value of the transistor Qi in the ON state is the ON resistance value for phase compensation (see FIG.
Corresponding to the ON resistance value of the NMOS transistor 18).

An input signal desired to be amplified is input from the input terminal 1 which is a negative input to the operational amplifier having such a configuration,
When a reference signal is input from the input terminal 2 which is a positive input, 2
The potential of the node N5 on the drain side of the NMOS transistor 14 varies according to the potential difference between the two signals. On the other hand, a bias voltage is applied from the bias input terminal 3 to determine the current flowing from the PMOS transistor 15 to the differential stage (PMOS transistors 11 and 12). The bias voltage is also applied to the gate of the PMOS transistor 16, so that the output current flowing through the power amplifier circuit 6 is also determined.

The signal obtained from the node N5 which is the output of the differential amplifier circuit 5 is further amplified by the power amplifier circuit 6 and output from the output terminal 4 as an output signal.

At this time, the operational amplifier such as phase margin, speed (slew rate), unity gain frequency, etc. is determined by the capacitance value for setting the circuit characteristic set by the capacitance value setting circuit 23 and the ON resistance value of the NMOS transistor Qi in the ON state. Circuit characteristics are determined.

As described above, the operational amplifier of the second embodiment is
Since the capacitance value of the internal circuit characteristic setting capacitor that determines the circuit characteristic of the operational amplifier can be variously set based on the capacitance value selection instruction signals SC1 to SCn obtained from the outside, a desired capacitance value can be set according to the application. Circuit characteristics can be obtained.

Further, even when the individual set capacitance values of the capacitors C1 to Cm in the capacitance built-in circuit 25 of FIG. 7 deviate from the design values to some extent, the design values can be selected by appropriately selecting the effective capacitors C1 to Cm. Since it is possible to obtain the capacitance value closest to, the capacitance value of the circuit characteristic setting capacitor can be accurately set, and the operational amplifier can obtain the circuit characteristic with high accuracy.

In addition, the selection circuit 2 is provided in the capacitance value setting circuit 23.
By providing 1, m which is larger than the number n of capacitance value indicating terminals
Since the individual capacitors C1 to Cm can be set to be valid / invalid, the number of capacitance value indicating terminals that are external terminals can be suppressed to a necessary minimum.

In addition, among the transistors Q1 to Qm used as the switching means, the ON resistance value of the transistor Qi in the ON state also serves as the resistance value for phase compensation, so that the comparison with the first embodiment is made. In this case, it is not necessary to separately provide a transistor for phase compensation (corresponding to the NMOS transistor 18 in FIG. 1), and it is possible to achieve integration by effectively using the element.

The capacitance value setting circuit 23, as described above,
The capacitance value of the capacitor formed between the terminals N3 and N4 can be variously changed based on the capacitance value selection instruction signals SC1 to SCn obtained from the outside. Therefore,
If the capacitance value setting circuit 23 is built in a semiconductor integrated circuit that desires various capacitance values in order to obtain various circuit characteristics like the operational amplifier having the configuration shown in FIG. 6, an external signal indicating the capacitance value can be obtained. By giving, it becomes possible to set various circuit characteristics.

<Application to Comparator> By replacing the capacitance value setting circuits 20 of the first and second comparators shown in FIGS. 4 and 5 with the capacitance value setting circuit 23, the capacitance value selection instruction signals SC1 to SC1. By setting the capacitance value of the circuit characteristic setting capacitor in the capacitance value setting circuit 23 by SCn, it is possible to determine the circuit characteristics of the first and second comparators in various ways and with high accuracy. However, in this case, the transistor Q1 in the capacitance built-in circuit 25
It is desirable to reduce the ON resistance of Qm to a negligible level.

<Others> In the first and second embodiments, examples of operational amplifiers and comparators having the capacitance value setting circuit 20 (23) are shown, but various other R
If the capacitance value setting circuit 20 is built-in by replacing the circuit characteristic setting capacitor in the semiconductor integrated circuit that desires various circuit characteristics such as a filter for which the C time constant is desired, by providing an external signal indicating the capacitance value, It is possible to obtain a semiconductor integrated circuit in which various circuit characteristics can be set.

The differential amplifier circuit 5 in the first and second embodiments has two input sections (PMOS transistor 1).
Although the gates 1 and 12 are connected to the input terminals 1 and 2 which are external input terminals, respectively, one of the two input sections may be configured to be supplied with a fixed voltage from the inside.

[0097]

The capacitance value setting means in the semiconductor integrated circuit according to the first aspect of the present invention sets the capacitance value of the circuit characteristic setting capacitance based on the capacitance value instruction signal.
By giving a capacitance value instruction signal for instructing a desired capacitance value from the outside, various capacitance values of the circuit characteristic setting capacitance can be set, and various circuit characteristics can be obtained according to the application of the semiconductor integrated circuit. .

Further, the capacitance value setting means in the semiconductor integrated circuit according to the second aspect of the present invention selectively selects the first to m-th (m ≧ 2) circuit characteristic setting partial capacitances based on the capacitance value instruction signal. Since the combined capacitance value of the circuit characteristic setting partial capacitors in the valid state is set as the capacitance value of the circuit characteristic setting capacitor, the individual capacitance values of the first to mth circuit characteristic setting partial capacitors are Even if the value deviates from the design value, by appropriately selecting the partial capacitor for circuit characteristic setting to be enabled, the capacitance value closest to the design value can be set to obtain a semiconductor integrated circuit with highly accurate circuit characteristics. You can

In addition, as in the semiconductor integrated circuit according to a third aspect of the present invention, the first to mth (m> n) selection signals are output based on the first to nth capacitance value selection instruction signals. Selection signal output means for providing each of the first to mth circuit characteristic setting partial capacitors and the first to mth selection signals, each of which is based on the first to mth selection signals. First to
Of the mth circuit characteristic setting partial capacitances, the corresponding circuit characteristic setting partial capacitances are enabled / disabled, respectively.
By providing the switching means of, the effective / ineffective setting of m circuit characteristic setting capacitors can be performed only by providing the capacitance value indicating terminal number n smaller than the circuit characteristic setting capacitance number m. The number n of certain capacitance value indicating terminals can be suppressed to the necessary minimum.

Further, as in the semiconductor integrated circuit according to the fourth aspect of the present invention, by turning on / off each of them, the corresponding circuit characteristic setting portion of the first to mth circuit characteristic setting partial capacitances. A first to a first transistor which controls whether the capacitance is valid or not, and which of the first to m-th transistors functions as a circuit characteristic setting resistor whose ON resistance value is the resistance value of the circuit characteristic setting resistor. Since the m-th transistor is provided, the first to m-th transistors have both effective / ineffective control of the first to m-th circuit characteristic setting partial capacitances and a circuit characteristic setting function, which enables effective use of the element. The degree of integration can be improved.

The capacitance value setting means of the capacitance value setting circuit according to a fifth aspect of the present invention is based on the capacitance value instruction signal,
In order to set the capacitance value of the setting capacitance, it is possible to variously set the capacitance value of the setting capacitance by externally supplying a capacitance value instruction signal for instructing a desired capacitance value.

Therefore, a circuit in which one electrode of the circuit characteristic setting capacitor is originally connected to a semiconductor integrated circuit which has a differential amplifier circuit and whose circuit characteristic changes depending on the capacitance value of the internal circuit characteristic setting capacitor. If the first terminal is connected to the portion and the second terminal is connected to the circuit portion to which the other electrode is connected, and the capacitance value setting circuit is built in the semiconductor integrated circuit by replacing it with the circuit characteristic setting capacitance. A semiconductor integrated circuit having various circuit characteristics according to the application can be obtained by externally supplying a capacitance value designating signal designating a desired capacitance value.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of an operational amplifier according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing an internal configuration of a capacitance value setting circuit of FIG.

FIG. 3 is a circuit diagram showing a configuration example of a selection circuit of FIG.

FIG. 4 is a circuit diagram showing a first configuration example when applied to the comparator of the first embodiment.

FIG. 5 is a circuit diagram showing a second configuration example when applied to the comparator of the first embodiment.

FIG. 6 is a circuit diagram showing a configuration of an operational amplifier according to a second embodiment of the present invention.

7 is a circuit diagram showing an internal configuration of the capacitance value setting circuit of FIG.

FIG. 8 is a circuit diagram showing a configuration of a conventional operational amplifier.

[Explanation of symbols]

 5 differential amplifier circuit 6 power amplifier circuit 20 capacity value setting circuit 21 selection circuit 22 capacity built-in circuit 23 capacity value setting circuit 25 capacity built-in circuit AS1 to ASm analog switches C1 to Cm capacitors Q1 to Qm NMOS transistors N1 to N4 terminals P1 to Pn capacitance value indication terminal

Claims (5)

[Claims] 1. An input terminal, an output terminal, and first and second input portions, at least one of which is connected to the input terminal, and an output portion, and a potential difference obtained from the first and second input portions. What is claimed is: 1. A semiconductor integrated circuit comprising: a differential amplifier circuit for outputting an amplified signal from said output section; and outputting an output signal from said output terminal based on a signal obtained from said output section, wherein at least 1 receives a capacitance value instruction signal. A capacitance value indicating terminal, a circuit characteristic setting capacitance that is interposed between the output terminal and the output section of the differential amplifier circuit, and determines the circuit characteristic of the semiconductor integrated circuit by the capacitance value thereof; A semiconductor integrated circuit comprising: a capacitance value setting means connected to at least one capacitance value instruction terminal and setting a capacitance value of the circuit characteristic setting capacitance based on the capacitance value instruction signal. 2. The circuit characteristic setting capacitance includes first to m-th (m ≧ 2) circuit characteristic setting partial capacitances, each of which is connected in parallel, and the capacitance value setting means includes the capacitance value. Based on the instruction signal,
2. The first to mth circuit characteristic setting partial capacitors are selectively validated, and the combined capacitance value of the circuit characteristic setting partial capacitors in the valid state is set as the capacitance value of the circuit characteristic setting capacitor. The semiconductor integrated circuit described. 3. The first to n-th (n
≧ 1), and the at least one capacitance value instruction terminal receives the first to nth capacitance value selection instruction signals from the first to nth capacitance value instruction terminals, respectively. Therefore, the relationship between the numbers of the first to nth capacitance value selection instruction signals and the first to mth circuit characteristic setting partial capacitances is m> n.
The capacitance value setting means is configured to output the first to nth capacitance value selection instruction signals based on the first to nth capacitance value selection instruction signals.
Selection signal output means for outputting an mth selection signal, each of which is provided corresponding to the first to mth circuit characteristic setting partial capacitors and the first to mth selection signals, and each of the selection signal output means First to mth switching means for activating / inactivating the corresponding circuit characteristic setting partial capacitances among the first to mth circuit characteristic setting partial capacitances, respectively, based on the first to mth selection signals. The semiconductor integrated circuit according to claim 2. 4. The semiconductor integrated circuit further has a circuit characteristic setting resistor therein, circuit characteristics change based on a resistance value of the circuit characteristic setting resistor, and the first to mth switching means are , Each said first
To m-th circuit characteristic setting partial capacitors, each of which is connected in series and includes first to m-th transistors that receive the first to m-th selection signals at their respective control electrodes, Each of the first to mth transistors is turned on / off to control the validity / invalidity of the corresponding circuit characteristic setting partial capacitance among the first to mth circuit characteristic setting partial capacitances. 4. The semiconductor integrated circuit according to claim 3, wherein among the first to m-th transistors, an on-state transistor functions as the circuit characteristic setting resistor, and the on resistance value becomes the resistance value of the circuit characteristic setting resistor. 5. A first and a second terminal, at least one capacitance value indication terminal for receiving a capacitance value indication signal, one electrode connected to the first terminal, and the other electrode connected to the second terminal. A capacitance value setting circuit comprising: a setting capacitance to be connected; and a capacitance value setting means that is connected to the at least one capacitance value instruction terminal and that sets a capacitance value of the setting capacitance based on the capacitance value instruction signal. .