JPH07220408A - Magnetic recording data reproduction device - Google Patents

Abstract

PURPOSE:To reduce read error by detecting and correcting an erroneous criterion pattern which can be judged by the three-value discrimination when reproducing data by obtaining an equalization waveform signal of PR-IV via an equalizer from magnetic disk where RLL code is magnetically recorded by NRZI modulation. CONSTITUTION:A comparator 1 for detecting +1 level of EQ output (equalization waveform signal PR) and a comparator 2 for detecting -1 level similarly are provided to properly correct an erroneous criterion pattern with a large possibility. Shift registers 100 and 200 consisting of DFF are provided at each output side of the comparator 2 and level criterion result at the past three continuous sampling points is stored for each rising of a clock CLK. When the contents are the erroneous criterion patterns, an erroneous criterion detection correction device 300 for detecting and correcting them is provided, thus correcting data output from shift registers 100 and 200 to an off circuit 17.

Description

Detailed Description of the Invention

[0001]

The present invention relates to RLL (Run Le).
NGZ (Non-Limited) code
The present invention relates to a magnetic recording data reproducing apparatus which reproduces data by equalizing a reproduction signal read from a magnetic disk magnetically recorded by Return to Zero Inverse modulation through a head and a head amplifier into an equalized waveform signal of PR-IV.

In the following drawings, the same reference numerals indicate the same or corresponding parts.

[0003]

2. Description of the Related Art FIG. 6 shows a general schematic construction of a PR-IV type magnetic recording data reproducing apparatus. That is, a reproduction signal HA obtained by a head and a head amplifier (not shown) from a magnetic disk (not shown) in which an RLL code (1,7 code, etc.) is magnetically recorded by NRZI modulation, has a constant amplitude by an automatic gain control amplifier AGC. Then, the equalizer EQ equalizes the waveform of the PR-IV equalized waveform signal. Also,
The clock signal 03 for data reproduction is generated by the clock generator 03 from the output signal of the amplifier AGC.
3-value discrimination from equalized waveform signal PR and clock signal CLK
The reproduced data DT1 is output by the data reproducer 01 (01A in the present invention), and this data DT1 is further converted by the decoder 02 into the original data DT2 before being encoded.

FIG. 7 shows a structure of a conventional three-value discrimination / data regenerator 01, and FIG. 8 shows operation waveforms of FIG. Referring to FIGS. 7 and 8, the output of the equalizer EQ (equalized waveform signal PR) is a threshold level (also referred to as a threshold value).
If larger than V _th1 , a comparator (abbreviated as CMP)
When 1 outputs "1" and is smaller than the threshold level V _{th2 which} is lower than the threshold level V _th1 , the comparator (CMP) 2 outputs "1". The outputs of CMP1 and CMP2 are input to the OR circuit 17, and its output 1
7a is input to a D flip-flop (abbreviated as FF) 18 and is latched at the rising edge of the clock CLK and becomes reproduced data DT1.

[0005]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
In the data regenerator 01, the reproduction signal from the head amplifier
Data output when HA level fluctuations and jitter increase
An error occurs. This is shown in FIG. That is, black
CLK rising edge (t₁, T₂... t_Ten) Focus on
Then, in this case, the output PR of the equalizer EQ has a dotted waveform.
In the ideal state, the correct data output is 0011011.
110. However, the level fluctuation of the reproduced signal and the jitter
If the EQ output PR is shifted like the solid line waveform due to
Time t ₇Erroneous setting of three-value discrimination in, that is, -1 is 0
Become. As a result, the data output 01a becomes 00110101.
It will be 10. In this way, the head amplifier playback signal
Signal level fluctuation and jitter have a synergistic effect, and data output
Makes DT1 error-prone.

Therefore, an object of the present invention is to provide a magnetic recording data reproducing apparatus capable of reducing such a data error.

[0007]

In order to solve the above-mentioned problems, in the magnetic recording data reproducing apparatus according to claim 1, the RLL is used.
Equalizing means (equalizer EQ, etc.) for equalizing a reproduction signal (HA, etc.) obtained by a head and a head amplifier from a magnetic disk, etc., whose code is magnetically recorded by NRZI modulation, into a PR-IV equalized waveform signal. , A clock generation means (clock generator 03 etc.) for generating a data reproduction clock signal (CLK etc.) from the reproduction signal, and a data reproduction means (reproduced data (DT1 etc.) from the equalized waveform signal and the clock signal ( In the magnetic recording data reproducing device, the magnetic recording data reproducing device is provided with a ternary discriminator / data reproducer 01A, etc.) and a tegode means (decoder 02 etc.) for converting the reproduced data into original data (DT2 etc.) before RLL encoding. data reproducing means (such as V _th1) at least said waveform signal is in a predetermined equalization first threshold depending on whether larger or not, respectively "1" A first comparison means for outputting a "0" (like the comparator 1), the equalized waveform signal is the first lower than the threshold value predetermined second threshold value (V
_{th 2,} etc.), depending on whether a smaller or not, each "1",
Second comparing means (comparator 2, etc.) for outputting “0” and first storing means for shifting the output value of the first comparing means at each rising time of the clock signal while storing them in time series. (A shift register 100 including flip-flops 3 to 5) and a second storage unit (flip-flop) that shifts while storing the output value of the second comparison unit at each rising time of the clock signal in time series. 6-8) and a predetermined data pattern detected in each of the stored data strings in the first storage means and the second storage means, and an erroneous determination of correcting the determined data pattern as an error. And a detection correction means (300, etc.).

According to a second aspect of the magnetic recording data reproducing apparatus of the present invention, in the magnetic recording data reproducing apparatus of the first aspect, the erroneous determination detection / correction means is at least the first and the first.
When a data pattern of "0", "1", "0" is detected (via the AND circuits 9 and 10) in each stored data string in the second storage means, this data pattern is
According to the inclination of the equalized waveform signal corresponding to this data pattern portion (detected via the delay circuits 19 and 20, the comparator 21 and the like) (AND circuits 11 to 14, OR
Via circuits 15 to 17), "1", "1", "0"
Alternatively, it should be corrected to "0", "1", "1".

According to a third aspect of the magnetic recording data reproducing apparatus of the present invention, in the magnetic recording data reproducing apparatus of the first aspect, the erroneous determination detection / correction means is at least the first and the first.
When a data pattern of "1", "1", "1" is detected (via the AND circuits 29, 30 etc.) in each stored data string in the second storage means, this data pattern According to the slope of the equalized waveform signal corresponding to this data pattern portion (detected via the delay circuits 19 and 20, the comparator 21 and the like) (NAND circuits 31 to 3).
4, through AND circuits 35 to 38, OR circuit 17 and the like), "1", "1", "0" or "0", "1",
Make sure it is corrected to "1".

[0010]

In the RLL code such as the 1,7 code, one or more "0" is inserted between "1" and "1". When a head amplifier reproduction signal obtained from a magnetic disk magnetically recorded by NRZI modulation is waveform equalized into a PR-IV equalized waveform signal, the level at the sampling point by the clock signal is +
It will be one of the levels 1, 0, -1. Further, the +1 level or the -1 level originally always appears at two consecutive sampling points, and never appears only once or three consecutive times.

In reality, however, the level erroneous determination at the sampling point occurs due to the level fluctuation and the jitter of the head amplifier reproduction signal as described above. Among them, the erroneous setting pattern with a high possibility may be a case where the +1 (or -1) level appears only once and a case where the level appears three times in succession. FIG. 1 is a principle block diagram of a ternary value discriminating / data reproducing device 01A according to the present invention, and corresponds to FIG. In the present invention, the EQ output (equalized waveform signal P
R) +1 level comparator (CMP)
The shift registers 100 and 200 formed of D flip-flops are provided on the respective output sides of the comparator (CMP) 2 which detects the level 1 and the level -1 as well, and at the three consecutive sampling points in the past for each rising edge of the clock CLK. The shift register 100, 200 is provided with an erroneous determination detection / correction unit 300 which stores the level determination result and detects and corrects the erroneous determination pattern when the content is the above-described erroneous determination pattern.
The data output from the OR circuit to the OR circuit 17 is corrected.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 is a three-value discrimination / data regenerator 01A of FIG.
2 is a detailed circuit diagram of a three-value discrimination / data regenerator (01A-1) as the first embodiment (claim 2) of the present invention, and FIG. 3 is a waveform diagram for explaining the operation of the main part of FIG. In FIG. 3, the solid line waveform shows the actual (distorted by level fluctuation or jitter) waveform, and the dotted line shows the original (ideal state) waveform.

The structure and operation of FIG. 2 will be described below with reference to FIG. 3. When the equalized waveform signal PR as the output of the equalizer EQ (not shown) is larger than the threshold value V _th1 , CMP1 becomes " 1 "is output, and if it is smaller than the threshold value V _th2 , CMP2
Outputs "1". CMP at the rising edge of clock CKL
The output of 1 is latched in the flip-flop (FF) 3,
At the same time, the output of FF3 is latched by FF4 through the OR circuit 15, and the output of FF4 is latched by FF5. The set of FFs 3 to 5 is the shift register 100 of FIG.
Equivalent to.

Similarly, at the rising edge of the clock CLK, CMP2
Is latched by FF6, and at the same time, the output of FF6 is O
It is latched by FF7 through the R circuit 16, and the output of FF7 is latched by FF8. The set of FFs 6 to 8 corresponds to the shift register 200 in FIG. FF3, FF
When the outputs of 4 and FF5 are "0", "1", and "0", respectively, this is judged to be an erroneous determination, and the AND circuit 9 outputs "1".

Similarly, when the outputs of FF6, FF7 and FF8 are "0", "1" and "0" respectively, this is judged to be an erroneous judgment,
The AND circuit 10 outputs "1". On the other hand, the equalized waveform signal PR is transferred to the delay circuit (abbreviated as DLY) 19 for time T ₁
Delay and delay by DLY20 for time T ₂ . In this case, the sampling period, that is, the period of the clock CLK is T _S , and the times T ₁ and T ₂ are determined as in the following equation.

[0016]

## EQU1 ## T ₁ = 2T _S − (ΔT / 2) T ₂ = 2T _S + (ΔT / 2) ΔT≈T _S Comparator (CMP) 21 has DLY 19 and DLY 20.
By comparing the outputs of (1) and (2), "1" is output when the slope of the equalized waveform signal is positive, and "0" is output when it is negative, as a signal of * 1. The signal * 1 is given to the AND circuits 12 and 13. Further, the inverter circuit 22 inverts the output of the CMP 21 and outputs it as a signal of * 2. The signal * 2 is given to the AND circuits 11 and 14. However, here it is focused on the equalized waveform signal time prior time from the present time 2T _S.

When the output of the AND circuit 9 is "1" and the output signal * 1 of the comparator 21 is "1", FF3, FF
4, it is determined that the correct outputs of FF5 are "0", "1", "1", and the output of the AND circuit 13 becomes "1". Further, the output of the AND circuit 9 is "1" and the output of the comparator 21 is "0" (that is, the output signal of the inverter circuit 22 *).
When 2 is "1"), it is judged that the correct outputs of FF3, FF4, FF5 are "1", "1", "0", and the output of the AND circuit 11 becomes "1".

Similarly, when the output of the AND circuit 10 is "1" and the output of the comparator 21 is "1", FF6, FF7,
It is determined that the correct output of the FF8 is "1", "1", "0", and the output of the AND circuit 12 becomes "1". Also,
When the output of the AND circuit 10 is "1" and the output of the comparator 21 is "0", it is determined that the correct outputs of FF6, FF7 and FF8 are "0", "1" and "1", and the AND circuit 14 Output becomes "1".

The OR circuit 15 causes the AND circuit 1
The signal obtained by the OR condition of the output of 1 and the output of FF3 is input to FF4. Similarly, the OR circuit 16 causes A
A signal obtained by the OR condition of the output of the ND circuit 12 and the output of the FF6 is input to the FF7. Finally OR circuit 1
7, AND circuit 13, AND circuit 14, FF5,
The OR condition of each output of FF8 is obtained, and this is FF18
Corrected data D latched by the clock rising edge
Outputs T1.

FIG. 4 is a detailed circuit diagram of a ternary data discriminating / data reproducing device (01A-2) as a second embodiment (claim 3) of the ternary data discriminating / data reproducing device of FIG. 1, and FIG. 4 is a waveform diagram for explaining the operation of the main part of FIG. Also in FIG. 5, the solid line waveform shows the actual waveform, and the dotted line shows the waveform in the ideal state. Next in FIG.
The configuration and operation of FIG. 4 will be described with reference to FIG. CMP
Means having the same reference numerals as those in FIG. 2, such as 1, CMP2, DLY19, DLY20, and CMP21, are the same as those in FIG. However, in FIG. 4, the output signal * 1 of the CMP 21 is given to the NAND circuits 31 and 34, and the inverter circuit 2
The output signal * 2 of 2 is given to the NAND circuits 32 and 33.

At the rising edge of the clock CLK, the output of CMP1 is latched in FF3, at the same time the output of FF3 is latched in FF4 through the AND circuit 35, and the output of FF4 is F.
Latched to F5. Similarly, at the rising edge of the clock CLK, the output of CMP2 is latched by FF6, and at the same time, the output of FF6 is latched by FF7 through the AND circuit 36, and F
The output of F7 is latched by FF8.

When the outputs of FF3, FF4 and FF5 are "1", "1" and "1" respectively, this is judged to be an erroneous judgment,
The AND circuit 29 outputs "1". Similarly FF6, F
When the outputs of F7 and FF8 are "1", "1", and "1", respectively, this is determined to be an erroneous determination, and the AND circuit 30 outputs "1". When the output of the AND circuit 29 is "1" and the output of the comparator 21 is "1", FF3, FF4, FF
It is determined that the correct outputs of 5 are "0", "1", and "1", and the output of the NAND circuit 31 becomes "0". Also, A
When the output of the ND circuit 29 is "1" and the output of the comparator 21 is "0", it is determined that the correct outputs of FF3, FF4, FF5 are "1", "1", "0", and the NAND circuit 33 is used. Output becomes "0".

Similarly, when the output of the AND circuit 30 is "1" and the output of the comparator 21 is "1", FF6, FF7,
It is determined that the correct output of the FF8 is "1", "1", "0", and the output of the NAND circuit 34 is "0". When the output of the AND circuit 30 is "1", the comparator 2
When the output of 1 is "0", it is judged that the correct outputs of FF6, FF7, FF8 are "0", "1", "1", and NA
The output of the ND circuit 32 becomes "0".

The signal obtained by the AND condition of the output of the NAND circuit 31 and the output of the FF3 is input to the FF4 by the AND circuit 35. Similarly, the AND circuit 36 causes the output of the NAND circuit 32 and the output of the FF 6 to be AN.
The signal obtained under the D condition is input to the FF7. AND
AND signal 37a of the output of NAND circuit 33 and the output of FF5 by circuit 37, and NAN by AND circuit 38
AND signal 38a of the output of D circuit 34 and the output of FF8
The OR signal 17a is obtained by the OR circuit 17, and the FF 18 latches this at the rising edge of the clock and outputs the corrected reproduction data DT1.

[0025]

As described above, the equalized waveform signal of PR-IV is obtained through the equalizer from the magnetic disk on which the RLL code such as the 1,7 code is magnetically recorded by the NRZI modulation to obtain the data. When reproducing, an erroneous determination pattern that is highly likely to be detected in the three-value determination is detected and corrected, so that the read error can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing the principle of a three-value discrimination / data regenerator according to the present invention.

2 is a detailed circuit diagram as a first embodiment of the three-value discrimination / data regenerator of FIG.

FIG. 3 is a waveform diagram for explaining the operation of the main part of FIG.

FIG. 4 is a detailed circuit diagram as a second embodiment of the three-value discrimination / data regenerator of FIG.

5 is a waveform diagram for explaining the operation of the main part of FIG.

FIG. 6 is a schematic configuration diagram of a magnetic recording data reproducing apparatus using the equalized waveform signal PR-IV.

FIG. 7 is a block diagram of a conventional three-value discrimination / data regenerator.

FIG. 8 is a waveform diagram for explaining the operation of FIG.

FIG. 9 is a waveform diagram for explaining the error occurrence of FIG.

[Explanation of symbols]

HA head amplifier reproduction signal AGC automatic gain control amplifier EQ equalizer PR, PR-IV equalized waveform signal (EQ output) 01A (01A-1, 01A-2) 3-value discrimination / data reproducer DT1 reproduction data 02 decoder DT2 Original data 03 Clock generator CLK Clock V _th1 , V _th2 Threshold level (threshold) 1, 2 Comparator (CMP) 3-8 D flip-flop (FF) 9-14 AND circuit 15-17 OR circuit 18 D flip-flop (FF) 19,20 Delay circuit (DLY) 21 Comparator (CMP) 22 Inverter circuit 29,30 AND circuit 31-34 NAND circuit 35-38 AND circuit 100,200 Shift register 300 Misjudgment detection correction means

Claims (3)

[Claims] 1. A reproduction signal obtained by a head and a head amplifier from a magnetic disk or the like on which RLL code is magnetically recorded by NRZI modulation is equalized into an equalized waveform signal of partial response class IV (hereinafter referred to as PR-IV). Equalizing means, a clock generating means for generating a clock signal for data reproduction from the reproduced signal, a data reproducing means for reproducing data from the equalized waveform signal and the clock signal, before RLL encoding the reproduced data In the magnetic recording data reproducing device provided with the decoding means for converting the original data into the original data, the data reproducing means respectively determines whether the equalized waveform signal is larger than a predetermined first threshold value. 1 "and" 0 "for outputting first comparing means, and the equalized waveform signal has a predetermined second threshold value lower than the first threshold value. Second comparison means for outputting "1" and "0" respectively, depending on whether or not it is stored, and an output value of the first comparison means for each rising time of the clock signal while being stored in time series. A first storage means for shifting; a second storage means for shifting the output value of the second comparing means for each rising time of the clock signal while storing the output value in a time series; the first storage means; Magnetic recording data reproduction characterized by including erroneous determination detection and correction means for correcting a predetermined data pattern detected in each stored data string in the second storage means by determining it as an error. apparatus. 2. The magnetic recording data reproducing apparatus according to claim 1, wherein the erroneous determination detection / correction means is at least the first and second
"0" in each stored data string in the storage means of
When a data pattern of "1" or "0" is detected, this data pattern is changed to "1", "1", according to the slope of the equalized waveform signal corresponding to this data pattern portion.
A magnetic recording data reproducing apparatus characterized by being corrected to "0" or "0", "1", "1". 3. The magnetic recording data reproducing apparatus according to claim 1, wherein the erroneous determination detection correcting means is at least the first and second
"1" in each stored data string in the storage means of
When a data pattern of "1" or "1" is detected, this data pattern is converted into "1", "1", or "1" depending on the slope of the equalized waveform signal corresponding to this data pattern portion.
A magnetic recording data reproducing apparatus characterized by being corrected to "0" or "0", "1", "1".