JPH07219846A - Associative memory and data processor - Google Patents

Abstract

PURPOSE:To provide a technology to surely relieve an associative memory or an LSI including this associative memory. CONSTITUTION:A memory line valid/invalid flag generating part 103 and an AND circuit 111 serve as the means which invalidate the deciding result of an address comparing part 102 based on the information on a defective part. Even if the presence is decided for such an address that is inputted for a searching purpose, the operation is limited to read the data out of a data storage means by invalidating such deciding result. Thus it is possible to relieve an associative memory including such a defect that cannot be relieved in a redundant constitution.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an associative memory and a defect relief technique therefor, and more particularly to a technique effectively applied to a cache memory included in a data processing device such as a single chip microcomputer.

[0002]

2. Description of the Related Art An associative memory that determines whether or not an address input for search exists and outputs corresponding data based on the determination result can be used as a cache memory. . A typical cache memory is called a set associative because the cache is divided into separate sets of lines, each set containing a certain small number of lines.
An address tag (also simply referred to as "tag") is attached to each block of the cache, and the address of the block frame is held therein. CPU (central processing unit)
When accessing the cache, the tag value is compared with the block frame address. This comparison is made for blocks that may result in cache hits. In the case of a cache miss, block replacement is performed. In that case, as a block replacement method, a random method in which candidate blocks are randomly selected or access to a block is recorded so that necessary information is not discarded immediately. An example of the LRU method is one in which blocks that have not been used for a time are targeted for replacement.

An example of a document describing the cache memory is "High Performance Computer Architecture (Page 31-)" issued by Maruzen Co., Ltd. on March 30, 1989.

By the way, generally, in order to improve the yield of the semiconductor memory device, the redundant structure of the memory is effective. That is, a spare bit or spare element is provided as a redundant configuration, and when a defect is found in the wafer probe test stage, the defective circuit portion is switched to a predetermined spare element. Information for such switching is programmed in a redundant program circuit including electric fuses and laser fuses, whereby a plurality of program circuits are arranged in response to the number of bits of an input address which enables defect relief. It Redundant relief is not performed in the state where all the fuses are not blown, but when the fuses are blown, the defective circuit portion corresponding thereto is addressed so as to be switched to a predetermined spare element. The semiconductor memory device thus defectively repaired is regarded as a good product.

[0005]

The defect remedy technique with the redundant configuration as described above can also be applied to an associative memory. However, in an associative memory mounted on an LSI such as a single-chip microcomputer, a large redundant memory cannot be mounted in general because of the chip area. Therefore, when the defective area is large, the redundant configuration as described above is used. In some cases, it may not be possible to provide sufficient relief. If such relief is not possible, the LSI
Is considered defective. That is, LS including associative memory
The main factor that hinders the improvement of the yield of I is
Found by the inventor.

An object of the present invention is to provide a technique for accurately relieving an associative memory or an LSI including it. Another object of the present invention is to improve the yield of a data processing device including an associative memory.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0008]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, a discriminating means for discriminating whether or not the address inputted for the search matches the tag information, and a data storing means for outputting the corresponding data based on the discrimination result. Including, when the associative memory is configured, means for invalidating the discrimination result of the discrimination means based on the information about the defective portion is provided. At this time, the invalidating means includes a flag generating means for generating a flag indicating the defective portion, and a logic circuit for taking a logic between the flag generated by this means and the discrimination result of the discriminating means. Can be included. Furthermore, the cache memory configured as described above can be applied to the cache memory in the data processing device.

[0010]

According to the above-mentioned means, the means for invalidating the discrimination result of the discrimination means is such that, in the discrimination of the discrimination means, it is determined that the address input for the search exists in the cache. Also, by invalidating such a determination result, it acts to prohibit access to the data storage means. This enables the associative memory including a defect that cannot be repaired by the redundant configuration and further the LSI including such an associative memory.

[0011]

FIG. 2 shows a microcomputer which is an embodiment of the present invention.

The microcomputer shown in FIG.
Although not particularly limited, it is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

An instruction cache memory 21 is provided in order to shorten the time when the same instruction is fetched from the main memory unit 22 in which the instruction to be executed by the CPU (central processing unit) is stored. The output of this instruction cache memory 21 is
The operation control signal of each unit is generated by being decoded by the instruction decoder 23 in the subsequent stage. A part of the decode output of the instruction decoder 23 is taken in by the program counter 24, and the address of the instruction to be executed next is determined.

A CPU 29 including an arithmetic unit 28 for performing a logical operation, a shifter 27 for shifting data in synchronization with a clock signal, a general-purpose register 26 used as a temporary storage area of data, and the like. Is provided,
Its constituent blocks are coupled by a data bus so that they can exchange data with each other. The data cache memory 25 is used to fetch the data to be calculated from the outside, so that the reading time of the same data is shortened. In such a microcomputer, the operation of each functional block is performed by this LS.
A clock signal CK generated outside or inside I is used as a reference.

Although not particularly limited, the instruction cache memory 21 employs a set associative method in which the cache is divided into separate sets, and each set includes a certain small number of lines. To be done. Here, the set means a set composed of two or more blocks on the cache. Blocks are placed anywhere in the set after being associated with the corresponding set. The selection of the set is usually performed by extracting some bits of the block frame address. If there are n blocks in one set, n
Called the Way Set Associative. Also, if you can put the block anywhere on the cache,
It is called the full associative. Each block of the instruction cache memory 21 has a tag, which holds a block frame address. When the instruction cache memory 21 is accessed by the CPU 29, the tag is compared with the block frame address.

When the address input for the search exists in the instruction cache memory 21, the tag matches the block address, and it is regarded as a cache hit. In the case of a cache hit, the instruction held as data in the instruction cache memory 21 is read,
It is transmitted to the instruction decoder 23. On the other hand, when the address input for the search does not exist in the instruction cache memory, it is regarded as a mishit, the instruction corresponding to the address is read from the main memory unit, and it is transmitted to the instruction decoder 23. At the same time, the storage state of the instruction cache memory 21 is updated.

Here, according to the prior art, when the storage portion of the instruction cache memory 21 contains a defect, for example, when the defect cannot be repaired by a redundant configuration, such an instruction cache memory 21 is used. Including microcomputer, even when other parts work normally,
It is considered defective. On the other hand, in the present embodiment, in the case where the storage unit of the instruction cache memory 21 includes a defect as described above, control is performed so that access to the defective unit does not occur. By being truncated so that it does not participate in the cache operation,
The instruction cache memory 21 and the microcomputer including it are saved. In other words, it is relieved as a microcomputer equipped with an instruction cache memory having a smaller capacity than when there is no defect. For example, when the instruction cache memory 21 has 64 entries in the full associative system, if a defect is found in wafer probing, the defective portion is not used, so that the instruction cache memory of 48 entries can be used. Can be relieved as a microcomputer including. Further, in the case of the n-way set associative method, if a defect is found in wafer probing, the defective part is not used so that n−j (j = 1 to n) is set in the set of the corresponding part. -1)
Way set or n-in all memories
It can be relieved by using the j-way set.

FIG. 1 shows the instruction cache memory 21.
A configuration example of is shown.

As shown in the figure, the instruction cache memory 21 includes, but is not limited to, a replacement set determination logic unit 101, an address comparison unit 102, and a data memory unit 107.

The replacement set judgment logic unit 101 fetches a part of the address 113 input to the instruction cache memory 21 for searching and generates a set number 108 corresponding thereto. An address comparison unit 102 for comparing one or more address tags corresponding to the generated set number with a part of the input address 113 is arranged at the subsequent stage of the replacement set determination logic unit 101.

The address comparison unit 102 outputs the set number 108 output from the replacement set determination logic unit 101.
1 or more address tags corresponding to the input address 11
Compare with 3. In this address comparison, if there is an address tag that matches the input address 113, it is a cache hit, and conversely, if there is no matching address tag, it is a cache miss. In the case of a cache hit, the address comparison unit 105
Causes the match signal 105 to be asserted at a high level, for example.

The data memory section 107 receives a match signal 105 according to the address comparison of the address comparison section 102.
When is asserted to a high level, the corresponding data line (stored information) is output. This output data is transmitted to the instruction decoder 23 shown in FIG. 1 as an instruction corresponding to the input address 113.

Further, in this embodiment, as the invalidation means for invalidating the determination result of the address comparison unit 102, the memory line valid / invalid flag generation unit 103 and a plurality of AND circuits to which the output flags are transmitted. 111 is provided. Memory line valid / invalid flag generator 1
When the flag output from 03 is high level, the corresponding AND circuit 111 is activated. On the contrary, when the flag is low level, the match signal 1
05 transmission is blocked.

Although not particularly limited, the memory line valid / invalid flag generator 103 includes a plurality of fuse circuits as information storage means. Although not particularly limited, a plurality of series-connected circuits of the fuse 201 and the resistor 206 are formed in this fuse circuit, as shown in FIG. The number of serially connected circuits is not particularly limited, but corresponds to the number of lines of the data memory unit 107. The other end of the fuse 201 is coupled to the high-potential side power supply Vdd, and the other end of the resistor is coupled to the ground GND. In the state where the fuse 201 is not cut, the memory line valid / invalid flag 104 is set to the high level, but the fuse cutting circuit 202 causes the fuse 201 to operate.
The memory line valid / invalid flag 104 is set to a low level in a state in which is disconnected. In wafer probing of the microcomputer of the present embodiment, if a defect is found in the data memory section 107, the fuse 201 corresponding to the data line of the defective section is blown to prohibit the use of the defective section. . The fuse cutting circuit 202 is not particularly limited, but the fuse 2
01 by supplying an overcurrent to the fuse 2
A method of electrically cutting 01 can be adopted.

Next, the operation of this embodiment will be described in detail.

First, in the wafer probing, when the data memory unit 107 and the replacement set determination function and the address comparison function corresponding to the memory unit 107 are determined to be normal, all of the memory valid / invalid flag generation unit 103. Fuse 201 is not blown. In that case, since all the memory line valid / invalid flags 104 are set to the high level, the logical output from the address comparison unit 102 can be transmitted to the data memory unit 107 in the subsequent stage via the AND circuit 111. .

When the address 113 is input to the instruction cache memory 21 based on the decoded output of the program counter 24 shown in FIG. 2, it is fetched by the replacement set determination logic unit 101 and the address comparison unit 102. Be done. When a part of the converted address is taken in by the replacement set determination logic unit 101, the replacement set determination logic unit 1
01 generates a set number corresponding to the input address. Then, the address comparison unit 102 compares one or more address tags referred to based on the set number output from the replacement set determination logic unit 101 with a part of the corresponding address. When the corresponding data is stored in the instruction cache memory 21, the match signal 105 is asserted when the address tag and the input address 113 match, whereby the corresponding data is read from the data memory unit 107. It

On the other hand, when the corresponding data is not stored in the associative memory, the address tag and the address do not match in the address comparison in the address comparison unit 102, so that the match signal 105 is negated. In this state, no data is read from the data memory unit 107. At this time, all AND circuits 1
The miss signal 109, which is the logical output of the NOR circuit 112 for obtaining the logical sum of the outputs of 11, is asserted to the high level, and the data of the address is read from the main memory located in the lower part of the associative memory. Also, in that case, do not discard the random method that randomly selected candidate blocks and the information that you need immediately,
Block replacement is performed by a method such as the LRU method in which access to a block is recorded and the block that has not been used for the longest time is targeted for replacement. That is, the replacement set determination logic unit 101 is excluded except for the portion invalidated by the memory line valid / invalid flag.
Corresponding set number is selected, and the address tag information is stored in the corresponding address tag. Then, the data corresponding to the corresponding tag is stored in the corresponding line of the data memory unit 107.

Next, in the wafer probing, when some defects in the data memory unit 107 and the replacement set determination function and the address comparison function corresponding to the memory unit 107 are recognized, the memory valid / invalid flag is generated. By cutting the corresponding fuse 201 in the portion 103, use of the defective portion is restricted. That is, in the memory line valid / invalid flag generation unit 103, the flag at the location where the fuse 201 is blown is set to low level, so that the activation of the corresponding AND circuit 111 is blocked and the output of the corresponding data line is output. Is prohibited.

In this state, even if the match signal 105 is asserted to the high level as a result of the address comparison in the address comparing section 102, the AND circuit 111 corresponding to the match signal 105 is inactivated. No data is read from the data memory unit 107.
At this time, since the miss signal 109 is asserted to the high level, the corresponding data is read from the main memory located in the lower part of this associative memory. At about the same time, the content stored in the associative memory is updated.

According to the above embodiment, the following operational effects can be obtained.

(1) As a means for invalidating the determination result of the address comparing section 102 based on the information about the defective portion, the memory line valid / invalid flag generating section 103 is provided so that it is inputted for the search. Even when it is determined that there is an address, the determination result is invalidated to limit the data read from the data storage unit, and the associative memory including a defect that cannot be repaired by the redundant configuration, It can be relieved as a small capacity cache memory.

(2) Further, a memory line valid / invalid flag generating section 103 as a flag generating means for generating a flag indicating the defective portion, and the generated flag and the output from the address comparing section 102. By configuring the invalidation means including the AND circuit 111 for obtaining the logical product, it is possible to accurately perform the invalidation of the determination result as described above, although it is a relatively simple circuit.

(3) Further, the cache memory is
By applying it to the instruction cache memory of the microcomputer, it is possible to improve the yield due to the defect of the cache memory. In other words, even when a defect that cannot be repaired by the redundant configuration is included, by repairing the defect, one kind of associative memory or a microcomputer including the same has a plurality of ranks with different cache memory capacities. Product development can be performed efficiently.

3 and 4 show another example of the configuration of the memory line valid / invalid flag generating section 103.

For example, the memory line valid / invalid flag is set in the fuse cutting circuit 2 as shown in FIG.
Although it is relatively simple to form using the fuse 201 including 02 and the resistor 206, an active element such as a transistor can be applied instead of the resistor 206. Further, instead of the fuse circuit, a PROM (programmable read only memory) or an EPROM
(Electrical programmable programmable read only
An information storage means such as a memory) or an EEPROM (electrically erasable and programmable read only memory) can be applied.

Further, as shown in FIG. 3B, a register 301 capable of setting a state indicating a memory line valid / invalid flag may be incorporated from the outside of the associative memory. In this case, the flag setting to the register 301 is
When the system including the CPU 29 is activated, the CPU 29
Done by

Further, in the configuration shown in FIG. 4, the memory line valid / invalid flag generator 103 shown in FIG.
Alternatively, the function of the AND circuit 111 is changed to the address comparison unit 102.
It is designed to be installed inside. A comparator 304 for comparing the input address 113 and the address tag 303 is provided, and the logical output of the comparator 304 is output as the coincidence signal 105 by passing through the AND circuit 402 in the subsequent stage. Has become. Then, a data valid / invalid flag generation unit 302 for generating a flag indicating that the information of a certain block in the cache is invalid (this is called a data valid / invalid flag) is provided, and the valid bit is set. If not, the coincidence signal 105 is not output. A memory line valid / invalid flag generating section 301 is provided so as to be provided side by side with the data valid / invalid flag generating section 302. The logic output of the memory line valid / invalid flag generating section 301 and the data valid / invalid The logical product of the flag and the flag generation unit 302 is obtained by the AND circuit 401 in the subsequent stage. And this AND circuit 4
The AND circuit 402 obtains the logical product of the logical output of 01 and the comparative output of the comparison circuit 304. Even with such a configuration, the transmission of the logic output of the comparator 304 as the determination means can be limited based on the flag, and therefore the same effect as that of the above embodiment can be obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and needless to say, various modifications can be made without departing from the scope of the invention. Yes.

For example, in the above embodiment, the memory line valid / invalid flag is set for each data line, but it may be set for each way (block). In the above embodiment, the instruction cache memory 2
Although the case of application to No. 1 has been described, the defect relief of this data cache memory 25 can be performed by applying it to the data cache memory 25 in the same manner.

In the above description, the case where the invention made by the present inventor is mainly applied to the built-in cache memory of the microcomputer, which is the field of application of the background, has been described, but the present invention is not limited thereto. , LSI in which associative memory itself is integrated into one chip
Alternatively, it can be widely applied to various data processing devices including an associative memory.

The present invention can be applied on condition that at least a data storage means is provided.

[0043]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, even if it is determined that the address input for the search exists by providing a means for invalidating the determination result of the above-mentioned determination means based on the information about the defective portion, it is possible to By invalidating such a determination result, data reading is prohibited by limiting data reading from the data storage unit, so that the associative memory including a defect that cannot be repaired by the redundant configuration can be repaired. .

Further, it includes a flag generating means for generating a flag indicating the defective portion, and a logic circuit for taking a logic between the flag generated by this means and the discrimination result of the discriminating means. By configuring the invalidation means, it is possible to accurately invalidate the determination result as described above.

By applying the cache memory configured as described above to a data processing device such as a microcomputer, the yield of the data processing device can be improved by repairing defects in the cache memory. .

[Brief description of drawings]

FIG. 1 is a configuration block diagram of an instruction cache memory applied to a microcomputer which is an embodiment of the present invention.

FIG. 2 is a configuration block diagram of a microcomputer that is an embodiment of the present invention.

FIG. 3A is a circuit diagram of a configuration example of a memory line valid / invalid flag generation unit included in the instruction cache memory;
FIG. 9B is a block diagram of another configuration example of the memory line valid / invalid flag generation unit.

FIG. 4 is a block diagram of another configuration example of the memory line valid / invalid flag generation unit.

[Explanation of symbols]

 21 instruction cache memory 22 main memory 23 instruction decoder 24 program counter 25 data cache memory 26 register 27 shifter 28 arithmetic unit 101 replacement set determination logic unit 102 address comparison unit 103 memory line valid / invalid flag generation unit 104 valid / invalid flag 105 match signal 107 data memory section 108 data 109 miss signal 111 AND circuit 112 NOR circuit 201 fuse 202 fuse cutting circuit 203 memory line valid / invalid flag 206 resistance 301 memory line valid / invalid flag generation section 302 data valid / invalid flag generation section 303 address Tag 304 Comparator Vdd High potential side power supply GND Ground

Claims (3)

[Claims] 1. A discriminating means for discriminating whether or not the address inputted for the search matches the tag information, and a data storing means for outputting corresponding data based on the discrimination result. An associative memory including the invalidation means for invalidating the determination result of the determination means based on preset information about the defective portion. 2. The invalidating means is a flag generating means for generating a flag indicating a defective portion, and a logic for performing a logical operation between the flag generated by this means and the discrimination result of the discriminating means. The associative memory of claim 1 including a circuit. 3. A main memory, a central processing unit that can access the main memory, and information temporarily accessed by the central processing unit interposed between the central processing unit and the main memory. A data processing device including a cache memory for storing in the data processing device, wherein the associative memory according to claim 1 or 2 is included as the cache memory.